diff --git a/examples/hdl4se_riscv/de1/clk/clk100M.v b/examples/hdl4se_riscv/de1/clk/clk100M.v index 95ee73a51cf2e1e34c073f21cd202cd6a38b9fbb..2b51bd68145401be40ad3fb3c2396e28ba9f5fdf 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M.v +++ b/examples/hdl4se_riscv/de1/clk/clk100M.v @@ -2,7 +2,7 @@ // GENERATION: XML // clk100M.v -// Generated using ACDS version 13.1 162 at 2021.08.27.17:20:30 +// Generated using ACDS version 13.1 162 at 2021.08.28.11:01:41 `timescale 1 ps / 1 ps module clk100M ( @@ -68,7 +68,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v b/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v index b3c90990aedbe4da4977b93e406483dfda40562b..7338770443fa629cfd4fdf3e79ed255362f8e59c 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v +++ b/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v @@ -22,7 +22,7 @@ module clk100M_0002( .reference_clock_frequency("50.0 MHz"), .operation_mode("direct"), .number_of_clocks(2), - .output_clock_frequency0("100.000000 MHz"), + .output_clock_frequency0("50.000000 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), .output_clock_frequency1("75.000000 MHz"), diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl b/examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl index 892bc36af208980191dc01147c60d8f23e3d0786..ec50b3dd6cb84e039acd357b021ceb947775c6a0 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # Auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh b/examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh index 3c004a344570e39477fddfefcfb608468382d1b8..fc0f9bfb8005dc97d551db3fb8c143a0514dc145 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # ncsim - auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo b/examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo index 6a8e7f845e376e68d45725e5e9344ceadeb4352a..9bd4953c7dfebf51aaffebefcbc372a3d44b2c60 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo @@ -210,7 +210,7 @@ module clk100M clk100m_altera_pll_altera_pll_i_1096.n_cnt_odd_div_duty_en = "false", clk100m_altera_pll_altera_pll_i_1096.number_of_clocks = 2, clk100m_altera_pll_altera_pll_i_1096.operation_mode = "direct", - clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "100.000000 MHz", + clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "50.000000 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency1 = "75.000000 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency10 = "0 MHz", clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency11 = "0 MHz", diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl b/examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl index e81810ab23ed239abbc4f76b1d4015efff10ebf5..c9072bae8e3c2938b05f845c6fff5dedf4ad76ba 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # Auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh b/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh index 30d306cbe72bfefd1bc159dc615c07ca4c1bbbd2..7a7d54547290789a660c0d5b9a100a81809a03d3 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # vcs - auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh b/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh index 63a581eed3ba75487968071d657c128a18581b8f..9d9eb23ac34086dcc02aeeaeb2cf606c417f99a5 100644 --- a/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 13.1 162 win32 2021.08.27.17:20:37 +# ACDS 13.1 162 win32 2021.08.28.11:01:49 # ---------------------------------------- # vcsmx - auto-generated simulation script diff --git a/examples/hdl4se_riscv/de1/clk100M.xml b/examples/hdl4se_riscv/de1/clk100M.xml index 3af333ade56099cd20ed256b54e0cd334cf807d8..cdabb27e83d3d5a7e678451644f7d0e54dc12573 100644 --- a/examples/hdl4se_riscv/de1/clk100M.xml +++ b/examples/hdl4se_riscv/de1/clk100M.xml @@ -19,7 +19,7 @@ - + diff --git a/examples/hdl4se_riscv/de1/de1_risc.mpf b/examples/hdl4se_riscv/de1/de1_risc.mpf index 137f8b6eb918312d28a2bc5f0a5a194cdfb101e7..d8edd2002f2d84eb5c69333833678538dac86b3f 100644 --- a/examples/hdl4se_riscv/de1/de1_risc.mpf +++ b/examples/hdl4se_riscv/de1/de1_risc.mpf @@ -454,7 +454,7 @@ Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 co Project_File_1 = C:/altera/13.1/quartus/eda/sim_lib/220model.v Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1382637203 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_2 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v -Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630049086 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630049086 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_3 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629969062 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_4 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v @@ -470,9 +470,9 @@ Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 co Project_File_9 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1630042952 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_10 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v -Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1630053824 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630053824 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_11 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v -Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1630049096 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1630049096 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_12 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1629969030 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_13 = D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v diff --git a/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt b/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt index 7763d3e74d9fe9a08b3d3ea0f4b3fd9772c43859..56051246aa91db567d45a394e468b233e2152ff2 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt @@ -1,5 +1,5 @@ Assembler report for de1_riscv -Fri Aug 27 17:23:28 2021 +Sat Aug 28 10:56:11 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Aug 27 17:23:28 2021 ; +; Assembler Status ; Successful - Sat Aug 28 10:56:11 2021 ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; @@ -92,8 +92,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+--------------------------------------------------------------------+ ; Device ; 5CSEMA5F31C6 ; -; JTAG usercode ; 0x0122624D ; -; Checksum ; 0x0122624D ; +; JTAG usercode ; 0x0122B7FD ; +; Checksum ; 0x0122B7FD ; +----------------+--------------------------------------------------------------------+ @@ -103,12 +103,12 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 64-Bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Fri Aug 27 17:23:13 2021 + Info: Processing started: Sat Aug 28 10:55:56 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv Info (115030): Assembler is generating device programming files Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 661 megabytes - Info: Processing ended: Fri Aug 27 17:23:28 2021 + Info: Processing ended: Sat Aug 28 10:56:11 2021 Info: Elapsed time: 00:00:15 Info: Total CPU time (on all processors): 00:00:15 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.done b/examples/hdl4se_riscv/de1/de1_riscv.done index d673dd50fe95fefd9b8658c10361e16a083e3e5a..dde85829518822dc1232a811112624b2ad7c44e6 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.done +++ b/examples/hdl4se_riscv/de1/de1_riscv.done @@ -1 +1 @@ -Fri Aug 27 17:24:02 2021 +Sat Aug 28 10:56:46 2021 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt b/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt index c3b26cd651d8ede63930d6a0f744dc64dafd4083..563bfb1a6fc1c0d27a022e4c23cbeb265f2145b7 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt @@ -1,5 +1,5 @@ Fitter report for de1_riscv -Fri Aug 27 17:23:09 2021 +Sat Aug 28 10:55:52 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -67,15 +67,15 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+---------------------------------------------+ -; Fitter Status ; Successful - Fri Aug 27 17:23:08 2021 ; +; Fitter Status ; Successful - Sat Aug 28 10:55:51 2021 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; ; Device ; 5CSEMA5F31C6 ; ; Timing Models ; Preliminary ; -; Logic utilization (in ALMs) ; 2,468 / 32,070 ( 8 % ) ; -; Total registers ; 1833 ; +; Logic utilization (in ALMs) ; 2,494 / 32,070 ( 8 % ) ; +; Total registers ; 1863 ; ; Total pins ; 204 / 457 ( 45 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ; @@ -154,12 +154,12 @@ applicable agreement for further details. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.37 ; +; Average used ; 1.41 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 37.2% ; +; Processor 2 ; 41.2% ; ; Processors 3-4 ; 0.0% ; +----------------------------+-------------+ @@ -310,9 +310,7 @@ applicable agreement for further details. ; GPIO[2] ; Missing drive strength and slew rate ; ; GPIO[3] ; Missing drive strength and slew rate ; ; GPIO[4] ; Missing drive strength and slew rate ; -; GPIO[5] ; Missing drive strength and slew rate ; ; GPIO[6] ; Missing drive strength and slew rate ; -; GPIO[7] ; Missing drive strength and slew rate ; ; GPIO[8] ; Missing drive strength and slew rate ; ; GPIO[9] ; Missing drive strength and slew rate ; ; GPIO[10] ; Missing drive strength and slew rate ; @@ -341,6 +339,8 @@ applicable agreement for further details. ; GPIO[33] ; Missing drive strength and slew rate ; ; GPIO[34] ; Missing drive strength and slew rate ; ; GPIO[35] ; Missing drive strength and slew rate ; +; GPIO[5] ; Missing drive strength and slew rate ; +; GPIO[7] ; Missing drive strength and slew rate ; +---------------+--------------------------------------+ @@ -1118,199 +1118,201 @@ applicable agreement for further details. ; riscv_core:core|rs2[31]~_Duplicate_4 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|rs2[31]~_Duplicate_5 ; Q ; ; ; riscv_core:core|rs2[31]~_Duplicate_5 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated|Mult0~781 ; AY ; ; ; riscv_core:core|rs2[31]~_Duplicate_5 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|rs2[31]~_Duplicate_6 ; Q ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[28] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[28]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[54] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[54]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[59] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[59]~DUPLICATE ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[24]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[47] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[47]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[50] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[50]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[52] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[52]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[53] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[53]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[56] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[56]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[58] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[58]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[60] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[60]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[75] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[75]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[79] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[79]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[83] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[83]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[90] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[90]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[91] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[91]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[92] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[92]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[93] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[93]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[101] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[101]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[123] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[123]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[143] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[143]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[146] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[146]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[147] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[147]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[150] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[150]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[104] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[104]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[108] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[108]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[151] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[151]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[156] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[156]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[157] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[157]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[179] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[179]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[186] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[186]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[178] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[178]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[188] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[188]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[190] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[190]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[213] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[213]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[216] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[216]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[247] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[247]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[282] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[282]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[283] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[283]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[290] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[290]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[291] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[291]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[292] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[292]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[308] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[308]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[352] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[352]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[284] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[284]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[70] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[70]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[128] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[128]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[129] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[129]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[132] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[132]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[133] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[133]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[139] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[139]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[161] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[161]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[163] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[163]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[167] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[167]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[168] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[168]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[172] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[172]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[225] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[225]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[226] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[226]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[160] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[160]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[170] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[170]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[192] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[192]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[196] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[196]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[204] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[204]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[205] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[205]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[227] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[227]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[229] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[229]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[230] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[230]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[231] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[231]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[239] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[239]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[242] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[242]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[243] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[243]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[266] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[266]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[267] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[267]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[271] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[271]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[256] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[256]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[259] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[259]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[261] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[261]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[265] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[265]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[274] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[274]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[278] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[278]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[289]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[275] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[275]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[277] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[277]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[320] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[320]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[321] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[321]~DUPLICATE ; ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[322] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[322]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[324] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[324]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[326] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[326]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[327] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[327]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[328] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[328]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[329] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[329]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[330] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[330]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[333] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[333]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[334] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[334]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[335] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[335]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[336] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[336]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[337] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[337]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[338] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[338]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[339] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[339]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[342] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[342]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[343] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[343]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[346] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[346]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[361] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[361]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[363] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[363]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[364] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[364]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[365] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[365]~DUPLICATE ; ; ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[370] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[370]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[46] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[46]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[51] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[51]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[54] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[54]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[74] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[74]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[84] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[84]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[85] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[85]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[108] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[108]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[113] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[113]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[114] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[114]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[143] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[143]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[151] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[151]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[158] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[158]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[323] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[323]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[325] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[325]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[344] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[344]~DUPLICATE ; ; ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[347] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[347]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[118] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[118]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[120] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[120]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[146] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[146]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[147] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[147]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[180] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[180]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[183] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[183]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[190] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[190]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[250] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[250]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[281] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[281]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[282] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[282]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[184] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[184]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[189] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[189]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[213] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[213]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[215] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[215]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[216] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[216]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[217] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[217]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[283] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[283]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[287] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[287]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[364] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[364]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[382] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[382]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[354] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[354]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[356] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[356]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[362] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[362]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[367] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[367]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[368] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[368]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[369] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[369]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[370] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[370]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[383] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[383]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[64] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[64]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[65] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[65]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[66] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[66]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[67] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[67]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[70] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[70]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[103] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[103]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[105] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[105]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[128] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[128]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[131] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[131]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[137] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[137]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[129] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[129]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[138] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[138]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[139] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[139]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[160] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[160]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[163] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[163]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[169] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[169]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[170] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[170]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[174] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[174]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[224] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[224]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[225] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[225]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[230] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[230]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[226] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[226]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[227] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[227]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[228] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[228]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[231] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[231]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[232] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[232]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[236] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[236]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[237] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[237]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[238] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[238]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[239] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[239]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[240] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[240]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[243] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[243]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[256] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[256]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[258] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[258]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[259] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[259]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[260] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[260]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[261] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[261]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[241] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[241]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[242] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[242]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[257] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[257]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[263] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[263]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[264] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[264]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[265] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[265]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[268] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[268]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[269] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[269]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[270] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[270]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[271] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[271]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[272] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[272]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[273] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[273]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[274] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[274]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[275] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[275]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[276] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[276]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[278] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[278]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[288] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[288]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[289]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[292] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[292]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[305] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[305]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[320] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[320]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[321] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[321]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[322] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[322]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[323] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[323]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[325] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[325]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[326] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[326]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[327] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[327]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[329] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[329]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[330] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[330]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[331] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[331]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[332] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[332]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[333] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[333]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[335] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[335]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[336] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[336]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[338] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[338]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[339] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[339]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[340] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[340]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[341] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[341]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[343] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[343]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[359] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[359]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[361] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[361]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[380] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[380]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[346] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[346]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[352] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[352]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[354] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[354]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[362] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[362]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ; -; riscv_core:core|dstreg[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|dstreg[1]~DUPLICATE ; ; ; -; riscv_core:core|imm[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[1]~DUPLICATE ; ; ; -; riscv_core:core|imm[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[3]~DUPLICATE ; ; ; -; riscv_core:core|imm[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[13]~DUPLICATE ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ; +; riscv_core:core|imm[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[2]~DUPLICATE ; ; ; +; riscv_core:core|imm[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[5]~DUPLICATE ; ; ; +; riscv_core:core|imm[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[12]~DUPLICATE ; ; ; +; riscv_core:core|imm[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[14]~DUPLICATE ; ; ; +; riscv_core:core|imm[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[15]~DUPLICATE ; ; ; +; riscv_core:core|imm[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[16]~DUPLICATE ; ; ; +; riscv_core:core|imm[17] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[17]~DUPLICATE ; ; ; +; riscv_core:core|imm[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[18]~DUPLICATE ; ; ; ; riscv_core:core|imm[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[22]~DUPLICATE ; ; ; ; riscv_core:core|imm[25] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[25]~DUPLICATE ; ; ; -; riscv_core:core|instr[20] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|instr[20]~DUPLICATE ; ; ; -; riscv_core:core|instr[23] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|instr[23]~DUPLICATE ; ; ; -; riscv_core:core|instr[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|instr[24]~DUPLICATE ; ; ; -; riscv_core:core|rs1[3]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[3]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs1[5]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[5]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs1[8]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[8]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|imm[31] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[31]~DUPLICATE ; ; ; +; riscv_core:core|ldaddr[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|ldaddr[0]~DUPLICATE ; ; ; +; riscv_core:core|ldaddr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|ldaddr[1]~DUPLICATE ; ; ; ; riscv_core:core|rs1[9]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[9]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs1[10]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[10]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs1[19]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[19]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs1[28]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[28]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs1[29]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[29]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs1[31]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[31]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[0]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[0]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[1]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[1]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs2[3]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[3]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs2[4]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[4]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs2[5]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[5]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs2[11]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[11]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[7]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[7]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[10]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[10]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[13]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[13]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[17]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[17]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|rs2[18]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[18]~_Duplicate_6DUPLICATE ; ; ; -; riscv_core:core|rs2[30]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[30]~_Duplicate_6DUPLICATE ; ; ; +; riscv_core:core|rs2[28]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[28]~_Duplicate_6DUPLICATE ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg0FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ; @@ -1352,8 +1354,8 @@ applicable agreement for further details. ; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; +---------------------+---------------------+----------------------------+--------------------------+ ; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 5964 ) ; 0.00 % ( 0 / 5964 ) ; 0.00 % ( 0 / 5964 ) ; -; -- Achieved ; 0.00 % ( 0 / 5964 ) ; 0.00 % ( 0 / 5964 ) ; 0.00 % ( 0 / 5964 ) ; +; -- Requested ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; +; -- Achieved ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; ; ; ; ; ; ; Routing (by net) ; ; ; ; ; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; @@ -1376,7 +1378,7 @@ applicable agreement for further details. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 5955 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 6027 ) ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 9 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -1392,44 +1394,44 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 +-------------------------------------------------------------+--------------------+-------+ ; Resource ; Usage ; % ; +-------------------------------------------------------------+--------------------+-------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 2,468 / 32,070 ; 8 % ; -; ALMs needed [=A-B+C] ; 2,468 ; ; -; [A] ALMs used in final placement [=a+b+c+d] ; 2,567 / 32,070 ; 8 % ; -; [a] ALMs used for LUT logic and registers ; 430 ; ; -; [b] ALMs used for LUT logic ; 1,652 ; ; -; [c] ALMs used for registers ; 385 ; ; +; Logic utilization (ALMs needed / total ALMs on device) ; 2,494 / 32,070 ; 8 % ; +; ALMs needed [=A-B+C] ; 2,494 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 2,611 / 32,070 ; 8 % ; +; [a] ALMs used for LUT logic and registers ; 427 ; ; +; [b] ALMs used for LUT logic ; 1,679 ; ; +; [c] ALMs used for registers ; 405 ; ; ; [d] ALMs used for memory (up to half of total ALMs) ; 100 ; ; -; [B] Estimate of ALMs recoverable by dense packing ; 152 / 32,070 ; < 1 % ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 53 / 32,070 ; < 1 % ; +; [B] Estimate of ALMs recoverable by dense packing ; 175 / 32,070 ; < 1 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 58 / 32,070 ; < 1 % ; ; [a] Due to location constrained logic ; 3 ; ; ; [b] Due to LAB-wide signal conflicts ; 0 ; ; -; [c] Due to LAB input limits ; 50 ; ; +; [c] Due to LAB input limits ; 55 ; ; ; [d] Due to virtual I/Os ; 0 ; ; ; ; ; ; ; Difficulty packing design ; Low ; ; ; ; ; ; -; Total LABs: partially or completely used ; 322 / 3,207 ; 10 % ; -; -- Logic LABs ; 312 ; ; +; Total LABs: partially or completely used ; 331 / 3,207 ; 10 % ; +; -- Logic LABs ; 321 ; ; ; -- Memory LABs (up to half of total LABs) ; 10 ; ; ; ; ; ; -; Combinational ALUT usage for logic ; 3,718 ; ; +; Combinational ALUT usage for logic ; 3,763 ; ; ; -- 7 input functions ; 47 ; ; -; -- 6 input functions ; 335 ; ; -; -- 5 input functions ; 468 ; ; -; -- 4 input functions ; 822 ; ; -; -- <=3 input functions ; 2,046 ; ; -; Combinational ALUT usage for route-throughs ; 519 ; ; +; -- 6 input functions ; 327 ; ; +; -- 5 input functions ; 472 ; ; +; -- 4 input functions ; 831 ; ; +; -- <=3 input functions ; 2,086 ; ; +; Combinational ALUT usage for route-throughs ; 547 ; ; ; Memory ALUT usage ; 103 ; ; ; -- 64-address deep ; 0 ; ; ; -- 32-address deep ; 103 ; ; ; ; ; ; -; Dedicated logic registers ; 1,833 ; ; +; Dedicated logic registers ; 1,863 ; ; ; -- By type: ; ; ; -; -- Primary logic registers ; 1,630 / 64,140 ; 3 % ; -; -- Secondary logic registers ; 203 / 64,140 ; < 1 % ; +; -- Primary logic registers ; 1,662 / 64,140 ; 3 % ; +; -- Secondary logic registers ; 201 / 64,140 ; < 1 % ; ; -- By function: ; ; ; -; -- Design implementation registers ; 1,640 ; ; -; -- Routing optimization registers ; 193 ; ; +; -- Design implementation registers ; 1,668 ; ; +; -- Routing optimization registers ; 195 ; ; ; ; ; ; ; Virtual pins ; 0 ; ; ; I/O pins ; 204 / 457 ; 45 % ; @@ -1482,11 +1484,11 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; Impedance control blocks ; 0 / 4 ; 0 % ; ; Hard Memory Controllers ; 0 / 2 ; 0 % ; ; Average interconnect usage (total/H/V) ; 2% / 2% / 2% ; ; -; Peak interconnect usage (total/H/V) ; 31% / 30% / 35% ; ; -; Maximum fan-out ; 2069 ; ; -; Highest non-global fan-out ; 238 ; ; -; Total fan-out ; 21123 ; ; -; Average fan-out ; 3.17 ; ; +; Peak interconnect usage (total/H/V) ; 30% / 31% / 27% ; ; +; Maximum fan-out ; 2099 ; ; +; Highest non-global fan-out ; 246 ; ; +; Total fan-out ; 21324 ; ; +; Average fan-out ; 3.15 ; ; +-------------------------------------------------------------+--------------------+-------+ @@ -1495,44 +1497,44 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 +-------------------------------------------------------------+-----------------------+--------------------------------+ ; Statistic ; Top ; hard_block:auto_generated_inst ; +-------------------------------------------------------------+-----------------------+--------------------------------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 2468 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ; -; ALMs needed [=A-B+C] ; 2468 ; 0 ; -; [A] ALMs used in final placement [=a+b+c+d] ; 2567 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ; -; [a] ALMs used for LUT logic and registers ; 430 ; 0 ; -; [b] ALMs used for LUT logic ; 1652 ; 0 ; -; [c] ALMs used for registers ; 385 ; 0 ; +; Logic utilization (ALMs needed / total ALMs on device) ; 2494 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 2494 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 2611 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 427 ; 0 ; +; [b] ALMs used for LUT logic ; 1679 ; 0 ; +; [c] ALMs used for registers ; 405 ; 0 ; ; [d] ALMs used for memory (up to half of total ALMs) ; 100 ; 0 ; -; [B] Estimate of ALMs recoverable by dense packing ; 152 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 53 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [B] Estimate of ALMs recoverable by dense packing ; 175 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 58 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ; ; [a] Due to location constrained logic ; 3 ; 0 ; ; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; -; [c] Due to LAB input limits ; 50 ; 0 ; +; [c] Due to LAB input limits ; 55 ; 0 ; ; [d] Due to virtual I/Os ; 0 ; 0 ; ; ; ; ; ; Difficulty packing design ; Low ; Low ; ; ; ; ; -; Total LABs: partially or completely used ; 322 / 3207 ( 10 % ) ; 0 / 3207 ( 0 % ) ; -; -- Logic LABs ; 312 ; 0 ; +; Total LABs: partially or completely used ; 331 / 3207 ( 10 % ) ; 0 / 3207 ( 0 % ) ; +; -- Logic LABs ; 321 ; 0 ; ; -- Memory LABs (up to half of total LABs) ; 10 ; 0 ; ; ; ; ; -; Combinational ALUT usage for logic ; 3821 ; 0 ; +; Combinational ALUT usage for logic ; 3866 ; 0 ; ; -- 7 input functions ; 47 ; 0 ; -; -- 6 input functions ; 335 ; 0 ; -; -- 5 input functions ; 468 ; 0 ; -; -- 4 input functions ; 822 ; 0 ; -; -- <=3 input functions ; 2046 ; 0 ; -; Combinational ALUT usage for route-throughs ; 519 ; 0 ; +; -- 6 input functions ; 327 ; 0 ; +; -- 5 input functions ; 472 ; 0 ; +; -- 4 input functions ; 831 ; 0 ; +; -- <=3 input functions ; 2086 ; 0 ; +; Combinational ALUT usage for route-throughs ; 547 ; 0 ; ; Memory ALUT usage ; 103 ; 0 ; ; -- 64-address deep ; 0 ; 0 ; ; -- 32-address deep ; 103 ; 0 ; ; ; ; ; ; Dedicated logic registers ; 0 ; 0 ; ; -- By type: ; ; ; -; -- Primary logic registers ; 1630 / 64140 ( 3 % ) ; 0 / 64140 ( 0 % ) ; -; -- Secondary logic registers ; 203 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; +; -- Primary logic registers ; 1662 / 64140 ( 3 % ) ; 0 / 64140 ( 0 % ) ; +; -- Secondary logic registers ; 201 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ; ; -- By function: ; ; ; -; -- Design implementation registers ; 1640 ; 0 ; -; -- Routing optimization registers ; 193 ; 0 ; +; -- Design implementation registers ; 1668 ; 0 ; +; -- Routing optimization registers ; 195 ; 0 ; ; ; ; ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; @@ -1549,18 +1551,18 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; PLL Reference Clock Select Block ; 0 / 6 ( 0 % ) ; 1 / 6 ( 16 % ) ; ; ; ; ; ; Connections ; ; ; -; -- Input Connections ; 2187 ; 0 ; -; -- Registered Input Connections ; 1866 ; 0 ; -; -- Output Connections ; 60 ; 2127 ; +; -- Input Connections ; 2246 ; 0 ; +; -- Registered Input Connections ; 1925 ; 0 ; +; -- Output Connections ; 60 ; 2186 ; ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; -; -- Total Connections ; 22211 ; 2161 ; -; -- Registered Connections ; 9663 ; 0 ; +; -- Total Connections ; 22412 ; 2220 ; +; -- Registered Connections ; 9803 ; 0 ; ; ; ; ; ; External Connections ; ; ; -; -- Top ; 120 ; 2127 ; -; -- hard_block:auto_generated_inst ; 2127 ; 0 ; +; -- Top ; 120 ; 2186 ; +; -- hard_block:auto_generated_inst ; 2186 ; 0 ; ; ; ; ; ; Partition Interface ; ; ; ; -- Input Ports ; 32 ; 2 ; @@ -1598,7 +1600,7 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; KEY[2] ; W15 ; 3B ; 40 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; -; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 59 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; +; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 88 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; @@ -1606,7 +1608,7 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; SW[4] ; AD11 ; 3A ; 2 ; 0 ; 40 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[5] ; AD12 ; 3A ; 16 ; 0 ; 17 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[6] ; AE11 ; 3A ; 4 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; -; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; +; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; ; TD_CLK27 ; H15 ; 8A ; 40 ; 81 ; 0 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; @@ -1799,9 +1801,9 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1 ; GPIO[35] ; AJ21 ; 4A ; 62 ; 0 ; 51 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[3] ; Y18 ; 4A ; 72 ; 0 ; 0 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[4] ; AK16 ; 4A ; 54 ; 0 ; 51 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; -; GPIO[5] ; AK18 ; 4A ; 58 ; 0 ; 57 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; +; GPIO[5] ; AK18 ; 4A ; 58 ; 0 ; 57 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[6] ; AK19 ; 4A ; 60 ; 0 ; 51 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; -; GPIO[7] ; AJ19 ; 4A ; 60 ; 0 ; 34 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; +; GPIO[7] ; AJ19 ; 4A ; 60 ; 0 ; 34 ; 1 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[8] ; AJ17 ; 4A ; 58 ; 0 ; 40 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; GPIO[9] ; AJ16 ; 4A ; 54 ; 0 ; 34 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; ; PS2_CLK ; AD7 ; 3A ; 6 ; 0 ; 0 ; 0 ; 0 ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; 0 ; Off ; User ; 0 pF ; - ; - ; @@ -2786,85 +2788,89 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------------------------------------------------------------------------------------------+----------------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; |de1_riscv ; 2468.0 (60.9) ; 2566.5 (68.8) ; 151.0 (8.4) ; 52.5 (0.5) ; 100.0 (0.0) ; 3718 (91) ; 1833 (66) ; 0 (0) ; 66560 ; 9 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; -; |clk100M:clk100| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; -; |clk100M_0002:clk100m_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; -; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; -; |ram8kb:ram| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram ; work ; -; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component ; work ; -; |altsyncram_bdq1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated ; work ; -; |regfile:regs| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; -; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; -; |altsyncram_nco1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; -; |riscv_core:core| ; 2407.1 (836.3) ; 2497.7 (861.6) ; 142.6 (55.4) ; 52.0 (30.2) ; 100.0 (0.0) ; 3627 (1184) ; 1767 (310) ; 0 (0) ; 0 ; 0 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; -; |adder:add| ; 11.0 (0.0) ; 11.3 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; -; |lpm_add_sub:LPM_ADD_SUB_component| ; 11.0 (0.0) ; 11.3 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; -; |add_sub_tih:auto_generated| ; 11.0 (11.0) ; 11.3 (11.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; -; |div:div| ; 623.8 (0.0) ; 651.7 (0.0) ; 34.6 (0.0) ; 6.7 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 658 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; -; |lpm_divide:LPM_DIVIDE_component| ; 623.8 (0.0) ; 651.7 (0.0) ; 34.6 (0.0) ; 6.7 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 658 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; -; |lpm_divide_2jt:auto_generated| ; 623.8 (0.0) ; 651.7 (0.0) ; 34.6 (0.0) ; 6.7 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 658 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; -; |sign_div_unsign_8ai:divider| ; 623.8 (0.0) ; 651.7 (0.0) ; 34.6 (0.0) ; 6.7 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 658 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; -; |alt_u_div_nlf:divider| ; 623.8 (623.8) ; 651.7 (651.7) ; 34.6 (34.6) ; 6.7 (6.7) ; 0.0 (0.0) ; 1002 (1002) ; 658 (658) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; -; |div_s:divs| ; 869.0 (0.0) ; 908.5 (0.0) ; 52.6 (0.0) ; 13.2 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 799 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; -; |lpm_divide:LPM_DIVIDE_component| ; 869.0 (0.0) ; 908.5 (0.0) ; 52.6 (0.0) ; 13.2 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 799 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; -; |lpm_divide_s4t:auto_generated| ; 869.0 (0.0) ; 908.5 (0.0) ; 52.6 (0.0) ; 13.2 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 799 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; -; |sign_div_unsign_2sh:divider| ; 869.0 (80.1) ; 908.5 (79.6) ; 52.6 (5.2) ; 13.2 (5.7) ; 100.0 (0.0) ; 1278 (175) ; 799 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; -; |alt_u_div_5eg:divider| ; 772.3 (630.3) ; 810.4 (656.0) ; 45.6 (33.1) ; 7.4 (7.4) ; 90.0 (0.0) ; 1090 (987) ; 772 (670) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; -; |altshift_taps:DFFNumerator_rtl_0| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 15 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; -; |shift_taps_hm21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 15 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; -; |altsyncram_9u91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; -; |cntr_9jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_1| ; 16.5 (0.0) ; 18.5 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; -; |shift_taps_gm21:auto_generated| ; 16.5 (2.3) ; 18.5 (3.3) ; 2.0 (1.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; -; |altsyncram_7u91:altsyncram5| ; 11.3 (11.3) ; 11.8 (11.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; -; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_2| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; -; |shift_taps_bl21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 16 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; -; |altsyncram_rr91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; -; |cntr_0if:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_3| ; 14.5 (0.0) ; 15.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (0) ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; -; |shift_taps_9l21:auto_generated| ; 14.5 (2.3) ; 15.0 (2.4) ; 0.5 (0.2) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (5) ; 11 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; -; |altsyncram_lr91:altsyncram4| ; 10.8 (10.8) ; 11.1 (11.1) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; -; |cntr_uhf:cntr1| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_4| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; -; |shift_taps_cl21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 11 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; -; |altsyncram_hr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; -; |cntr_thf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_5| ; 16.5 (0.0) ; 18.0 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; -; |shift_taps_dl21:auto_generated| ; 16.5 (2.3) ; 18.0 (3.2) ; 1.5 (0.9) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (6) ; 11 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; -; |altsyncram_mr91:altsyncram5| ; 10.6 (10.6) ; 11.0 (11.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; -; |cntr_shf:cntr1| ; 3.7 (3.7) ; 3.8 (3.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_6| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; -; |shift_taps_4l21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 12 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; -; |altsyncram_dr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; -; |cntr_rhf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_7| ; 13.0 (0.0) ; 13.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; -; |shift_taps_3l21:auto_generated| ; 13.0 (1.8) ; 13.5 (1.8) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (4) ; 6 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; -; |altsyncram_9r91:altsyncram4| ; 10.4 (10.4) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; -; |cntr_phf:cntr1| ; 0.8 (0.8) ; 1.0 (1.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_8| ; 13.5 (0.0) ; 14.5 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; -; |shift_taps_5l21:auto_generated| ; 13.5 (0.9) ; 14.5 (1.3) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (2) ; 7 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; -; |altsyncram_br91:altsyncram4| ; 10.4 (10.4) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; -; |cntr_ohf:cntr1| ; 2.2 (2.2) ; 2.5 (2.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; -; |altshift_taps:DFF_Num_Sign_rtl_0| ; 16.6 (0.0) ; 18.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; -; |shift_taps_7l21:auto_generated| ; 16.6 (2.5) ; 18.5 (3.3) ; 1.9 (0.7) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; -; |altsyncram_kr91:altsyncram5| ; 11.0 (11.0) ; 11.8 (11.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; -; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; -; |mulsu:mul_su| ; 19.2 (0.0) ; 18.7 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; -; |lpm_mult:lpm_mult_component| ; 19.2 (0.0) ; 18.7 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; -; |mult_61n:auto_generated| ; 19.2 (19.2) ; 18.7 (18.7) ; 0.0 (0.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 38 (38) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; -; |mult:mul| ; 23.9 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.9 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; -; |lpm_mult:lpm_mult_component| ; 23.9 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.9 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; -; |mult_b8n:auto_generated| ; 23.9 (23.9) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; -; |mult_s:mul_s| ; 23.6 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.6 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; -; |lpm_mult:lpm_mult_component| ; 23.6 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.6 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; -; |mult_81n:auto_generated| ; 23.6 (23.6) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; -+----------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |de1_riscv ; 2493.5 (64.7) ; 2609.5 (70.4) ; 173.0 (6.5) ; 57.0 (0.8) ; 100.0 (0.0) ; 3763 (95) ; 1863 (66) ; 0 (0) ; 66560 ; 9 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; +; |altera_uart:uart| ; 18.5 (0.0) ; 20.5 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (0) ; 29 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart ; work ; +; |altera_uart_regs:the_altera_uart_regs| ; 0.9 (0.9) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ; +; |altera_uart_rx:the_altera_uart_rx| ; 17.6 (16.9) ; 19.3 (18.7) ; 1.7 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (35) ; 27 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; work ; +; |clk100M:clk100| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; +; |clk100M_0002:clk100m_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; +; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; +; |ram8kb:ram| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram ; work ; +; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component ; work ; +; |altsyncram_bdq1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated ; work ; +; |regfile:regs| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; +; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; +; |altsyncram_nco1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; +; |riscv_core:core| ; 2410.3 (842.3) ; 2518.6 (868.5) ; 164.5 (60.1) ; 56.2 (33.9) ; 100.0 (0.0) ; 3632 (1189) ; 1768 (314) ; 0 (0) ; 0 ; 0 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; +; |adder:add| ; 9.0 (0.0) ; 9.8 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; +; |lpm_add_sub:LPM_ADD_SUB_component| ; 9.0 (0.0) ; 9.8 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; +; |add_sub_tih:auto_generated| ; 9.0 (9.0) ; 9.8 (9.8) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; +; |div:div| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; +; |lpm_divide:LPM_DIVIDE_component| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; +; |lpm_divide_2jt:auto_generated| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; +; |sign_div_unsign_8ai:divider| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; +; |alt_u_div_nlf:divider| ; 622.1 (622.1) ; 657.9 (657.9) ; 43.1 (43.1) ; 7.3 (7.3) ; 0.0 (0.0) ; 1002 (1002) ; 648 (648) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; +; |div_s:divs| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; +; |lpm_divide:LPM_DIVIDE_component| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; +; |lpm_divide_s4t:auto_generated| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; +; |sign_div_unsign_2sh:divider| ; 869.4 (80.0) ; 917.4 (76.2) ; 60.4 (1.6) ; 12.5 (5.4) ; 100.0 (0.0) ; 1278 (175) ; 806 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; +; |alt_u_div_5eg:divider| ; 772.8 (630.8) ; 822.7 (668.0) ; 57.0 (44.3) ; 7.1 (7.1) ; 90.0 (0.0) ; 1090 (987) ; 779 (682) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; +; |altshift_taps:DFFNumerator_rtl_0| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; +; |shift_taps_hm21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; +; |altsyncram_9u91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; +; |cntr_9jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_1| ; 16.5 (0.0) ; 18.5 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; +; |shift_taps_gm21:auto_generated| ; 16.5 (2.3) ; 18.5 (3.3) ; 2.0 (1.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 14 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; +; |altsyncram_7u91:altsyncram5| ; 11.3 (11.3) ; 11.8 (11.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; +; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_2| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; +; |shift_taps_bl21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 16 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; +; |altsyncram_rr91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; +; |cntr_0if:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_3| ; 14.5 (0.0) ; 15.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; +; |shift_taps_9l21:auto_generated| ; 14.5 (2.3) ; 15.0 (2.6) ; 0.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (5) ; 9 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; +; |altsyncram_lr91:altsyncram4| ; 10.8 (10.8) ; 10.9 (10.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; +; |cntr_uhf:cntr1| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_4| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; +; |shift_taps_cl21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 9 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; +; |altsyncram_hr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; +; |cntr_thf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_5| ; 16.5 (0.0) ; 18.2 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; +; |shift_taps_dl21:auto_generated| ; 16.5 (2.3) ; 18.2 (3.0) ; 1.7 (0.8) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (6) ; 10 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; +; |altsyncram_mr91:altsyncram5| ; 10.6 (10.6) ; 11.2 (11.2) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; +; |cntr_shf:cntr1| ; 3.7 (3.7) ; 4.0 (4.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_6| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; +; |shift_taps_4l21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 12 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; +; |altsyncram_dr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; +; |cntr_rhf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_7| ; 13.0 (0.0) ; 13.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; +; |shift_taps_3l21:auto_generated| ; 13.0 (1.8) ; 13.5 (1.9) ; 0.5 (0.2) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (4) ; 7 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; +; |altsyncram_9r91:altsyncram4| ; 10.4 (10.4) ; 10.6 (10.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; +; |cntr_phf:cntr1| ; 0.8 (0.8) ; 1.0 (1.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_8| ; 13.5 (0.0) ; 14.5 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; +; |shift_taps_5l21:auto_generated| ; 13.5 (0.9) ; 14.5 (1.3) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (2) ; 7 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; +; |altsyncram_br91:altsyncram4| ; 10.4 (10.4) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; +; |cntr_ohf:cntr1| ; 2.2 (2.2) ; 2.5 (2.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; +; |altshift_taps:DFF_Num_Sign_rtl_0| ; 16.6 (0.0) ; 18.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; +; |shift_taps_7l21:auto_generated| ; 16.6 (2.5) ; 18.5 (3.5) ; 1.9 (1.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; +; |altsyncram_kr91:altsyncram5| ; 11.0 (11.0) ; 11.5 (11.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; +; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; +; |mulsu:mul_su| ; 19.5 (0.0) ; 19.0 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; +; |lpm_mult:lpm_mult_component| ; 19.5 (0.0) ; 19.0 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; +; |mult_61n:auto_generated| ; 19.5 (19.5) ; 19.0 (19.0) ; 0.0 (0.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 38 (38) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; +; |mult:mul| ; 24.2 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; +; |lpm_mult:lpm_mult_component| ; 24.2 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; +; |mult_b8n:auto_generated| ; 24.2 (24.2) ; 23.0 (23.0) ; 0.0 (0.0) ; 1.2 (1.2) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; +; |mult_s:mul_s| ; 23.7 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; +; |lpm_mult:lpm_mult_component| ; 23.7 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; +; |mult_81n:auto_generated| ; 23.7 (23.7) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; ++----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -3031,9 +3037,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; GPIO[2] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[3] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[4] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; GPIO[5] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[6] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; -; GPIO[7] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[8] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[9] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[10] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; @@ -3062,6 +3066,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; GPIO[33] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[34] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; GPIO[35] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; GPIO[5] ; Bidir ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; GPIO[7] ; Bidir ; -- ; (0) ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; KEY[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[8] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[9] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; @@ -3070,9 +3076,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SW[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; SW[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; SW[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -; SW[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[5] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; SW[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; KEY[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; KEY[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; @@ -3080,262 +3086,292 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+--------------------------------------------------------------------------------------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+--------------------------------------------------------------------------------------------------------+-------------------+---------+ -; ADC_DOUT ; ; ; -; AUD_ADCDAT ; ; ; -; CLOCK2_50 ; ; ; -; CLOCK3_50 ; ; ; -; CLOCK4_50 ; ; ; -; IRDA_RXD ; ; ; -; TD_CLK27 ; ; ; -; TD_DATA[0] ; ; ; -; TD_DATA[1] ; ; ; -; TD_DATA[2] ; ; ; -; TD_DATA[3] ; ; ; -; TD_DATA[4] ; ; ; -; TD_DATA[5] ; ; ; -; TD_DATA[6] ; ; ; -; TD_DATA[7] ; ; ; -; TD_HS ; ; ; -; TD_VS ; ; ; -; AUD_ADCLRCK ; ; ; -; AUD_BCLK ; ; ; -; AUD_DACLRCK ; ; ; -; DRAM_DQ[0] ; ; ; -; DRAM_DQ[1] ; ; ; -; DRAM_DQ[2] ; ; ; -; DRAM_DQ[3] ; ; ; -; DRAM_DQ[4] ; ; ; -; DRAM_DQ[5] ; ; ; -; DRAM_DQ[6] ; ; ; -; DRAM_DQ[7] ; ; ; -; DRAM_DQ[8] ; ; ; -; DRAM_DQ[9] ; ; ; -; DRAM_DQ[10] ; ; ; -; DRAM_DQ[11] ; ; ; -; DRAM_DQ[12] ; ; ; -; DRAM_DQ[13] ; ; ; -; DRAM_DQ[14] ; ; ; -; DRAM_DQ[15] ; ; ; -; FPGA_I2C_SDAT ; ; ; -; PS2_CLK ; ; ; -; PS2_CLK2 ; ; ; -; PS2_DAT ; ; ; -; PS2_DAT2 ; ; ; -; GPIO[0] ; ; ; -; GPIO[1] ; ; ; -; GPIO[2] ; ; ; -; GPIO[3] ; ; ; -; GPIO[4] ; ; ; -; GPIO[5] ; ; ; -; GPIO[6] ; ; ; -; GPIO[7] ; ; ; -; GPIO[8] ; ; ; -; GPIO[9] ; ; ; -; GPIO[10] ; ; ; -; GPIO[11] ; ; ; -; GPIO[12] ; ; ; -; GPIO[13] ; ; ; -; GPIO[14] ; ; ; -; GPIO[15] ; ; ; -; GPIO[16] ; ; ; -; GPIO[17] ; ; ; -; GPIO[18] ; ; ; -; GPIO[19] ; ; ; -; GPIO[20] ; ; ; -; GPIO[21] ; ; ; -; GPIO[22] ; ; ; -; GPIO[23] ; ; ; -; GPIO[24] ; ; ; -; GPIO[25] ; ; ; -; GPIO[26] ; ; ; -; GPIO[27] ; ; ; -; GPIO[28] ; ; ; -; GPIO[29] ; ; ; -; GPIO[30] ; ; ; -; GPIO[31] ; ; ; -; GPIO[32] ; ; ; -; GPIO[33] ; ; ; -; GPIO[34] ; ; ; -; GPIO[35] ; ; ; -; KEY[3] ; ; ; -; - riscv_core:core|pc[22] ; 0 ; 0 ; -; - riscv_core:core|pc[23] ; 0 ; 0 ; -; - riscv_core:core|pc[24] ; 0 ; 0 ; -; - riscv_core:core|pc[25] ; 0 ; 0 ; -; - riscv_core:core|pc[3] ; 0 ; 0 ; -; - riscv_core:core|pc[26] ; 0 ; 0 ; -; - riscv_core:core|pc[20] ; 0 ; 0 ; -; - riscv_core:core|pc[27] ; 0 ; 0 ; -; - riscv_core:core|pc[13] ; 0 ; 0 ; -; - riscv_core:core|pc[30] ; 0 ; 0 ; -; - riscv_core:core|pc[10] ; 0 ; 0 ; -; - riscv_core:core|pc[28] ; 0 ; 0 ; -; - riscv_core:core|pc[14] ; 0 ; 0 ; -; - riscv_core:core|pc[15] ; 0 ; 0 ; -; - riscv_core:core|pc[16] ; 0 ; 0 ; -; - riscv_core:core|pc[17] ; 0 ; 0 ; -; - riscv_core:core|pc[18] ; 0 ; 0 ; -; - riscv_core:core|pc[29] ; 0 ; 0 ; -; - riscv_core:core|pc[11] ; 0 ; 0 ; -; - riscv_core:core|pc[9] ; 0 ; 0 ; -; - riscv_core:core|pc[7] ; 0 ; 0 ; -; - riscv_core:core|pc[12] ; 0 ; 0 ; -; - riscv_core:core|pc[19] ; 0 ; 0 ; -; - riscv_core:core|pc[21] ; 0 ; 0 ; -; - riscv_core:core|pc[8] ; 0 ; 0 ; -; - riscv_core:core|write ; 0 ; 0 ; -; - riscv_core:core|pc[0] ; 0 ; 0 ; -; - riscv_core:core|pc[1] ; 0 ; 0 ; -; - riscv_core:core|state.0110 ; 0 ; 0 ; -; - riscv_core:core|state.1010 ; 0 ; 0 ; -; - riscv_core:core|state.0010 ; 0 ; 0 ; -; - riscv_core:core|pc[31] ; 0 ; 0 ; -; - led0~0 ; 0 ; 0 ; -; - led2~0 ; 0 ; 0 ; -; - riscv_core:core|writedata[0]~2 ; 0 ; 0 ; -; - bReadData[13]~1 ; 0 ; 0 ; -; - riscv_core:core|state~25 ; 0 ; 0 ; -; - riscv_core:core|state.0000 ; 0 ; 0 ; -; - riscv_core:core|state~26 ; 0 ; 0 ; -; - readaddr~0 ; 0 ; 0 ; -; - riscv_core:core|state~27 ; 0 ; 0 ; -; - riscv_core:core|state~28 ; 0 ; 0 ; -; - riscv_core:core|state~29 ; 0 ; 0 ; -; - riscv_core:core|pc[31]~3 ; 0 ; 0 ; -; - riscv_core:core|pc~26 ; 0 ; 0 ; -; - riscv_core:core|pc~28 ; 0 ; 0 ; -; - riscv_core:core|pc~29 ; 0 ; 0 ; -; - riscv_core:core|pc~30 ; 0 ; 0 ; -; - riscv_core:core|Mux5~0 ; 0 ; 0 ; -; - riscv_core:core|Selector247~4 ; 0 ; 0 ; -; - riscv_core:core|state~30 ; 0 ; 0 ; -; - riscv_core:core|divclk[4]~0 ; 0 ; 0 ; -; - riscv_core:core|divclk[3]~1 ; 0 ; 0 ; -; - riscv_core:core|divclk[2]~2 ; 0 ; 0 ; -; - riscv_core:core|divclk[0]~3 ; 0 ; 0 ; -; - riscv_core:core|divclk[1]~4 ; 0 ; 0 ; -; - riscv_core:core|pc[0]~33 ; 0 ; 0 ; -; - KEY[3]~_wirecell ; 0 ; 0 ; -; - clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL ; 0 ; 0 ; -; SW[8] ; ; ; -; - led0~0 ; 1 ; 0 ; -; - led2~0 ; 1 ; 0 ; -; - riscv_core:core|Mux17~0 ; 1 ; 0 ; -; - riscv_core:core|Mux57~0 ; 1 ; 0 ; -; - bReadData[8]~20 ; 1 ; 0 ; -; SW[9] ; ; ; -; - led1[5]~0 ; 1 ; 0 ; -; - led1[5]~3 ; 1 ; 0 ; -; - led2~1 ; 1 ; 0 ; -; - led3~0 ; 1 ; 0 ; -; - led4[0]~0 ; 1 ; 0 ; -; - led4~1 ; 1 ; 0 ; -; - led5~0 ; 1 ; 0 ; -; - bReadData[9]~18 ; 1 ; 0 ; -; - riscv_core:core|Mux9~0 ; 1 ; 0 ; -; - riscv_core:core|Mux56~1 ; 1 ; 0 ; -; CLOCK_50 ; ; ; -; KEY[2] ; ; ; -; - bReadData[12]~0 ; 1 ; 0 ; -; - riscv_core:core|Mux6~0 ; 1 ; 0 ; -; - riscv_core:core|Selector248~4 ; 1 ; 0 ; -; SW[2] ; ; ; -; - bReadData[2]~3 ; 0 ; 0 ; -; SW[3] ; ; ; -; - bReadData[3]~4 ; 0 ; 0 ; -; SW[6] ; ; ; -; - bReadData[6]~5 ; 1 ; 0 ; -; SW[4] ; ; ; -; - bReadData[4]~6 ; 1 ; 0 ; -; SW[5] ; ; ; -; - bReadData[5]~7 ; 1 ; 0 ; -; SW[0] ; ; ; -; - riscv_core:core|Mux57~1 ; 0 ; 0 ; -; SW[7] ; ; ; -; - riscv_core:core|Mux18~1 ; 0 ; 0 ; -; - bReadData[7]~19 ; 0 ; 0 ; -; - riscv_core:core|Mux1~1 ; 0 ; 0 ; -; - riscv_core:core|Mux1~3 ; 0 ; 0 ; -; - riscv_core:core|Mux26~5 ; 0 ; 0 ; -; - riscv_core:core|Mux26~7 ; 0 ; 0 ; -; KEY[0] ; ; ; -; - bReadData[10]~27 ; 0 ; 0 ; -; - riscv_core:core|Mux8~0 ; 0 ; 0 ; -; - riscv_core:core|Selector250~4 ; 0 ; 0 ; -; KEY[1] ; ; ; -; - bReadData[11]~29 ; 1 ; 0 ; -; - riscv_core:core|Mux7~0 ; 1 ; 0 ; -; - riscv_core:core|Selector249~4 ; 1 ; 0 ; -; SW[1] ; ; ; -; - riscv_core:core|Mux56~2 ; 0 ; 0 ; -+--------------------------------------------------------------------------------------------------------+-------------------+---------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; ADC_DOUT ; ; ; +; AUD_ADCDAT ; ; ; +; CLOCK2_50 ; ; ; +; CLOCK3_50 ; ; ; +; CLOCK4_50 ; ; ; +; IRDA_RXD ; ; ; +; TD_CLK27 ; ; ; +; TD_DATA[0] ; ; ; +; TD_DATA[1] ; ; ; +; TD_DATA[2] ; ; ; +; TD_DATA[3] ; ; ; +; TD_DATA[4] ; ; ; +; TD_DATA[5] ; ; ; +; TD_DATA[6] ; ; ; +; TD_DATA[7] ; ; ; +; TD_HS ; ; ; +; TD_VS ; ; ; +; AUD_ADCLRCK ; ; ; +; AUD_BCLK ; ; ; +; AUD_DACLRCK ; ; ; +; DRAM_DQ[0] ; ; ; +; DRAM_DQ[1] ; ; ; +; DRAM_DQ[2] ; ; ; +; DRAM_DQ[3] ; ; ; +; DRAM_DQ[4] ; ; ; +; DRAM_DQ[5] ; ; ; +; DRAM_DQ[6] ; ; ; +; DRAM_DQ[7] ; ; ; +; DRAM_DQ[8] ; ; ; +; DRAM_DQ[9] ; ; ; +; DRAM_DQ[10] ; ; ; +; DRAM_DQ[11] ; ; ; +; DRAM_DQ[12] ; ; ; +; DRAM_DQ[13] ; ; ; +; DRAM_DQ[14] ; ; ; +; DRAM_DQ[15] ; ; ; +; FPGA_I2C_SDAT ; ; ; +; PS2_CLK ; ; ; +; PS2_CLK2 ; ; ; +; PS2_DAT ; ; ; +; PS2_DAT2 ; ; ; +; GPIO[0] ; ; ; +; GPIO[1] ; ; ; +; GPIO[2] ; ; ; +; GPIO[3] ; ; ; +; GPIO[4] ; ; ; +; GPIO[6] ; ; ; +; GPIO[8] ; ; ; +; GPIO[9] ; ; ; +; GPIO[10] ; ; ; +; GPIO[11] ; ; ; +; GPIO[12] ; ; ; +; GPIO[13] ; ; ; +; GPIO[14] ; ; ; +; GPIO[15] ; ; ; +; GPIO[16] ; ; ; +; GPIO[17] ; ; ; +; GPIO[18] ; ; ; +; GPIO[19] ; ; ; +; GPIO[20] ; ; ; +; GPIO[21] ; ; ; +; GPIO[22] ; ; ; +; GPIO[23] ; ; ; +; GPIO[24] ; ; ; +; GPIO[25] ; ; ; +; GPIO[26] ; ; ; +; GPIO[27] ; ; ; +; GPIO[28] ; ; ; +; GPIO[29] ; ; ; +; GPIO[30] ; ; ; +; GPIO[31] ; ; ; +; GPIO[32] ; ; ; +; GPIO[33] ; ; ; +; GPIO[34] ; ; ; +; GPIO[35] ; ; ; +; GPIO[5] ; ; ; +; GPIO[7] ; ; ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~feeder ; 0 ; 0 ; +; KEY[3] ; ; ; +; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|d1_rx_char_ready ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|d1_tx_ready ; 0 ; 0 ; +; - riscv_core:core|pc[18] ; 0 ; 0 ; +; - riscv_core:core|pc[3] ; 0 ; 0 ; +; - riscv_core:core|pc[14] ; 0 ; 0 ; +; - riscv_core:core|pc[8] ; 0 ; 0 ; +; - riscv_core:core|pc[9] ; 0 ; 0 ; +; - riscv_core:core|pc[10] ; 0 ; 0 ; +; - riscv_core:core|pc[11] ; 0 ; 0 ; +; - riscv_core:core|pc[12] ; 0 ; 0 ; +; - riscv_core:core|pc[13] ; 0 ; 0 ; +; - riscv_core:core|pc[30] ; 0 ; 0 ; +; - riscv_core:core|pc[15] ; 0 ; 0 ; +; - riscv_core:core|pc[16] ; 0 ; 0 ; +; - riscv_core:core|pc[17] ; 0 ; 0 ; +; - riscv_core:core|pc[19] ; 0 ; 0 ; +; - riscv_core:core|pc[20] ; 0 ; 0 ; +; - riscv_core:core|pc[21] ; 0 ; 0 ; +; - riscv_core:core|pc[22] ; 0 ; 0 ; +; - riscv_core:core|pc[23] ; 0 ; 0 ; +; - riscv_core:core|pc[24] ; 0 ; 0 ; +; - riscv_core:core|pc[7] ; 0 ; 0 ; +; - riscv_core:core|pc[26] ; 0 ; 0 ; +; - riscv_core:core|pc[27] ; 0 ; 0 ; +; - riscv_core:core|pc[28] ; 0 ; 0 ; +; - riscv_core:core|pc[29] ; 0 ; 0 ; +; - riscv_core:core|pc[25] ; 0 ; 0 ; +; - riscv_core:core|write ; 0 ; 0 ; +; - riscv_core:core|pc[0] ; 0 ; 0 ; +; - riscv_core:core|pc[1] ; 0 ; 0 ; +; - riscv_core:core|state.0110 ; 0 ; 0 ; +; - riscv_core:core|state.1010 ; 0 ; 0 ; +; - riscv_core:core|state.0010 ; 0 ; 0 ; +; - riscv_core:core|pc[31] ; 0 ; 0 ; +; - led0~0 ; 0 ; 0 ; +; - led2~0 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; 0 ; 0 ; +; - riscv_core:core|writedata[0]~2 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxrx_in_processxx3 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 0 ; 0 ; +; - bReadData[13]~1 ; 0 ; 0 ; +; - riscv_core:core|state~25 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_clk_en ; 0 ; 0 ; +; - riscv_core:core|state.0000 ; 0 ; 0 ; +; - riscv_core:core|state~26 ; 0 ; 0 ; +; - readaddr~1 ; 0 ; 0 ; +; - riscv_core:core|state~27 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[3] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[2] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[8] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[7] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[6] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[5] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[4] ; 0 ; 0 ; +; - riscv_core:core|state~28 ; 0 ; 0 ; +; - riscv_core:core|state~29 ; 0 ; 0 ; +; - riscv_core:core|pc[31]~3 ; 0 ; 0 ; +; - riscv_core:core|pc~26 ; 0 ; 0 ; +; - riscv_core:core|pc~28 ; 0 ; 0 ; +; - riscv_core:core|pc~29 ; 0 ; 0 ; +; - riscv_core:core|pc~30 ; 0 ; 0 ; +; - riscv_core:core|Mux5~0 ; 0 ; 0 ; +; - riscv_core:core|Selector247~4 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; 0 ; 0 ; +; - riscv_core:core|state~30 ; 0 ; 0 ; +; - riscv_core:core|divclk[4]~0 ; 0 ; 0 ; +; - riscv_core:core|divclk[3]~1 ; 0 ; 0 ; +; - riscv_core:core|divclk[2]~2 ; 0 ; 0 ; +; - riscv_core:core|divclk[0]~3 ; 0 ; 0 ; +; - riscv_core:core|divclk[1]~4 ; 0 ; 0 ; +; - riscv_core:core|pc[0]~33 ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0 ; 0 ; +; - KEY[3]~_wirecell ; 0 ; 0 ; +; - clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL ; 0 ; 0 ; +; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0]~DUPLICATE ; 0 ; 0 ; +; SW[8] ; ; ; +; - led0~0 ; 1 ; 0 ; +; - led2~0 ; 1 ; 0 ; +; - riscv_core:core|Mux57~2 ; 1 ; 0 ; +; - bReadData[8]~21 ; 1 ; 0 ; +; - riscv_core:core|Selector244~2 ; 1 ; 0 ; +; SW[9] ; ; ; +; - led2[3]~1 ; 1 ; 0 ; +; - led2[3]~4 ; 1 ; 0 ; +; - led2~5 ; 1 ; 0 ; +; - led3~0 ; 1 ; 0 ; +; - led4[4]~0 ; 1 ; 0 ; +; - led4~1 ; 1 ; 0 ; +; - led5~0 ; 1 ; 0 ; +; - bReadData[9]~19 ; 1 ; 0 ; +; - riscv_core:core|Mux9~0 ; 1 ; 0 ; +; - riscv_core:core|Mux56~1 ; 1 ; 0 ; +; CLOCK_50 ; ; ; +; KEY[2] ; ; ; +; - bReadData[12]~0 ; 1 ; 0 ; +; - riscv_core:core|Mux6~0 ; 1 ; 0 ; +; - riscv_core:core|Selector248~4 ; 1 ; 0 ; +; SW[2] ; ; ; +; - bReadData[2]~3 ; 0 ; 0 ; +; SW[3] ; ; ; +; - bReadData[3]~4 ; 0 ; 0 ; +; SW[6] ; ; ; +; - bReadData[6]~5 ; 1 ; 0 ; +; SW[4] ; ; ; +; - bReadData[4]~6 ; 0 ; 0 ; +; SW[5] ; ; ; +; - bReadData[5]~7 ; 0 ; 0 ; +; SW[0] ; ; ; +; - riscv_core:core|Mux57~4 ; 1 ; 0 ; +; SW[7] ; ; ; +; - riscv_core:core|Mux18~0 ; 0 ; 0 ; +; - bReadData[7]~20 ; 0 ; 0 ; +; - riscv_core:core|Mux1~3 ; 0 ; 0 ; +; - riscv_core:core|Mux1~4 ; 0 ; 0 ; +; - riscv_core:core|Mux26~4 ; 0 ; 0 ; +; KEY[0] ; ; ; +; - bReadData[10]~28 ; 0 ; 0 ; +; - riscv_core:core|Mux8~0 ; 0 ; 0 ; +; - riscv_core:core|Selector250~4 ; 0 ; 0 ; +; KEY[1] ; ; ; +; - bReadData[11]~30 ; 1 ; 0 ; +; - riscv_core:core|Mux7~0 ; 1 ; 0 ; +; - riscv_core:core|Selector249~4 ; 1 ; 0 ; +; SW[1] ; ; ; +; - riscv_core:core|Mux56~2 ; 0 ; 0 ; ++-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; KEY[3] ; PIN_Y16 ; 59 ; Sync. clear ; no ; -- ; -- ; -- ; -; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1956 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; -; comb~1 ; LABCELL_X43_Y29_N27 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; led1[5]~0 ; LABCELL_X55_Y28_N27 ; 38 ; Sync. load ; no ; -- ; -- ; -- ; -; led1[5]~3 ; LABCELL_X55_Y28_N33 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; -; led4[0]~0 ; LABCELL_X55_Y28_N30 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; -; ramaddr[3]~0 ; LABCELL_X42_Y28_N57 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; readaddr~0 ; LABCELL_X55_Y25_N45 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|Selector167~1 ; LABCELL_X42_Y25_N45 ; 2 ; Write enable ; no ; -- ; -- ; -- ; -; riscv_core:core|bReadAddr[11]~0 ; LABCELL_X51_Y25_N3 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; LABCELL_X40_Y33_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; LABCELL_X36_Y33_N9 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; LABCELL_X33_Y30_N48 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; LABCELL_X29_Y29_N9 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; LABCELL_X27_Y28_N24 ; 19 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; LABCELL_X30_Y31_N9 ; 30 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; LABCELL_X30_Y35_N42 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; LABCELL_X29_Y32_N18 ; 28 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; LABCELL_X30_Y40_N18 ; 47 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; LABCELL_X29_Y45_N18 ; 37 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; LABCELL_X46_Y33_N42 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; LABCELL_X33_Y42_N24 ; 7 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X36_Y31_N24 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; LABCELL_X33_Y36_N24 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; LABCELL_X36_Y34_N30 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; LABCELL_X37_Y32_N3 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; LABCELL_X46_Y36_N18 ; 18 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; LABCELL_X42_Y35_N33 ; 19 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; LABCELL_X42_Y39_N9 ; 19 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; LABCELL_X36_Y40_N21 ; 29 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; MLABCELL_X34_Y39_N12 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; LABCELL_X36_Y35_N33 ; 31 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; LABCELL_X36_Y28_N18 ; 40 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; MLABCELL_X34_Y25_N39 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; LABCELL_X37_Y36_N21 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; MLABCELL_X47_Y35_N48 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|dstvalue[24]~60 ; LABCELL_X40_Y27_N45 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|dstvalue[2]~0 ; LABCELL_X42_Y28_N42 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|dstvalue[2]~42 ; LABCELL_X53_Y29_N36 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[18]~5 ; LABCELL_X48_Y29_N42 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[19]~4 ; LABCELL_X40_Y27_N0 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[29]~6 ; LABCELL_X40_Y27_N36 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[4]~0 ; LABCELL_X42_Y28_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|imm[4]~1 ; LABCELL_X42_Y28_N21 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|pc[0]~33 ; LABCELL_X42_Y27_N39 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|pc[31]~3 ; MLABCELL_X52_Y27_N57 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|rs2[31]~_Duplicate_6 ; FF_X42_Y30_N59 ; 41 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|state.0010 ; FF_X42_Y25_N41 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; -; riscv_core:core|state.0011 ; FF_X45_Y27_N38 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|state.0100 ; FF_X45_Y27_N35 ; 59 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|state.0101 ; FF_X45_Y27_N23 ; 49 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|writedata[0]~2 ; LABCELL_X42_Y28_N12 ; 69 ; Clock enable ; no ; -- ; -- ; -- ; -; riscv_core:core|writedata[22]~5 ; LABCELL_X40_Y31_N9 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; -; riscv_core:core|writedata[5]~0 ; LABCELL_X40_Y31_N27 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ +; KEY[3] ; PIN_Y16 ; 88 ; Async. clear, Sync. clear ; no ; -- ; -- ; -- ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]~0 ; LABCELL_X55_Y1_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1986 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; +; comb~1 ; LABCELL_X45_Y16_N27 ; 8 ; Write enable ; no ; -- ; -- ; -- ; +; led2[3]~1 ; LABCELL_X53_Y16_N33 ; 38 ; Sync. load ; no ; -- ; -- ; -- ; +; led2[3]~4 ; LABCELL_X53_Y16_N3 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; +; led4[4]~0 ; LABCELL_X53_Y16_N0 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; readaddr[17]~0 ; LABCELL_X36_Y18_N21 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; readaddr~1 ; LABCELL_X40_Y14_N21 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|Selector167~1 ; LABCELL_X48_Y14_N0 ; 2 ; Write enable ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; LABCELL_X56_Y21_N12 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; MLABCELL_X47_Y22_N39 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; MLABCELL_X39_Y22_N24 ; 17 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; LABCELL_X40_Y22_N57 ; 18 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; LABCELL_X40_Y24_N24 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; LABCELL_X37_Y24_N57 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; LABCELL_X33_Y24_N12 ; 31 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; LABCELL_X29_Y25_N12 ; 27 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; LABCELL_X27_Y22_N9 ; 36 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; LABCELL_X31_Y19_N54 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; LABCELL_X53_Y21_N15 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; MLABCELL_X34_Y23_N48 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X40_Y21_N48 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; LABCELL_X33_Y28_N18 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; LABCELL_X42_Y27_N24 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; LABCELL_X40_Y28_N9 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; LABCELL_X40_Y31_N57 ; 15 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; LABCELL_X36_Y29_N51 ; 20 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; LABCELL_X37_Y32_N54 ; 19 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; LABCELL_X45_Y30_N45 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; LABCELL_X48_Y27_N12 ; 37 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; LABCELL_X45_Y25_N24 ; 28 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; LABCELL_X48_Y22_N21 ; 44 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; MLABCELL_X52_Y24_N33 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; LABCELL_X45_Y23_N39 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X35_Y20_N24 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|dstvalue[25]~59 ; MLABCELL_X34_Y13_N45 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|dstvalue[3]~0 ; LABCELL_X35_Y18_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|dstvalue[3]~47 ; LABCELL_X40_Y17_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[12]~5 ; LABCELL_X40_Y18_N33 ; 14 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[19]~4 ; LABCELL_X42_Y18_N24 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[27]~6 ; LABCELL_X42_Y18_N30 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[4]~0 ; LABCELL_X42_Y18_N45 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|imm[4]~1 ; LABCELL_X42_Y18_N42 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|pc[0]~33 ; LABCELL_X40_Y14_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|pc[31]~3 ; LABCELL_X36_Y13_N21 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|rs2[31]~_Duplicate_6 ; FF_X50_Y17_N35 ; 41 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|state.0010 ; FF_X40_Y17_N50 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; riscv_core:core|state.0011 ; FF_X36_Y13_N59 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|state.0100 ; FF_X36_Y13_N56 ; 55 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|state.0101 ; FF_X36_Y13_N53 ; 53 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|writedata[0]~2 ; LABCELL_X42_Y18_N48 ; 69 ; Clock enable ; no ; -- ; -- ; -- ; +; riscv_core:core|writedata[19]~5 ; LABCELL_X51_Y18_N15 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ; +; riscv_core:core|writedata[1]~0 ; LABCELL_X51_Y18_N39 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ; +; uartaddr[0]~0 ; LABCELL_X42_Y18_N36 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -3343,7 +3379,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; +---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+ -; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1956 ; Global Clock ; GCLK0 ; -- ; +; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1986 ; Global Clock ; GCLK0 ; -- ; +---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+ @@ -3352,172 +3388,178 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; riscv_core:core|instr[12] ; 238 ; +; riscv_core:core|instr[12] ; 246 ; ; riscv_core:core|instr[13] ; 170 ; ; riscv_core:core|Equal0~8 ; 97 ; -; riscv_core:core|rs2[1]~_Duplicate_6 ; 91 ; -; riscv_core:core|rs2[0]~_Duplicate_6 ; 80 ; -; riscv_core:core|rs2[3]~_Duplicate_6DUPLICATE ; 75 ; -; riscv_core:core|imm[3]~DUPLICATE ; 70 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign[0] ; 70 ; +; KEY[3]~input ; 88 ; +; riscv_core:core|rs2[1]~_Duplicate_6DUPLICATE ; 80 ; +; riscv_core:core|imm[1] ; 79 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign[0] ; 71 ; +; riscv_core:core|imm[3] ; 71 ; ; riscv_core:core|writedata[0]~2 ; 69 ; ; riscv_core:core|imm[0] ; 67 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|add_sub_31_result_int[32]~1 ; 66 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[31] ; 64 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[31] ; 65 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[957] ; 61 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[957] ; 61 ; -; KEY[3]~input ; 59 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[924] ; 59 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[924] ; 59 ; -; riscv_core:core|state.0100 ; 59 ; -; riscv_core:core|rs1[31]~_Duplicate_6 ; 58 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[858] ; 55 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[858] ; 55 ; +; riscv_core:core|state.0100 ; 55 ; +; riscv_core:core|state.0101 ; 53 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[792] ; 51 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[792] ; 51 ; -; Equal1~0 ; 51 ; +; riscv_core:core|rs1[31]~_Duplicate_6DUPLICATE ; 49 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[759] ; 49 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[759] ; 49 ; -; riscv_core:core|state.0101 ; 49 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; 47 ; +; riscv_core:core|rs2[0]~_Duplicate_6DUPLICATE ; 48 ; +; Equal1~1 ; 48 ; ; riscv_core:core|instr[2] ; 47 ; -; riscv_core:core|imm[1]~DUPLICATE ; 45 ; +; riscv_core:core|rs2[3]~_Duplicate_6 ; 46 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[693] ; 45 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[693] ; 45 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; 44 ; ; riscv_core:core|state.0111 ; 44 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[660] ; 43 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[660] ; 43 ; ; riscv_core:core|rs2[2]~_Duplicate_6 ; 43 ; -; riscv_core:core|instr[14] ; 42 ; +; riscv_core:core|instr[14] ; 43 ; ; riscv_core:core|rs2[31]~_Duplicate_6 ; 41 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; 40 ; ; riscv_core:core|instr[6] ; 40 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[594] ; 39 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[594] ; 39 ; ; riscv_core:core|state.0110 ; 39 ; -; riscv_core:core|imm[2] ; 38 ; -; riscv_core:core|state.0011 ; 38 ; -; led1[5]~0 ; 38 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; 37 ; +; led2[3]~1 ; 38 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; 37 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; 36 ; ; riscv_core:core|state.1010 ; 36 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[528] ; 35 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[528] ; 35 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; 35 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; 35 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 35 ; ; riscv_core:core|instr[30] ; 35 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 34 ; -; riscv_core:core|imm[1] ; 34 ; +; riscv_core:core|state.0011 ; 35 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; 34 ; +; riscv_core:core|imm[19]~4 ; 34 ; ; riscv_core:core|state.0010 ; 34 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[495] ; 33 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[495] ; 33 ; -; Equal0~6 ; 33 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; 31 ; -; riscv_core:core|dstvalue[28]~23 ; 31 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; 30 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; 32 ; +; riscv_core:core|rs2[0]~_Duplicate_6 ; 32 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; 31 ; +; riscv_core:core|dstvalue[30]~28 ; 31 ; +; Equal0~6 ; 31 ; +; riscv_core:core|rs2[3]~_Duplicate_6DUPLICATE ; 30 ; ; riscv_core:core|pc[31]~3 ; 30 ; -; riscv_core:core|pc[2]~1 ; 30 ; +; riscv_core:core|pc[18]~1 ; 30 ; +; riscv_core:core|instr[31] ; 30 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[429] ; 29 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[429] ; 29 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; 29 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; 29 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; 28 ; -; riscv_core:core|dstvalue[2]~42 ; 28 ; -; riscv_core:core|ldaddr[1] ; 28 ; -; riscv_core:core|imm[19]~4 ; 28 ; -; riscv_core:core|rs1[11]~_Duplicate_6 ; 28 ; -; led1[5]~3 ; 28 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; 28 ; +; riscv_core:core|dstvalue[3]~47 ; 28 ; +; led2[3]~4 ; 28 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[396] ; 27 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[396] ; 27 ; -; riscv_core:core|dstvalue[2]~26 ; 27 ; -; riscv_core:core|dstvalue[2]~25 ; 27 ; -; riscv_core:core|rs2[4]~_Duplicate_6DUPLICATE ; 26 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; 27 ; +; riscv_core:core|dstvalue[3]~31 ; 27 ; +; riscv_core:core|dstvalue[3]~30 ; 27 ; +; riscv_core:core|rs1[11]~_Duplicate_6 ; 27 ; ; riscv_core:core|instr[5] ; 26 ; -; riscv_core:core|rs1[9]~_Duplicate_6DUPLICATE ; 25 ; -; riscv_core:core|instr[31] ; 25 ; +; riscv_core:core|rs1[29]~_Duplicate_6 ; 25 ; ; riscv_core:core|rs1[20]~_Duplicate_6 ; 25 ; -; riscv_core:core|rs1[29]~_Duplicate_6DUPLICATE ; 24 ; -; readaddr~0 ; 24 ; +; riscv_core:core|rs1[9]~_Duplicate_6DUPLICATE ; 24 ; +; riscv_core:core|rs2[4]~_Duplicate_6DUPLICATE ; 24 ; +; readaddr~1 ; 24 ; ; riscv_core:core|rs1[30]~_Duplicate_6 ; 24 ; ; riscv_core:core|imm[4] ; 24 ; ; riscv_core:core|rs1[7]~_Duplicate_6 ; 24 ; ; riscv_core:core|rs1[21]~_Duplicate_6 ; 24 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[330] ; 23 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[330] ; 23 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; 23 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; 23 ; ; riscv_core:core|Selector214~5 ; 23 ; ; riscv_core:core|Selector214~4 ; 23 ; ; riscv_core:core|rs1[4]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[13]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[12]~_Duplicate_6 ; 23 ; +; riscv_core:core|rs1[10]~_Duplicate_6 ; 23 ; +; riscv_core:core|rs1[5]~_Duplicate_6 ; 23 ; +; riscv_core:core|rs1[3]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[23]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[22]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[18]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[27]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[25]~_Duplicate_6 ; 23 ; ; riscv_core:core|rs1[0]~_Duplicate_6 ; 23 ; +; riscv_core:core|imm[2] ; 23 ; ; riscv_core:core|rs1[2]~_Duplicate_6 ; 23 ; -; riscv_core:core|dstvalue[5]~45 ; 22 ; -; riscv_core:core|dstvalue[5]~44 ; 22 ; -; riscv_core:core|rs1[6]~_Duplicate_6 ; 22 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; 21 ; +; riscv_core:core|ldaddr[1]~DUPLICATE ; 22 ; +; riscv_core:core|rs1[19]~_Duplicate_6DUPLICATE ; 22 ; +; riscv_core:core|dstvalue[6]~50 ; 22 ; +; riscv_core:core|dstvalue[6]~49 ; 22 ; +; riscv_core:core|rs1[6]~_Duplicate_6 ; 21 ; ; riscv_core:core|rs1[24]~_Duplicate_6 ; 21 ; ; riscv_core:core|rs1[17]~_Duplicate_6 ; 21 ; ; riscv_core:core|rs1[14]~_Duplicate_6 ; 21 ; ; riscv_core:core|rs1[26]~_Duplicate_6 ; 21 ; +; riscv_core:core|rs1[8]~_Duplicate_6 ; 21 ; ; riscv_core:core|instr[3] ; 21 ; -; riscv_core:core|rs1[28]~_Duplicate_6DUPLICATE ; 20 ; -; riscv_core:core|ldaddr[0] ; 20 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; 20 ; ; riscv_core:core|rs1[15]~_Duplicate_6 ; 20 ; ; riscv_core:core|rs1[1]~_Duplicate_6 ; 20 ; -; riscv_core:core|rs1[10]~_Duplicate_6DUPLICATE ; 19 ; -; riscv_core:core|rs1[8]~_Duplicate_6DUPLICATE ; 19 ; +; riscv_core:core|ldaddr[0]~DUPLICATE ; 19 ; +; riscv_core:core|rs1[28]~_Duplicate_6DUPLICATE ; 19 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[264] ; 19 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[264] ; 19 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; 19 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; 19 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; 19 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; 19 ; ; riscv_core:core|instr[25] ; 19 ; ; riscv_core:core|rs1[16]~_Duplicate_6 ; 19 ; -; riscv_core:core|rs1[19]~_Duplicate_6DUPLICATE ; 18 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; 18 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; 18 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; 18 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; 18 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[231] ; 17 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[231] ; 17 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; 17 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; 17 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; 17 ; -; riscv_core:core|writedata[22]~3 ; 17 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; 17 ; +; riscv_core:core|writedata[19]~3 ; 17 ; ; riscv_core:core|instr[4] ; 17 ; -; riscv_core:core|rs1[5]~_Duplicate_6DUPLICATE ; 16 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 16 ; -; riscv_core:core|dstvalue[2]~37 ; 16 ; -; riscv_core:core|dstvalue[2]~36 ; 16 ; -; riscv_core:core|dstvalue[2]~29 ; 16 ; -; riscv_core:core|writedata[5]~0 ; 16 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[3] ; 16 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[5] ; 16 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1]~DUPLICATE ; 15 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; 15 ; -; riscv_core:core|dstvalue[2]~31 ; 15 ; -; riscv_core:core|dstvalue[2]~30 ; 15 ; +; riscv_core:core|dstvalue[3]~34 ; 16 ; +; riscv_core:core|writedata[1]~0 ; 16 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[28] ; 16 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0]~DUPLICATE ; 15 ; +; riscv_core:core|imm[2]~DUPLICATE ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; 15 ; +; riscv_core:core|dstvalue[3]~42 ; 15 ; +; riscv_core:core|dstvalue[3]~41 ; 15 ; +; riscv_core:core|dstvalue[3]~36 ; 15 ; +; riscv_core:core|dstvalue[3]~35 ; 15 ; ; riscv_core:core|state.0001 ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; 15 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; 15 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[28] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[29] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[30] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[7] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[1] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[3] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[4] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[8] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[9] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[10] ; 15 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[11] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[13] ; 15 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[17] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[18] ; 15 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[19] ; 15 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2]~DUPLICATE ; 14 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; 14 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; 14 ; -; riscv_core:core|dstvalue[2]~28 ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[0] ; 15 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; 14 ; +; riscv_core:core|imm[12]~5 ; 14 ; ; riscv_core:core|Equal7~0 ; 14 ; -; led4[0]~0 ; 14 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 14 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 14 ; +; led4[4]~0 ; 14 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; 14 ; ; riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated|Mult0~523 ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[15] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[22] ; 14 ; @@ -3526,33 +3568,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[25] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[26] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[27] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[7] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[1] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[29] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[30] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[2] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[5] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[6] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[8] ; 14 ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[11] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[12] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[13] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[14] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[16] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[17] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[20] ; 14 ; ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[21] ; 14 ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[0] ; 14 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[165] ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[165] ; 13 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; 13 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; 13 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; 13 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; 13 ; -; riscv_core:core|dstvalue[2]~1 ; 13 ; +; riscv_core:core|dstvalue[3]~1 ; 13 ; ; riscv_core:core|state.1000 ; 13 ; -; riscv_core:core|imm[29]~6 ; 13 ; -; ramaddr[3]~0 ; 13 ; +; riscv_core:core|imm[27]~6 ; 13 ; +; uartaddr[0]~0 ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; 13 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; 13 ; -; riscv_core:core|rs1[3]~_Duplicate_6DUPLICATE ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 12 ; @@ -3563,46 +3600,46 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a0~portb_address_reg1FITTER_CREATED_FF ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a0~portb_address_reg0FITTER_CREATED_FF ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[2] ; 12 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1] ; 12 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0] ; 12 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[1] ; 12 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; 12 ; -; riscv_core:core|dstvalue[24]~60 ; 12 ; -; riscv_core:core|dstvalue[24]~56 ; 12 ; -; riscv_core:core|dstvalue[24]~55 ; 12 ; -; riscv_core:core|dstvalue[24]~54 ; 12 ; -; riscv_core:core|dstvalue[24]~53 ; 12 ; -; riscv_core:core|dstvalue[2]~40 ; 12 ; -; riscv_core:core|dstvalue[2]~38 ; 12 ; -; riscv_core:core|dstvalue[2]~34 ; 12 ; -; riscv_core:core|dstvalue[2]~32 ; 12 ; -; riscv_core:core|dstvalue[2]~12 ; 12 ; -; riscv_core:core|rs2[7]~_Duplicate_6 ; 12 ; +; riscv_core:core|dstvalue[25]~59 ; 12 ; +; riscv_core:core|dstvalue[25]~55 ; 12 ; +; riscv_core:core|dstvalue[25]~54 ; 12 ; +; riscv_core:core|dstvalue[25]~53 ; 12 ; +; riscv_core:core|dstvalue[25]~52 ; 12 ; +; riscv_core:core|dstvalue[3]~45 ; 12 ; +; riscv_core:core|dstvalue[3]~43 ; 12 ; +; riscv_core:core|dstvalue[3]~39 ; 12 ; +; riscv_core:core|dstvalue[3]~37 ; 12 ; +; riscv_core:core|dstvalue[3]~16 ; 12 ; ; riscv_core:core|rs2[6]~_Duplicate_6 ; 12 ; +; riscv_core:core|rs2[5]~_Duplicate_6 ; 12 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; 12 ; +; riscv_core:core|rs2[7]~_Duplicate_6DUPLICATE ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[0] ; 11 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[132] ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[132] ; 11 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0] ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; 11 ; -; riscv_core:core|Mux26~3 ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; 11 ; ; riscv_core:core|rs2[15]~_Duplicate_6 ; 11 ; -; riscv_core:core|dstvalue[2]~0 ; 11 ; -; riscv_core:core|rs1[3]~_Duplicate_6 ; 11 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 11 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 11 ; ; riscv_core:core|rs2[14]~_Duplicate_6 ; 11 ; -; riscv_core:core|rs2[13]~_Duplicate_6 ; 11 ; ; riscv_core:core|rs2[12]~_Duplicate_6 ; 11 ; -; riscv_core:core|rs2[10]~_Duplicate_6 ; 11 ; +; riscv_core:core|rs2[11]~_Duplicate_6 ; 11 ; ; riscv_core:core|rs2[9]~_Duplicate_6 ; 11 ; ; riscv_core:core|rs2[8]~_Duplicate_6 ; 11 ; +; riscv_core:core|rs2[1]~_Duplicate_6 ; 11 ; ; led0~0 ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; 11 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; 11 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 11 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; 10 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 10 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 10 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 10 ; @@ -3624,53 +3661,56 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a0~portb_address_reg0FITTER_CREATED_FF ; 10 ; ; SW[9]~input ; 10 ; ; KEY[3]~_wirecell ; 10 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; 10 ; +; riscv_core:core|Mux26~2 ; 10 ; ; riscv_core:core|rs2[23]~_Duplicate_6 ; 10 ; +; riscv_core:core|dstvalue[3]~0 ; 10 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]~0 ; 10 ; +; riscv_core:core|rs2[30]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[29]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[22]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[21]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[20]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[19]~_Duplicate_6 ; 10 ; -; riscv_core:core|rs2[17]~_Duplicate_6 ; 10 ; ; riscv_core:core|rs2[16]~_Duplicate_6 ; 10 ; -; riscv_core:core|writedata[22]~4 ; 10 ; -; riscv_core:core|rs2[18]~_Duplicate_6DUPLICATE ; 9 ; -; riscv_core:core|rs2[11]~_Duplicate_6DUPLICATE ; 9 ; -; riscv_core:core|imm[18]~5 ; 9 ; +; riscv_core:core|writedata[19]~4 ; 10 ; +; riscv_core:core|rs2[13]~_Duplicate_6 ; 10 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; 9 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; 9 ; ; riscv_core:core|state.0000 ; 9 ; -; riscv_core:core|rs2[28]~_Duplicate_6 ; 9 ; +; riscv_core:core|rs1[31]~_Duplicate_6 ; 9 ; ; riscv_core:core|rs2[27]~_Duplicate_6 ; 9 ; ; riscv_core:core|rs2[26]~_Duplicate_6 ; 9 ; ; riscv_core:core|rs2[25]~_Duplicate_6 ; 9 ; ; riscv_core:core|rs2[24]~_Duplicate_6 ; 9 ; -; riscv_core:core|writedata[22]~5 ; 9 ; +; riscv_core:core|writedata[19]~5 ; 9 ; ; riscv_core:core|writeaddr[1] ; 9 ; ; riscv_core:core|writeaddr[0] ; 9 ; ; riscv_core:core|write ; 9 ; -; riscv_core:core|rs2[5]~_Duplicate_6DUPLICATE ; 8 ; +; riscv_core:core|rs2[18]~_Duplicate_6DUPLICATE ; 8 ; +; riscv_core:core|rs2[10]~_Duplicate_6DUPLICATE ; 8 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[64] ; 8 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[224] ; 8 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; 8 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; 8 ; -; riscv_core:core|dstvalue[8]~47 ; 8 ; -; ramaddr[10]~13 ; 8 ; -; ramaddr[9]~12 ; 8 ; -; ramaddr[8]~11 ; 8 ; -; ramaddr[7]~10 ; 8 ; -; ramaddr[6]~9 ; 8 ; -; ramaddr[5]~8 ; 8 ; -; ramaddr[4]~7 ; 8 ; -; ramaddr[3]~6 ; 8 ; -; ramaddr[2]~5 ; 8 ; -; ramaddr[1]~4 ; 8 ; -; ramaddr[0]~3 ; 8 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|Equal0~1 ; 8 ; +; ramaddr[10]~7 ; 8 ; +; ramaddr[9]~6 ; 8 ; +; ramaddr[8]~5 ; 8 ; +; ramaddr[7]~4 ; 8 ; +; ramaddr[6]~3 ; 8 ; +; ramaddr[5]~2 ; 8 ; +; ramaddr[4]~1 ; 8 ; +; ramaddr[3]~0 ; 8 ; +; uartaddr[2]~5 ; 8 ; +; uartaddr[1]~4 ; 8 ; +; uartaddr[0]~3 ; 8 ; ; comb~1 ; 8 ; -; riscv_core:core|imm[11] ; 8 ; -; riscv_core:core|writedata[31]~7 ; 8 ; -; riscv_core:core|writedata[31]~6 ; 8 ; +; riscv_core:core|writedata[27]~7 ; 8 ; +; riscv_core:core|writedata[27]~6 ; 8 ; ; riscv_core:core|Equal3~3 ; 8 ; ; led2~0 ; 8 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 8 ; -; riscv_core:core|rs2[30]~_Duplicate_6DUPLICATE ; 7 ; +; riscv_core:core|rs2[28]~_Duplicate_6DUPLICATE ; 7 ; +; riscv_core:core|rs2[17]~_Duplicate_6DUPLICATE ; 7 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 7 ; @@ -3678,34 +3718,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[128] ; 7 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[32] ; 7 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[160] ; 7 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; 7 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[224] ; 7 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ; 7 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[66] ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[66] ; 7 ; -; riscv_core:core|imm[31] ; 7 ; -; riscv_core:core|imm[10] ; 7 ; -; riscv_core:core|imm[6] ; 7 ; -; riscv_core:core|rs1[5]~_Duplicate_6 ; 7 ; -; riscv_core:core|rs1[19]~_Duplicate_6 ; 7 ; -; riscv_core:core|imm[9] ; 7 ; -; riscv_core:core|imm[8] ; 7 ; +; riscv_core:core|Selector241~0 ; 7 ; +; riscv_core:core|Selector244~0 ; 7 ; +; riscv_core:core|imm[11] ; 7 ; +; riscv_core:core|rs2[4]~_Duplicate_6 ; 7 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|add_sub_31_result_int[32]~1 ; 7 ; ; riscv_core:core|imm[30] ; 7 ; ; riscv_core:core|imm[29] ; 7 ; ; riscv_core:core|imm[28] ; 7 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2]~DUPLICATE ; 6 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0]~DUPLICATE ; 6 ; -; SW[7]~input ; 6 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; 6 ; ; riscv_core:core|Selector125~0 ; 6 ; ; riscv_core:core|Mux26~1 ; 6 ; ; riscv_core:core|Selector249~14 ; 6 ; +; riscv_core:core|dstvalue[3]~33 ; 6 ; ; riscv_core:core|Selector121~0 ; 6 ; ; riscv_core:core|always7~0 ; 6 ; -; riscv_core:core|imm[4]~1 ; 6 ; -; ramaddr[3]~2 ; 6 ; -; ramaddr[3]~1 ; 6 ; +; uartaddr[0]~2 ; 6 ; +; uartaddr[0]~1 ; 6 ; +; riscv_core:core|imm[10] ; 6 ; ; riscv_core:core|imm[7] ; 6 ; -; riscv_core:core|imm[5] ; 6 ; +; riscv_core:core|imm[6] ; 6 ; +; riscv_core:core|imm[9] ; 6 ; +; riscv_core:core|imm[8] ; 6 ; ; riscv_core:core|writedata[14] ; 6 ; ; riscv_core:core|writedata[13] ; 6 ; ; riscv_core:core|writedata[12] ; 6 ; @@ -3713,17 +3753,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|writedata[10] ; 6 ; ; riscv_core:core|writedata[9] ; 6 ; ; riscv_core:core|writedata[8] ; 6 ; -; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|q_a[23] ; 6 ; -; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|q_a[7] ; 6 ; -; riscv_core:core|imm[12] ; 6 ; +; riscv_core:core|imm[13] ; 6 ; ; riscv_core:core|imm[24] ; 6 ; ; riscv_core:core|imm[23] ; 6 ; ; riscv_core:core|imm[20] ; 6 ; -; riscv_core:core|imm[18] ; 6 ; -; riscv_core:core|imm[17] ; 6 ; -; riscv_core:core|imm[16] ; 6 ; -; riscv_core:core|imm[15] ; 6 ; -; riscv_core:core|imm[14] ; 6 ; ; riscv_core:core|imm[27] ; 6 ; ; riscv_core:core|imm[26] ; 6 ; ; riscv_core:core|imm[19] ; 6 ; @@ -3734,33 +3767,52 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|writedata[2] ; 6 ; ; riscv_core:core|writedata[1] ; 6 ; ; riscv_core:core|writedata[0] ; 6 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256]~DUPLICATE ; 5 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2]~DUPLICATE ; 5 ; -; riscv_core:core|imm[13]~DUPLICATE ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1]~DUPLICATE ; 5 ; +; riscv_core:core|imm[5]~DUPLICATE ; 5 ; +; riscv_core:core|imm[12]~DUPLICATE ; 5 ; +; riscv_core:core|imm[15]~DUPLICATE ; 5 ; +; SW[7]~input ; 5 ; ; SW[8]~input ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[135] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[134] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[133] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[132] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[131] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[130] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[129] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[137] ; 5 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[192] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[69] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[225] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[276] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[260] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[259] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[258] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[225] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[35] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[70] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[274] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[272] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[278] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[258] ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; 5 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; 5 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; 5 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[332] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[338] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[337] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[336] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[335] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[330] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[324] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[322] ; 5 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; 5 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; 5 ; -; riscv_core:core|Mux26~6 ; 5 ; -; riscv_core:core|Mux1~0 ; 5 ; -; riscv_core:core|dstvalue[2]~41 ; 5 ; -; riscv_core:core|dstvalue[2]~35 ; 5 ; -; riscv_core:core|dstvalue[2]~27 ; 5 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[72] ; 5 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[351] ; 5 ; +; riscv_core:core|dstvalue[3]~46 ; 5 ; +; riscv_core:core|dstvalue[3]~40 ; 5 ; +; riscv_core:core|dstvalue[3]~32 ; 5 ; +; bReadData[23]~18 ; 5 ; ; riscv_core:core|Equal0~7 ; 5 ; -; riscv_core:core|dstreg[4]~1 ; 5 ; +; riscv_core:core|dstreg[0]~1 ; 5 ; +; riscv_core:core|imm[4]~1 ; 5 ; +; readaddr[17]~0 ; 5 ; ; bReadData[17]~10 ; 5 ; ; bReadData[16]~9 ; 5 ; -; riscv_core:core|rs1[10]~_Duplicate_6 ; 5 ; -; riscv_core:core|rs2[4]~_Duplicate_6 ; 5 ; ; riscv_core:core|writedata[30] ; 5 ; ; riscv_core:core|writedata[29] ; 5 ; ; riscv_core:core|writedata[28] ; 5 ; @@ -3768,6 +3820,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|writedata[26] ; 5 ; ; riscv_core:core|writedata[25] ; 5 ; ; riscv_core:core|writedata[24] ; 5 ; +; riscv_core:core|Mux26~5 ; 5 ; ; riscv_core:core|imm[21] ; 5 ; ; riscv_core:core|Add0~101 ; 5 ; ; riscv_core:core|Add0~97 ; 5 ; @@ -3781,70 +3834,55 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|writedata[18] ; 5 ; ; riscv_core:core|writedata[17] ; 5 ; ; riscv_core:core|writedata[16] ; 5 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288]~DUPLICATE ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0]~DUPLICATE ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3]~DUPLICATE ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257]~DUPLICATE ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1]~DUPLICATE ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0]~DUPLICATE ; 4 ; +; riscv_core:core|imm[22]~DUPLICATE ; 4 ; +; riscv_core:core|imm[18]~DUPLICATE ; 4 ; +; riscv_core:core|imm[17]~DUPLICATE ; 4 ; +; riscv_core:core|imm[14]~DUPLICATE ; 4 ; ; riscv_core:core|imm[25]~DUPLICATE ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[65] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[65] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[66] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[66] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[135] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[135] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[134] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[134] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[133] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[133] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[132] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[132] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[131] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[131] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[130] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[130] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[129] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[129] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[67] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[136] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[171] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[171] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[170] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[170] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[169] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[168] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[168] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[167] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[166] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[165] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[164] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[163] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[162] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[161] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[33] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[33] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[68] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[68] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[137] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[137] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[172] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[172] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[34] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[34] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[69] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[69] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[138] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[138] ; 4 ; @@ -3884,27 +3922,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[227] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[226] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[226] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[225] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[225] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[35] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[35] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[70] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[277] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[277] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[276] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[276] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[275] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[275] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[139] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[139] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[274] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[274] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[273] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[273] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[271] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[272] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[272] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[271] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[174] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[270] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[270] ; 4 ; @@ -3924,16 +3957,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[264] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[264] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[263] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[278] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[278] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[262] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[262] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[261] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[261] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[260] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[260] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[259] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[259] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[258] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[258] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[36] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[36] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[71] ; 4 ; @@ -3967,22 +4001,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[339] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[339] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[338] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[338] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[337] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[337] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[335] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[336] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[336] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[335] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[334] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[334] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[333] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[333] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[332] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[332] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[331] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[331] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[330] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[330] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[329] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[329] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[327] ; 4 ; @@ -3994,12 +4024,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[325] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[325] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[324] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[324] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[317] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[323] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[323] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[322] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[322] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[321] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[321] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[29] ; 4 ; @@ -4011,12 +4038,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[0] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[37] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[37] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[38] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[73] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[72] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[141] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[141] ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[142] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[177] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[176] ; 4 ; @@ -4028,10 +4054,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[246] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[280] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[280] ; 4 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[349] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[350] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; 4 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[351] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; 4 ; ; riscv_core:core|writedata[31] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~31 ; 4 ; @@ -4040,16 +4065,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~28 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~27 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~25 ; 4 ; +; riscv_core:core|Mux1~0 ; 4 ; ; riscv_core:core|ShiftLeft0~5 ; 4 ; ; riscv_core:core|ShiftLeft1~5 ; 4 ; ; riscv_core:core|ShiftLeft0~3 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~23 ; 4 ; ; riscv_core:core|ShiftRight0~26 ; 4 ; -; riscv_core:core|dstvalue[2]~39 ; 4 ; +; riscv_core:core|dstvalue[3]~44 ; 4 ; ; riscv_core:core|ShiftLeft1~3 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~20 ; 4 ; ; riscv_core:core|ShiftRight1~28 ; 4 ; -; riscv_core:core|dstvalue[2]~33 ; 4 ; +; riscv_core:core|dstvalue[3]~38 ; 4 ; ; riscv_core:core|ShiftLeft1~1 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~16 ; 4 ; ; riscv_core:core|ShiftRight1~17 ; 4 ; @@ -4057,29 +4083,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~13 ; 4 ; ; riscv_core:core|ShiftRight0~15 ; 4 ; ; riscv_core:core|dstvalue[7] ; 4 ; -; bReadData[22]~15 ; 4 ; +; bReadData[22]~17 ; 4 ; ; riscv_core:core|writedata[15] ; 4 ; -; bReadData[20]~13 ; 4 ; -; riscv_core:core|Selector252~0 ; 4 ; +; riscv_core:core|Selector252~1 ; 4 ; +; bReadData[24]~14 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~10 ; 4 ; ; riscv_core:core|ShiftRight1~6 ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~4 ; 4 ; ; riscv_core:core|ShiftRight0~5 ; 4 ; ; riscv_core:core|divclk[0] ; 4 ; -; riscv_core:core|imm[1]~7 ; 4 ; +; riscv_core:core|imm[3]~7 ; 4 ; ; riscv_core:core|instr[7] ; 4 ; ; riscv_core:core|WideOr20 ; 4 ; ; bReadData[19]~12 ; 4 ; ; bReadData[18]~11 ; 4 ; ; riscv_core:core|instr[22] ; 4 ; -; Equal0~2 ; 4 ; -; riscv_core:core|rs2[5]~_Duplicate_6 ; 4 ; +; bReadData[15]~8 ; 4 ; +; riscv_core:core|instr[20] ; 4 ; +; riscv_core:core|imm[31] ; 4 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 4 ; ; riscv_core:core|Equal2~0 ; 4 ; ; riscv_core:core|writeaddr[2] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[1] ; 4 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[2] ; 4 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 4 ; ; riscv_core:core|writedata[7] ; 4 ; ; riscv_core:core|writedata[23] ; 4 ; +; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|q_a[23] ; 4 ; ; riscv_core:core|pc[11] ; 4 ; ; riscv_core:core|pc[10] ; 4 ; ; riscv_core:core|pc[9] ; 4 ; @@ -4112,16 +4143,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|Add0~9 ; 4 ; ; riscv_core:core|Add0~5 ; 4 ; ; riscv_core:core|Add0~1 ; 4 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257]~DUPLICATE ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1]~DUPLICATE ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0]~DUPLICATE ; 3 ; -; riscv_core:core|instr[20]~DUPLICATE ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0]~DUPLICATE ; 3 ; -; riscv_core:core|imm[22]~DUPLICATE ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162]~DUPLICATE ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174]~DUPLICATE ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73]~DUPLICATE ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0]~DUPLICATE ; 3 ; +; riscv_core:core|imm[31]~DUPLICATE ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 3 ; +; riscv_core:core|imm[16]~DUPLICATE ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a6 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a1 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a2 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ram_block6a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ram_block6a6 ; 3 ; @@ -4130,7 +4168,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a6 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a1 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a2 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a1 ; 3 ; @@ -4138,19 +4176,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a5 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a6 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a1 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a2 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a5 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a1 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a6 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a1 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a6 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a2 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a1 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a6 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a8 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a7 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a1 ; 3 ; @@ -4161,7 +4199,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; KEY[0]~input ; 3 ; ; KEY[2]~input ; 3 ; ; led2~0_wirecell ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[100] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[100] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[99] ; 3 ; @@ -4173,11 +4210,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[58] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[58] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[101] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[101] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[59] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[59] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[102] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[103] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[103] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[206] ; 3 ; @@ -4218,7 +4257,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[105] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[209] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[209] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cmpr4_aeb_int~0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|op_2~0 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[314] ; 3 ; @@ -4229,24 +4267,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[312] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[312] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[311] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[310] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[309] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[309] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[106] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[106] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[308] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[308] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[307] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[307] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[306] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[305] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[305] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cmpr4_aeb_int~0 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|op_2~0 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[303] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[304] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[303] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[302] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[302] ; 3 ; @@ -4270,88 +4306,88 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[294] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[293] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[293] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[292] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[292] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[291] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[291] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[290] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[289] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[33]~47 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[315] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[315] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[316] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[317] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[317] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[318] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[319] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[2] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[3] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[22] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[27] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[21] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[20] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[28] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[26] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[18] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[15] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[38] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[38] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[51] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[58] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[47] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[53] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[52] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[42] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[40] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[61] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[43] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[41] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297]~24 ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[76] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297]~24 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[82] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[81] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[76] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[88] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[87] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[86] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[75] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[107] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[118] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[115] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[125] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[119] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[124] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[114] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[111] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[126] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[111] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[110] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[114] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[115] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462]~13 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[158] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[154] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[146] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462]~13 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[152] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[148] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[157] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561]~9 ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[184] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[181] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561]~9 ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[185] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[183] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[181] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[211] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[211] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[215] ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[218] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726]~3 ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[252] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[251] ; 3 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[250] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726]~3 ; 3 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[249] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[255] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[251] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[281] ; 3 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[281] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[286] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[284] ; 3 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; 3 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; 3 ; -; riscv_core:core|dstvalue[28]~66 ; 3 ; -; riscv_core:core|dstvalue[28]~65 ; 3 ; -; riscv_core:core|dstvalue[28]~64 ; 3 ; -; riscv_core:core|dstvalue[28]~63 ; 3 ; -; riscv_core:core|dstvalue[28]~62 ; 3 ; -; riscv_core:core|dstvalue[28]~61 ; 3 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|always2~0 ; 3 ; +; riscv_core:core|dstvalue[30]~65 ; 3 ; +; riscv_core:core|dstvalue[30]~64 ; 3 ; +; riscv_core:core|dstvalue[30]~63 ; 3 ; +; riscv_core:core|dstvalue[30]~62 ; 3 ; +; riscv_core:core|dstvalue[30]~61 ; 3 ; +; riscv_core:core|dstvalue[30]~60 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~33 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~32 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~26 ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~24 ; 3 ; -; riscv_core:core|ShiftLeft0~22 ; 3 ; -; riscv_core:core|ShiftLeft0~21 ; 3 ; -; riscv_core:core|ShiftLeft1~22 ; 3 ; -; riscv_core:core|ShiftLeft1~21 ; 3 ; -; riscv_core:core|ShiftLeft0~19 ; 3 ; +; riscv_core:core|Mux2~0 ; 3 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ @@ -4360,18 +4396,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+ ; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+ -; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 2048 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 65536 ; 2048 ; 32 ; -- ; -- ; 65536 ; 8 ; 0 ; test.mif ; M10K_X49_Y27_N0, M10K_X49_Y26_N0, M10K_X41_Y27_N0, M10K_X41_Y26_N0, M10K_X49_Y28_N0, M10K_X38_Y28_N0, M10K_X41_Y28_N0, M10K_X38_Y26_N0 ; Don't care ; New data ; New data ; No - Address Too Wide ; -; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 32 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1024 ; 32 ; 32 ; -- ; -- ; 1024 ; 1 ; 0 ; None ; M10K_X41_Y25_N0 ; Don't care ; New data ; New data ; No - Single Port Feed Through New Data with Unregistered Data Out ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 11 ; 10 ; 11 ; 10 ; yes ; no ; no ; yes ; 110 ; 11 ; 10 ; 11 ; 10 ; 110 ; 0 ; 10 ; None ; LAB_X34_Y42_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 10 ; 10 ; 10 ; yes ; no ; no ; yes ; 100 ; 10 ; 10 ; 10 ; 10 ; 100 ; 0 ; 10 ; None ; LAB_X39_Y31_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 9 ; 12 ; 9 ; 12 ; yes ; no ; no ; yes ; 108 ; 9 ; 12 ; 9 ; 12 ; 108 ; 0 ; 12 ; None ; LAB_X34_Y36_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 8 ; 10 ; 8 ; 10 ; yes ; no ; no ; yes ; 80 ; 8 ; 10 ; 8 ; 10 ; 80 ; 0 ; 10 ; None ; LAB_X34_Y34_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 7 ; 10 ; 7 ; 10 ; yes ; no ; no ; yes ; 70 ; 7 ; 10 ; 7 ; 10 ; 70 ; 0 ; 10 ; None ; LAB_X47_Y33_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 6 ; 12 ; 6 ; 12 ; yes ; no ; no ; yes ; 72 ; 6 ; 12 ; 6 ; 12 ; 72 ; 0 ; 12 ; None ; LAB_X39_Y32_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 5 ; 10 ; 5 ; 10 ; yes ; no ; no ; yes ; 50 ; 5 ; 10 ; 5 ; 10 ; 50 ; 0 ; 10 ; None ; LAB_X34_Y31_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 4 ; 10 ; 4 ; 10 ; yes ; no ; no ; yes ; 40 ; 4 ; 10 ; 4 ; 10 ; 40 ; 0 ; 10 ; None ; LAB_X34_Y37_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 3 ; 12 ; 3 ; 12 ; yes ; no ; no ; yes ; 36 ; 3 ; 12 ; 3 ; 12 ; 36 ; 0 ; 12 ; None ; LAB_X34_Y32_N0 ; ; ; ; ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 7 ; 10 ; 7 ; yes ; no ; no ; yes ; 70 ; 10 ; 7 ; 10 ; 7 ; 70 ; 0 ; 7 ; None ; LAB_X39_Y35_N0 ; ; ; ; ; +; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 2048 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 65536 ; 2048 ; 32 ; -- ; -- ; 65536 ; 8 ; 0 ; test.mif ; M10K_X38_Y16_N0, M10K_X38_Y18_N0, M10K_X41_Y15_N0, M10K_X41_Y17_N0, M10K_X41_Y16_N0, M10K_X38_Y15_N0, M10K_X38_Y17_N0, M10K_X41_Y18_N0 ; Don't care ; New data ; New data ; No - Address Too Wide ; +; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 32 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1024 ; 32 ; 32 ; -- ; -- ; 1024 ; 1 ; 0 ; None ; M10K_X49_Y14_N0 ; Don't care ; New data ; New data ; No - Single Port Feed Through New Data with Unregistered Data Out ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 11 ; 10 ; 11 ; 10 ; yes ; no ; no ; yes ; 110 ; 11 ; 10 ; 11 ; 10 ; 110 ; 0 ; 10 ; None ; LAB_X34_Y21_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 10 ; 10 ; 10 ; yes ; no ; no ; yes ; 100 ; 10 ; 10 ; 10 ; 10 ; 100 ; 0 ; 10 ; None ; LAB_X39_Y21_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 9 ; 12 ; 9 ; 12 ; yes ; no ; no ; yes ; 108 ; 9 ; 12 ; 9 ; 12 ; 108 ; 0 ; 12 ; None ; LAB_X34_Y28_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 8 ; 10 ; 8 ; 10 ; yes ; no ; no ; yes ; 80 ; 8 ; 10 ; 8 ; 10 ; 80 ; 0 ; 10 ; None ; LAB_X39_Y27_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 7 ; 10 ; 7 ; 10 ; yes ; no ; no ; yes ; 70 ; 7 ; 10 ; 7 ; 10 ; 70 ; 0 ; 10 ; None ; LAB_X34_Y22_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 6 ; 12 ; 6 ; 12 ; yes ; no ; no ; yes ; 72 ; 6 ; 12 ; 6 ; 12 ; 72 ; 0 ; 12 ; None ; LAB_X39_Y29_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 5 ; 10 ; 5 ; 10 ; yes ; no ; no ; yes ; 50 ; 5 ; 10 ; 5 ; 10 ; 50 ; 0 ; 10 ; None ; LAB_X34_Y26_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 4 ; 10 ; 4 ; 10 ; yes ; no ; no ; yes ; 40 ; 4 ; 10 ; 4 ; 10 ; 40 ; 0 ; 10 ; None ; LAB_X47_Y24_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 3 ; 12 ; 3 ; 12 ; yes ; no ; no ; yes ; 36 ; 3 ; 12 ; 3 ; 12 ; 36 ; 0 ; 12 ; None ; LAB_X47_Y25_N0 ; ; ; ; ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 7 ; 10 ; 7 ; yes ; no ; no ; yes ; 70 ; 10 ; 7 ; 10 ; 7 ; 70 ; 0 ; 7 ; None ; LAB_X34_Y20_N0 ; ; ; ; ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+ Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. @@ -4399,14 +4435,14 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +---------------------------------------------+-------------------------+ ; Routing Resource Type ; Usage ; +---------------------------------------------+-------------------------+ -; Block interconnects ; 8,830 / 289,320 ( 3 % ) ; -; C12 interconnects ; 268 / 13,420 ( 2 % ) ; -; C2 interconnects ; 3,408 / 119,108 ( 3 % ) ; -; C4 interconnects ; 1,823 / 56,300 ( 3 % ) ; +; Block interconnects ; 8,941 / 289,320 ( 3 % ) ; +; C12 interconnects ; 94 / 13,420 ( < 1 % ) ; +; C2 interconnects ; 3,192 / 119,108 ( 3 % ) ; +; C4 interconnects ; 1,703 / 56,300 ( 3 % ) ; ; DQS bus muxes ; 0 / 25 ( 0 % ) ; ; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; ; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; -; Direct links ; 790 / 289,320 ( < 1 % ) ; +; Direct links ; 917 / 289,320 ( < 1 % ) ; ; Global clocks ; 1 / 16 ( 6 % ) ; ; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; ; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; @@ -4462,13 +4498,13 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. ; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; ; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; ; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; -; Local interconnects ; 1,555 / 84,580 ( 2 % ) ; +; Local interconnects ; 1,536 / 84,580 ( 2 % ) ; ; Quadrant clocks ; 0 / 66 ( 0 % ) ; -; R14 interconnects ; 353 / 12,676 ( 3 % ) ; -; R14/C12 interconnect drivers ; 584 / 20,720 ( 3 % ) ; -; R3 interconnects ; 4,128 / 130,992 ( 3 % ) ; -; R6 interconnects ; 6,375 / 266,960 ( 2 % ) ; -; Spine clocks ; 4 / 360 ( 1 % ) ; +; R14 interconnects ; 313 / 12,676 ( 2 % ) ; +; R14/C12 interconnect drivers ; 374 / 20,720 ( 2 % ) ; +; R3 interconnects ; 3,906 / 130,992 ( 3 % ) ; +; R6 interconnects ; 6,099 / 266,960 ( 2 % ) ; +; Spine clocks ; 5 / 360 ( 1 % ) ; ; Wire stub REs ; 0 / 15,858 ( 0 % ) ; +---------------------------------------------+-------------------------+ @@ -4527,9 +4563,9 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ ; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000034 ; +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ -; Total Pass ; 204 ; 0 ; 204 ; 0 ; 0 ; 204 ; 204 ; 0 ; 204 ; 204 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 60 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Pass ; 204 ; 0 ; 204 ; 0 ; 0 ; 204 ; 204 ; 0 ; 204 ; 204 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 59 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 0 ; 204 ; 0 ; 204 ; 204 ; 0 ; 0 ; 204 ; 0 ; 0 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 144 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; +; Total Inapplicable ; 0 ; 204 ; 0 ; 204 ; 204 ; 0 ; 0 ; 204 ; 0 ; 0 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 145 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; 204 ; ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; ADC_CONVST ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; ADC_DIN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; @@ -4689,9 +4725,7 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. ; GPIO[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; -; GPIO[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; -; GPIO[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; @@ -4720,6 +4754,8 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. ; GPIO[33] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[34] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; GPIO[35] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; GPIO[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; GPIO[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; KEY[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; @@ -4782,118 +4818,118 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 55.4 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 60.1 ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Details ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; Source Register ; Destination Register ; Delay Added in ns ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.959 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.894 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.877 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.877 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; 0.865 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; 0.800 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; 0.758 ; -; riscv_core:core|imm[11] ; HEX0[0] ; 0.685 ; -; riscv_core:core|rs2[0]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFQuotient[30] ; 0.620 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.578 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.557 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.544 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.540 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[73] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a11~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.494 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[28] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a9~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.494 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.474 ; -; riscv_core:core|rs1[12]~_Duplicate_6 ; HEX0[0] ; 0.465 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.456 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.447 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.447 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.447 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.447 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.438 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|dstvalue[12] ; 0.401 ; -; riscv_core:core|instr[20] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a15~porta_address_reg0 ; 0.400 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.399 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|dstvalue[12] ; 0.398 ; -; riscv_core:core|instr[22] ; riscv_core:core|imm[2] ; 0.383 ; -; riscv_core:core|divclk[0] ; riscv_core:core|divclk[2] ; 0.382 ; -; riscv_core:core|divclk[1] ; riscv_core:core|divclk[2] ; 0.381 ; -; riscv_core:core|rs2[12]~_Duplicate_6 ; riscv_core:core|writedata[28] ; 0.381 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.379 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.379 ; -; riscv_core:core|imm[5] ; HEX0[0] ; 0.376 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|dstvalue[12] ; 0.370 ; -; riscv_core:core|state.0111 ; riscv_core:core|dstvalue[6] ; 0.362 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.360 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.359 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.350 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.349 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.347 ; -; riscv_core:core|rs2[20]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[20] ; 0.341 ; -; riscv_core:core|dstvalue[15] ; riscv_core:core|dstvalue[15] ; 0.338 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.335 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.335 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.334 ; -; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[177] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a11~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.333 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.333 ; -; riscv_core:core|imm[4] ; HEX0[0] ; 0.333 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.330 ; -; riscv_core:core|dstvalue[7] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.317 ; -; riscv_core:core|state.0110 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.317 ; -; riscv_core:core|state.0000 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.317 ; -; riscv_core:core|state.0001 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.317 ; -; riscv_core:core|dstvalue[12] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a12~porta_datain_reg0 ; 0.316 ; -; riscv_core:core|dstvalue[10] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a10~porta_datain_reg0 ; 0.316 ; -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 0.316 ; -; riscv_core:core|dstvalue[8] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a8~porta_datain_reg0 ; 0.315 ; -; riscv_core:core|instr[9] ; riscv_core:core|dstreg[2] ; 0.314 ; -; riscv_core:core|pc[1] ; riscv_core:core|ldaddr[1] ; 0.314 ; -; riscv_core:core|dstvalue[2] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.314 ; -; riscv_core:core|dstvalue[5] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a5~porta_datain_reg0 ; 0.314 ; -; riscv_core:core|rs1[30]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[1] ; 0.313 ; -; riscv_core:core|rs2[23]~_Duplicate_6 ; riscv_core:core|writedata[31] ; 0.313 ; -; riscv_core:core|imm[6] ; HEX0[0] ; 0.310 ; -; riscv_core:core|dstvalue[3] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a3~porta_datain_reg0 ; 0.309 ; -; riscv_core:core|dstvalue[6] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_datain_reg0 ; 0.308 ; -; riscv_core:core|dstvalue[11] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a11~porta_datain_reg0 ; 0.308 ; -; riscv_core:core|dstvalue[9] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a9~porta_datain_reg0 ; 0.307 ; -; riscv_core:core|instr[31] ; riscv_core:core|imm[31] ; 0.306 ; -; riscv_core:core|dstvalue[4] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a4~porta_datain_reg0 ; 0.306 ; -; riscv_core:core|imm[7] ; HEX0[0] ; 0.301 ; -; riscv_core:core|imm[9] ; HEX0[0] ; 0.301 ; -; riscv_core:core|imm[8] ; HEX0[0] ; 0.299 ; -; riscv_core:core|imm[3] ; HEX0[0] ; 0.297 ; -; riscv_core:core|pc[0] ; riscv_core:core|ldaddr[0] ; 0.296 ; -; riscv_core:core|state.0011 ; riscv_core:core|dstvalue[6] ; 0.294 ; -; riscv_core:core|state.0101 ; riscv_core:core|dstvalue[6] ; 0.294 ; -; riscv_core:core|instr[6] ; riscv_core:core|imm[5] ; 0.292 ; -; riscv_core:core|state.0100 ; riscv_core:core|dstvalue[6] ; 0.288 ; -; riscv_core:core|pc[2] ; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a0~porta_address_reg0 ; 0.284 ; -; riscv_core:core|instr[24] ; riscv_core:core|imm[4] ; 0.281 ; -; riscv_core:core|rs1[27]~_Duplicate_6 ; HEX0[0] ; 0.278 ; -; riscv_core:core|imm[2] ; HEX0[0] ; 0.269 ; -; riscv_core:core|divclk[2] ; riscv_core:core|dstvalue[1] ; 0.261 ; -; riscv_core:core|dstvalue[0] ; riscv_core:core|dstvalue[0] ; 0.256 ; -; riscv_core:core|divclk[4] ; riscv_core:core|dstvalue[1] ; 0.249 ; -; readaddr[14] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[27] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[22] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[21] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[20] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[18] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[17] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[16] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[15] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[19] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[24] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[23] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -; readaddr[25] ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.243 ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.864 ; +; riscv_core:core|divclk[3] ; riscv_core:core|dstvalue[31] ; 0.811 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.808 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.784 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.784 ; +; riscv_core:core|divclk[2] ; riscv_core:core|dstvalue[31] ; 0.763 ; +; riscv_core:core|divclk[1] ; riscv_core:core|dstvalue[31] ; 0.735 ; +; riscv_core:core|divclk[0] ; riscv_core:core|dstvalue[31] ; 0.719 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.708 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.674 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.629 ; +; riscv_core:core|divclk[4] ; riscv_core:core|dstvalue[31] ; 0.597 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.586 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.571 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.537 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.504 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.504 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.444 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.444 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.444 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.431 ; +; riscv_core:core|dstvalue[31] ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|instr[13] ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|state.1000 ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|state.1010 ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|instr[12] ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|instr[14] ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|state.0111 ; riscv_core:core|dstvalue[31] ; 0.416 ; +; riscv_core:core|state.0001 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_address_reg0 ; 0.409 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ; +; riscv_core:core|rs1[13]~_Duplicate_6 ; riscv_core:core|dstvalue[14] ; 0.397 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.390 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.369 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.366 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.364 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.363 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.363 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[3] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.352 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.351 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.349 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.349 ; +; riscv_core:core|dstvalue[15] ; riscv_core:core|dstvalue[15] ; 0.347 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.340 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.340 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.338 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.337 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.337 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0.335 ; +; riscv_core:core|rs2[11]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[11] ; 0.335 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.334 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.334 ; +; riscv_core:core|rs2[0]~_Duplicate_6 ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[30] ; 0.331 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0.331 ; +; riscv_core:core|rs1[14]~_Duplicate_6 ; riscv_core:core|dstvalue[14] ; 0.329 ; +; riscv_core:core|dstvalue[7] ; riscv_core:core|dstvalue[7] ; 0.327 ; +; riscv_core:core|instr[7] ; riscv_core:core|dstreg[0] ; 0.324 ; +; riscv_core:core|pc[2] ; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a0~porta_address_reg0 ; 0.320 ; +; riscv_core:core|pc[0] ; riscv_core:core|ldaddr[0] ; 0.318 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 0.315 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[2] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.314 ; +; riscv_core:core|state.0011 ; riscv_core:core|dstvalue[31] ; 0.313 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; 0.312 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; 0.312 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; 0.312 ; +; riscv_core:core|pc[1] ; riscv_core:core|ldaddr[1] ; 0.311 ; +; riscv_core:core|state.0100 ; riscv_core:core|dstvalue[31] ; 0.299 ; +; riscv_core:core|state.0101 ; riscv_core:core|dstvalue[31] ; 0.299 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; 0.298 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; 0.298 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; 0.298 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0.298 ; +; riscv_core:core|readreg[1] ; riscv_core:core|dstreg[1] ; 0.298 ; +; riscv_core:core|readreg[3] ; riscv_core:core|dstreg[3] ; 0.298 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxrx_in_processxx3 ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; 0.295 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 0.295 ; +; riscv_core:core|readreg[2] ; riscv_core:core|dstreg[2] ; 0.283 ; +; riscv_core:core|readreg[0] ; riscv_core:core|dstreg[0] ; 0.283 ; +; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a9~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.282 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.274 ; +; riscv_core:core|rs1[15]~_Duplicate_6 ; HEX0[0] ; 0.256 ; +; SW[1] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a1~porta_datain_reg0 ; riscv_core:core|dstvalue[1] ; 0.249 ; +; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a1~porta_we_reg ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[24] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[14] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[18] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[20] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[17] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[21] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[22] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[16] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[23] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[25] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[26] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[27] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[15] ; riscv_core:core|dstvalue[1] ; 0.249 ; +; readaddr[19] ; riscv_core:core|dstvalue[1] ; 0.249 ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ Note: This table only shows the top 100 path(s) that have the largest delay added for hold. @@ -4912,9 +4948,12 @@ Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSE Info (184020): Starting Fitter periphery placement operations Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSEMA5 with package FBGA and pin count 896 Info (11191): Automatically promoted 1 clock (1 global) - Info (11162): clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 1878 fanout uses global clock CLKCTRL_G0 + Info (11162): clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 1906 fanout uses global clock CLKCTRL_G0 Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSEMA5 with package FBGA and pin count 896 Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332104): Reading SDC File: 'de1_riscv.SDC' Warning (332049): Ignored create_clock at de1_riscv.sdc(20): Time value "1.536 MH" is not valid Info (332050): create_clock -period "1.536 MH" -name clk_audbck [get_ports AUD_BCLK] @@ -4975,17 +5014,17 @@ Warning (170052): Fitter has implemented the following 103 RAMs using MLAB locat Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report. Info (170056): Fitter has implemented the following 103 RAMs using MLAB locations, which will have the same paused read capabilities as dedicated RAM locations Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:05 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:06 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:13 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:14 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 2% of the available device resources - Info (170196): Router estimated peak interconnect usage is 28% of the available device resources in the region that extends from location X33_Y23 to location X44_Y34 + Info (170196): Router estimated peak interconnect usage is 28% of the available device resources in the region that extends from location X33_Y11 to location X44_Y22 Info (170194): Fitter routing operations ending: elapsed time is 00:00:16 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 9.48 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 10.22 seconds. Info (334003): Started post-fitting delay annotation Warning (334000): Timing characteristics of device 5CSEMA5F31C6 are preliminary Info (334004): Delay annotation completed successfully @@ -5023,9 +5062,7 @@ Warning (169064): Following 60 pins have no output enable or a GND or VCC output Info (169065): Pin GPIO[2] has a permanently disabled output enable Info (169065): Pin GPIO[3] has a permanently disabled output enable Info (169065): Pin GPIO[4] has a permanently disabled output enable - Info (169065): Pin GPIO[5] has a permanently disabled output enable Info (169065): Pin GPIO[6] has a permanently disabled output enable - Info (169065): Pin GPIO[7] has a permanently disabled output enable Info (169065): Pin GPIO[8] has a permanently disabled output enable Info (169065): Pin GPIO[9] has a permanently disabled output enable Info (169065): Pin GPIO[10] has a permanently disabled output enable @@ -5054,12 +5091,14 @@ Warning (169064): Following 60 pins have no output enable or a GND or VCC output Info (169065): Pin GPIO[33] has a permanently disabled output enable Info (169065): Pin GPIO[34] has a permanently disabled output enable Info (169065): Pin GPIO[35] has a permanently disabled output enable + Info (169065): Pin GPIO[5] has a permanently enabled output enable + Info (169065): Pin GPIO[7] has a permanently disabled output enable Info (144001): Generated suppressed messages file D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.fit.smsg Info: Quartus II 64-Bit Fitter was successful. 0 errors, 29 warnings - Info: Peak virtual memory: 2325 megabytes - Info: Processing ended: Fri Aug 27 17:23:11 2021 - Info: Elapsed time: 00:01:56 - Info: Total CPU time (on all processors): 00:02:33 + Info: Peak virtual memory: 2323 megabytes + Info: Processing ended: Sat Aug 28 10:55:54 2021 + Info: Elapsed time: 00:01:57 + Info: Total CPU time (on all processors): 00:02:34 +----------------------------+ diff --git a/examples/hdl4se_riscv/de1/de1_riscv.fit.summary b/examples/hdl4se_riscv/de1/de1_riscv.fit.summary index 3fc28c729a5b0518cc402a83d157ec11b837905f..45b60eee8d0d0e5c34d9da1dcb1ef0be17fd6038 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.fit.summary +++ b/examples/hdl4se_riscv/de1/de1_riscv.fit.summary @@ -1,12 +1,12 @@ -Fitter Status : Successful - Fri Aug 27 17:23:08 2021 +Fitter Status : Successful - Sat Aug 28 10:55:51 2021 Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version Revision Name : de1_riscv Top-level Entity Name : de1_riscv Family : Cyclone V Device : 5CSEMA5F31C6 Timing Models : Preliminary -Logic utilization (in ALMs) : 2,468 / 32,070 ( 8 % ) -Total registers : 1833 +Logic utilization (in ALMs) : 2,494 / 32,070 ( 8 % ) +Total registers : 1863 Total pins : 204 / 457 ( 45 % ) Total virtual pins : 0 Total block memory bits : 66,560 / 4,065,280 ( 2 % ) diff --git a/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt b/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt index 0e81bb7c7391d03fd36aa6052bf2d4da23a26019..7ab1e81ebf4840ee9e697f997766a7582145f170 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt @@ -1,5 +1,5 @@ Flow report for de1_riscv -Fri Aug 27 17:24:01 2021 +Sat Aug 28 11:02:31 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -40,25 +40,25 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+---------------------------------------------+ -; Flow Status ; Successful - Fri Aug 27 17:23:28 2021 ; +; Flow Status ; Successful - Sat Aug 28 11:02:31 2021 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; ; Device ; 5CSEMA5F31C6 ; ; Timing Models ; Preliminary ; -; Logic utilization (in ALMs) ; 2,468 / 32,070 ( 8 % ) ; -; Total registers ; 1833 ; -; Total pins ; 204 / 457 ( 45 % ) ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 1636 ; +; Total pins ; 204 ; ; Total virtual pins ; 0 ; -; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ; -; Total DSP Blocks ; 10 / 87 ( 11 % ) ; +; Total block memory bits ; 67,296 ; +; Total DSP Blocks ; 10 ; ; Total HSSI RX PCSs ; 0 ; ; Total HSSI PMA RX Deserializers ; 0 ; ; Total HSSI TX PCSs ; 0 ; ; Total HSSI TX Channels ; 0 ; -; Total PLLs ; 1 / 6 ( 17 % ) ; -; Total DLLs ; 0 / 4 ( 0 % ) ; +; Total PLLs ; 1 ; +; Total DLLs ; 0 ; +---------------------------------+---------------------------------------------+ @@ -67,7 +67,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/27/2021 17:20:52 ; +; Start date & time ; 08/28/2021 11:02:08 ; ; Main task ; Compilation ; ; Revision Name ; de1_riscv ; +-------------------+---------------------+ @@ -78,7 +78,7 @@ applicable agreement for further details. +-------------------------------------+---------------------------------------+---------------+--------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+---------------------------------------+---------------+--------------+------------+ -; COMPILER_SIGNATURE_ID ; 621136229624.163005605235460 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 621136229624.163011972824564 ; -- ; -- ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ; ; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ; @@ -129,38 +129,29 @@ applicable agreement for further details. +-------------------------------------+---------------------------------------+---------------+--------------+------------+ -+-------------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 670 MB ; 00:00:20 ; -; Fitter ; 00:01:53 ; 1.4 ; 2325 MB ; 00:02:30 ; -; Assembler ; 00:00:15 ; 1.0 ; 661 MB ; 00:00:15 ; -; TimeQuest Timing Analyzer ; 00:00:32 ; 1.3 ; 1135 MB ; 00:00:41 ; -; Total ; 00:03:01 ; -- ; -- ; 00:03:46 ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:22 ; 1.0 ; 670 MB ; 00:00:21 ; +; Total ; 00:00:22 ; -- ; -- ; 00:00:21 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ -+----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; -; Fitter ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; -; Assembler ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; -; TimeQuest Timing Analyzer ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; -+---------------------------+------------------+-----------+------------+----------------+ ++-----------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ; ++----------------------+------------------+-----------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv -quartus_fit --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv -quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv -quartus_sta de1_riscv -c de1_riscv diff --git a/examples/hdl4se_riscv/de1/de1_riscv.jdi b/examples/hdl4se_riscv/de1/de1_riscv.jdi index 0dd59e763e2be243c79ef301a014caf264007797..b91d50455a910c65261f24d08c0cc7e2568f5c6a 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.jdi +++ b/examples/hdl4se_riscv/de1/de1_riscv.jdi @@ -1,6 +1,6 @@ - + diff --git a/examples/hdl4se_riscv/de1/de1_riscv.map.rpt b/examples/hdl4se_riscv/de1/de1_riscv.map.rpt index 813b3b0d50fc50812e85b441282153b82480340a..c58c87201377f315e453f61d73b150f4785731f8 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.map.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for de1_riscv -Fri Aug 27 17:21:13 2021 +Sat Aug 28 11:02:31 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -17,54 +17,60 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version 9. Analysis & Synthesis DSP Block Usage Summary 10. Analysis & Synthesis IP Cores Summary 11. State Machine - |de1_riscv|riscv_core:core|state - 12. Registers Removed During Synthesis - 13. General Register Statistics - 14. Inverted Register Statistics - 15. Registers Packed Into Inferred Megafunctions - 16. Multiplexer Restructuring Statistics (Restructuring Performed) - 17. Source assignments for regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated - 18. Source assignments for ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated - 19. Source assignments for riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider - 20. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider - 21. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 - 22. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 - 23. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 - 24. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 - 25. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 - 26. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 - 27. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 - 28. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 - 29. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 - 30. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 - 31. Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i - 32. Parameter Settings for User Entity Instance: regfile:regs|altsyncram:altsyncram_component - 33. Parameter Settings for User Entity Instance: ram8kb:ram|altsyncram:altsyncram_component - 34. Parameter Settings for User Entity Instance: riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component - 35. Parameter Settings for User Entity Instance: riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component - 36. Parameter Settings for User Entity Instance: riscv_core:core|mult:mul|lpm_mult:lpm_mult_component - 37. Parameter Settings for User Entity Instance: riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component - 38. Parameter Settings for User Entity Instance: riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component - 39. Parameter Settings for User Entity Instance: riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component - 40. Parameter Settings for User Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component - 41. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 - 42. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 - 43. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 - 44. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 - 45. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 - 46. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 - 47. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 - 48. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 - 49. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 - 50. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 - 51. altsyncram Parameter Settings by Entity Instance - 52. lpm_mult Parameter Settings by Entity Instance - 53. altshift_taps Parameter Settings by Entity Instance - 54. Port Connectivity Checks: "riscv_core:core|mulsu:mul_su" - 55. Port Connectivity Checks: "riscv_core:core|mult:mul" - 56. Port Connectivity Checks: "riscv_core:core" - 57. Port Connectivity Checks: "clk100M:clk100" - 58. Elapsed Time Per Partition - 59. Analysis & Synthesis Messages + 12. Registers Protected by Synthesis + 13. Registers Removed During Synthesis + 14. Removed Registers Triggering Further Register Optimizations + 15. General Register Statistics + 16. Inverted Register Statistics + 17. Registers Packed Into Inferred Megafunctions + 18. Multiplexer Restructuring Statistics (Restructuring Performed) + 19. Source assignments for altera_uart:uart + 20. Source assignments for altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer + 21. Source assignments for regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated + 22. Source assignments for ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated + 23. Source assignments for riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider + 24. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider + 25. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 + 26. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 + 27. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 + 28. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 + 29. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 + 30. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 + 31. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 + 32. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 + 33. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 + 34. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 + 35. Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i + 36. Parameter Settings for User Entity Instance: altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer + 37. Parameter Settings for User Entity Instance: regfile:regs|altsyncram:altsyncram_component + 38. Parameter Settings for User Entity Instance: ram8kb:ram|altsyncram:altsyncram_component + 39. Parameter Settings for User Entity Instance: riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component + 40. Parameter Settings for User Entity Instance: riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component + 41. Parameter Settings for User Entity Instance: riscv_core:core|mult:mul|lpm_mult:lpm_mult_component + 42. Parameter Settings for User Entity Instance: riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component + 43. Parameter Settings for User Entity Instance: riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component + 44. Parameter Settings for User Entity Instance: riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component + 45. Parameter Settings for User Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component + 46. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 + 47. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 + 48. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 + 49. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 + 50. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 + 51. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 + 52. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 + 53. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 + 54. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 + 55. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 + 56. altsyncram Parameter Settings by Entity Instance + 57. lpm_mult Parameter Settings by Entity Instance + 58. altshift_taps Parameter Settings by Entity Instance + 59. Port Connectivity Checks: "riscv_core:core|mulsu:mul_su" + 60. Port Connectivity Checks: "riscv_core:core|mult:mul" + 61. Port Connectivity Checks: "riscv_core:core" + 62. Port Connectivity Checks: "altera_uart:uart" + 63. Port Connectivity Checks: "clk100M:clk100" + 64. Elapsed Time Per Partition + 65. Analysis & Synthesis Messages @@ -90,13 +96,13 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Aug 27 17:21:13 2021 ; +; Analysis & Synthesis Status ; Successful - Sat Aug 28 11:02:31 2021 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; de1_riscv ; ; Top-level Entity Name ; de1_riscv ; ; Family ; Cyclone V ; ; Logic utilization (in ALMs) ; N/A ; -; Total registers ; 1608 ; +; Total registers ; 1636 ; ; Total pins ; 204 ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 67,296 ; @@ -215,97 +221,99 @@ applicable agreement for further details. +----------------------------+-------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+ -; ../verilog/riscv_core.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core.v ; ; -; ram/ram8kb.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram8kb.v ; ; -; regfile/regfile.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v ; ; -; alu/mult.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v ; ; -; alu/mult_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v ; ; -; alu/div.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v ; ; -; alu/div_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v ; ; -; alu/adder.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v ; ; -; alu/suber.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v ; ; -; alu/mulsu.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v ; ; -; clk/clk100M.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v ; clk100M ; -; clk/clk100M/clk100M_0002.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v ; clk100M ; -; de1_riscv.v ; yes ; Auto-Found Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v ; ; -; altera_pll.v ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altera_pll.v ; ; -; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf ; ; -; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; -; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; -; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc ; ; -; aglobal131.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ; -; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; -; altrom.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altrom.inc ; ; -; altram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altram.inc ; ; -; altdpram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc ; ; -; db/altsyncram_nco1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_nco1.tdf ; ; -; db/altsyncram_bdq1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_bdq1.tdf ; ; -; test.mif ; yes ; Auto-Found Memory Initialization File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/test.mif ; ; -; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; -; addcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/addcore.inc ; ; -; look_add.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/look_add.inc ; ; -; bypassff.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/bypassff.inc ; ; -; altshift.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift.inc ; ; -; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; -; db/add_sub_tih.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_tih.tdf ; ; -; db/add_sub_ujh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_ujh.tdf ; ; -; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; -; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; -; multcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/multcore.inc ; ; -; db/mult_b8n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_b8n.v ; ; -; db/mult_81n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_81n.v ; ; -; db/mult_61n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_61n.v ; ; -; lpm_divide.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_divide.tdf ; ; -; abs_divider.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/abs_divider.inc ; ; -; sign_div_unsign.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/sign_div_unsign.inc ; ; -; db/lpm_divide_2jt.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_2jt.tdf ; ; -; db/sign_div_unsign_8ai.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_8ai.tdf ; ; -; db/alt_u_div_nlf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_nlf.tdf ; ; -; db/lpm_divide_s4t.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_s4t.tdf ; ; -; db/sign_div_unsign_2sh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_2sh.tdf ; ; -; db/alt_u_div_5eg.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_5eg.tdf ; ; -; altshift_taps.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf ; ; -; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc ; ; -; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc ; ; -; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc ; ; -; db/shift_taps_7l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_7l21.tdf ; ; -; db/altsyncram_kr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_kr91.tdf ; ; -; db/cntr_8jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_8jf.tdf ; ; -; db/cmpr_c9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_c9c.tdf ; ; -; db/shift_taps_hm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_hm21.tdf ; ; -; db/altsyncram_9u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9u91.tdf ; ; -; db/cntr_9jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_9jf.tdf ; ; -; db/shift_taps_gm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_gm21.tdf ; ; -; db/altsyncram_7u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_7u91.tdf ; ; -; db/shift_taps_bl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_bl21.tdf ; ; -; db/altsyncram_rr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_rr91.tdf ; ; -; db/cntr_0if.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_0if.tdf ; ; -; db/shift_taps_9l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_9l21.tdf ; ; -; db/altsyncram_lr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_lr91.tdf ; ; -; db/cntr_uhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_uhf.tdf ; ; -; db/shift_taps_cl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_cl21.tdf ; ; -; db/altsyncram_hr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_hr91.tdf ; ; -; db/cntr_thf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_thf.tdf ; ; -; db/cmpr_b9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_b9c.tdf ; ; -; db/shift_taps_dl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_dl21.tdf ; ; -; db/altsyncram_mr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_mr91.tdf ; ; -; db/cntr_shf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_shf.tdf ; ; -; db/shift_taps_4l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_4l21.tdf ; ; -; db/altsyncram_dr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_dr91.tdf ; ; -; db/cntr_rhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_rhf.tdf ; ; -; db/shift_taps_3l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_3l21.tdf ; ; -; db/altsyncram_9r91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9r91.tdf ; ; -; db/cntr_phf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_phf.tdf ; ; -; db/shift_taps_5l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_5l21.tdf ; ; -; db/altsyncram_br91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_br91.tdf ; ; -; db/cntr_ohf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_ohf.tdf ; ; -; db/cmpr_a9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_a9c.tdf ; ; -+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ +; de1_riscv_v2.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv_v2.v ; ; +; ../verilog/riscv_core.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core.v ; ; +; uart/altera_uart.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/uart/altera_uart.v ; ; +; ram/ram8kb.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram8kb.v ; ; +; regfile/regfile.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v ; ; +; alu/mult.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v ; ; +; alu/mult_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v ; ; +; alu/div.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v ; ; +; alu/div_s.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v ; ; +; alu/adder.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v ; ; +; alu/suber.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v ; ; +; alu/mulsu.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v ; ; +; clk/clk100M.v ; yes ; User Wizard-Generated File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M.v ; clk100M ; +; clk/clk100M/clk100M_0002.v ; yes ; User Verilog HDL File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v ; clk100M ; +; altera_pll.v ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altera_pll.v ; ; +; altera_std_synchronizer.v ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altera_std_synchronizer.v ; ; +; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf ; ; +; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; +; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; +; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc ; ; +; aglobal131.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ; +; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; +; altrom.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altrom.inc ; ; +; altram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altram.inc ; ; +; altdpram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc ; ; +; db/altsyncram_nco1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_nco1.tdf ; ; +; db/altsyncram_bdq1.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_bdq1.tdf ; ; +; test.mif ; yes ; Auto-Found Memory Initialization File ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/test.mif ; ; +; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; +; addcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/addcore.inc ; ; +; look_add.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/look_add.inc ; ; +; bypassff.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/bypassff.inc ; ; +; altshift.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift.inc ; ; +; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; +; db/add_sub_tih.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_tih.tdf ; ; +; db/add_sub_ujh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/add_sub_ujh.tdf ; ; +; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; +; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; +; multcore.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/multcore.inc ; ; +; db/mult_b8n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_b8n.v ; ; +; db/mult_81n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_81n.v ; ; +; db/mult_61n.v ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/mult_61n.v ; ; +; lpm_divide.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_divide.tdf ; ; +; abs_divider.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/abs_divider.inc ; ; +; sign_div_unsign.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/sign_div_unsign.inc ; ; +; db/lpm_divide_2jt.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_2jt.tdf ; ; +; db/sign_div_unsign_8ai.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_8ai.tdf ; ; +; db/alt_u_div_nlf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_nlf.tdf ; ; +; db/lpm_divide_s4t.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/lpm_divide_s4t.tdf ; ; +; db/sign_div_unsign_2sh.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/sign_div_unsign_2sh.tdf ; ; +; db/alt_u_div_5eg.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/alt_u_div_5eg.tdf ; ; +; altshift_taps.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf ; ; +; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc ; ; +; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc ; ; +; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc ; ; +; db/shift_taps_7l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_7l21.tdf ; ; +; db/altsyncram_kr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_kr91.tdf ; ; +; db/cntr_8jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_8jf.tdf ; ; +; db/cmpr_c9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_c9c.tdf ; ; +; db/shift_taps_hm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_hm21.tdf ; ; +; db/altsyncram_9u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9u91.tdf ; ; +; db/cntr_9jf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_9jf.tdf ; ; +; db/shift_taps_gm21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_gm21.tdf ; ; +; db/altsyncram_7u91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_7u91.tdf ; ; +; db/shift_taps_bl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_bl21.tdf ; ; +; db/altsyncram_rr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_rr91.tdf ; ; +; db/cntr_0if.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_0if.tdf ; ; +; db/shift_taps_9l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_9l21.tdf ; ; +; db/altsyncram_lr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_lr91.tdf ; ; +; db/cntr_uhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_uhf.tdf ; ; +; db/shift_taps_cl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_cl21.tdf ; ; +; db/altsyncram_hr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_hr91.tdf ; ; +; db/cntr_thf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_thf.tdf ; ; +; db/cmpr_b9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_b9c.tdf ; ; +; db/shift_taps_dl21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_dl21.tdf ; ; +; db/altsyncram_mr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_mr91.tdf ; ; +; db/cntr_shf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_shf.tdf ; ; +; db/shift_taps_4l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_4l21.tdf ; ; +; db/altsyncram_dr91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_dr91.tdf ; ; +; db/cntr_rhf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_rhf.tdf ; ; +; db/shift_taps_3l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_3l21.tdf ; ; +; db/altsyncram_9r91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_9r91.tdf ; ; +; db/cntr_phf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_phf.tdf ; ; +; db/shift_taps_5l21.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/shift_taps_5l21.tdf ; ; +; db/altsyncram_br91.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/altsyncram_br91.tdf ; ; +; db/cntr_ohf.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cntr_ohf.tdf ; ; +; db/cmpr_a9c.tdf ; yes ; Auto-Generated Megafunction ; D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/db/cmpr_a9c.tdf ; ; ++----------------------------------+-----------------+----------------------------------------+--------------------------------------------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------+ @@ -313,16 +321,16 @@ applicable agreement for further details. +---------------------------------------------+---------------------------------------------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+---------------------------------------------------------------------------------+ -; Estimate of Logic utilization (ALMs needed) ; 2157 ; +; Estimate of Logic utilization (ALMs needed) ; 2177 ; ; ; ; -; Combinational ALUT usage for logic ; 3706 ; +; Combinational ALUT usage for logic ; 3750 ; ; -- 7 input functions ; 47 ; -; -- 6 input functions ; 335 ; -; -- 5 input functions ; 468 ; -; -- 4 input functions ; 822 ; -; -- <=3 input functions ; 2034 ; +; -- 6 input functions ; 327 ; +; -- 5 input functions ; 472 ; +; -- 4 input functions ; 831 ; +; -- <=3 input functions ; 2073 ; ; ; ; -; Dedicated logic registers ; 1608 ; +; Dedicated logic registers ; 1636 ; ; ; ; ; I/O pins ; 204 ; ; Total MLAB memory bits ; 0 ; @@ -332,91 +340,95 @@ applicable agreement for further details. ; -- PLLs ; 1 ; ; ; ; ; Maximum fan-out node ; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; -; Maximum fan-out ; 1776 ; -; Total fan-out ; 20815 ; -; Average fan-out ; 3.49 ; +; Maximum fan-out ; 1804 ; +; Total fan-out ; 21004 ; +; Average fan-out ; 3.48 ; +---------------------------------------------+---------------------------------------------------------------------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; |de1_riscv ; 3706 (79) ; 1608 (66) ; 67296 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; -; |clk100M:clk100| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; -; |clk100M_0002:clk100m_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; -; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; -; |ram8kb:ram| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram ; work ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component ; work ; -; |altsyncram_bdq1:auto_generated| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated ; work ; -; |regfile:regs| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; -; |altsyncram_nco1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; -; |riscv_core:core| ; 3627 (1184) ; 1542 (287) ; 736 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; -; |adder:add| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; -; |lpm_add_sub:LPM_ADD_SUB_component| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; -; |add_sub_tih:auto_generated| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; -; |div:div| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; -; |lpm_divide:LPM_DIVIDE_component| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; -; |lpm_divide_2jt:auto_generated| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; -; |sign_div_unsign_8ai:divider| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; -; |alt_u_div_nlf:divider| ; 1002 (1002) ; 583 (583) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; -; |div_s:divs| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; -; |lpm_divide:LPM_DIVIDE_component| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; -; |lpm_divide_s4t:auto_generated| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; -; |sign_div_unsign_2sh:divider| ; 1278 (175) ; 672 (14) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; -; |alt_u_div_5eg:divider| ; 1090 (987) ; 650 (594) ; 666 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; -; |altshift_taps:DFFNumerator_rtl_0| ; 14 (0) ; 8 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; -; |shift_taps_hm21:auto_generated| ; 14 (8) ; 8 (4) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; -; |altsyncram_9u91:altsyncram5| ; 0 (0) ; 0 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; -; |cntr_9jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_1| ; 13 (0) ; 8 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; -; |shift_taps_gm21:auto_generated| ; 13 (7) ; 8 (4) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; -; |altsyncram_7u91:altsyncram5| ; 0 (0) ; 0 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; -; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_2| ; 14 (0) ; 8 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; -; |shift_taps_bl21:auto_generated| ; 14 (8) ; 8 (4) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; -; |altsyncram_rr91:altsyncram5| ; 0 (0) ; 0 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; -; |cntr_0if:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_3| ; 8 (0) ; 6 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; -; |shift_taps_9l21:auto_generated| ; 8 (5) ; 6 (3) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; -; |altsyncram_lr91:altsyncram4| ; 0 (0) ; 0 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; -; |cntr_uhf:cntr1| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_4| ; 14 (0) ; 6 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; -; |shift_taps_cl21:auto_generated| ; 14 (7) ; 6 (3) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; -; |altsyncram_hr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; -; |cntr_thf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_5| ; 13 (0) ; 6 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; -; |shift_taps_dl21:auto_generated| ; 13 (6) ; 6 (3) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; -; |altsyncram_mr91:altsyncram5| ; 0 (0) ; 0 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; -; |cntr_shf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_6| ; 14 (0) ; 6 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; -; |shift_taps_4l21:auto_generated| ; 14 (7) ; 6 (3) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; -; |altsyncram_dr91:altsyncram5| ; 0 (0) ; 0 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; -; |cntr_rhf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_7| ; 6 (0) ; 4 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; -; |shift_taps_3l21:auto_generated| ; 6 (4) ; 4 (2) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; -; |altsyncram_9r91:altsyncram4| ; 0 (0) ; 0 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; -; |cntr_phf:cntr1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; -; |altshift_taps:DFFNumerator_rtl_8| ; 7 (0) ; 4 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; -; |shift_taps_5l21:auto_generated| ; 7 (2) ; 4 (2) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; -; |altsyncram_br91:altsyncram4| ; 0 (0) ; 0 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; -; |cntr_ohf:cntr1| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; -; |altshift_taps:DFF_Num_Sign_rtl_0| ; 13 (0) ; 8 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; -; |shift_taps_7l21:auto_generated| ; 13 (7) ; 8 (4) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; -; |altsyncram_kr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; -; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; -; |mulsu:mul_su| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; -; |lpm_mult:lpm_mult_component| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; -; |mult_61n:auto_generated| ; 38 (38) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; -; |mult:mul| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; -; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; -; |mult_b8n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; -; |mult_s:mul_s| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; -; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; -; |mult_81n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; -+----------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |de1_riscv ; 3750 (83) ; 1636 (66) ; 67296 ; 10 ; 204 ; 0 ; |de1_riscv ; work ; +; |altera_uart:uart| ; 35 (0) ; 28 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart ; work ; +; |altera_uart_regs:the_altera_uart_regs| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ; +; |altera_uart_rx:the_altera_uart_rx| ; 35 (35) ; 26 (24) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; work ; +; |clk100M:clk100| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ; +; |clk100M_0002:clk100m_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ; +; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ; +; |ram8kb:ram| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component ; work ; +; |altsyncram_bdq1:auto_generated| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; |de1_riscv|ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated ; work ; +; |regfile:regs| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ; +; |altsyncram_nco1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ; +; |riscv_core:core| ; 3632 (1189) ; 1542 (287) ; 736 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ; +; |adder:add| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ; +; |lpm_add_sub:LPM_ADD_SUB_component| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ; +; |add_sub_tih:auto_generated| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ; +; |div:div| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ; +; |lpm_divide:LPM_DIVIDE_component| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ; +; |lpm_divide_2jt:auto_generated| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ; +; |sign_div_unsign_8ai:divider| ; 1002 (0) ; 583 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ; +; |alt_u_div_nlf:divider| ; 1002 (1002) ; 583 (583) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ; +; |div_s:divs| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ; +; |lpm_divide:LPM_DIVIDE_component| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ; +; |lpm_divide_s4t:auto_generated| ; 1278 (0) ; 672 (0) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ; +; |sign_div_unsign_2sh:divider| ; 1278 (175) ; 672 (14) ; 736 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ; +; |alt_u_div_5eg:divider| ; 1090 (987) ; 650 (594) ; 666 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ; +; |altshift_taps:DFFNumerator_rtl_0| ; 14 (0) ; 8 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ; +; |shift_taps_hm21:auto_generated| ; 14 (8) ; 8 (4) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ; +; |altsyncram_9u91:altsyncram5| ; 0 (0) ; 0 (0) ; 110 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ; +; |cntr_9jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_1| ; 13 (0) ; 8 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ; +; |shift_taps_gm21:auto_generated| ; 13 (7) ; 8 (4) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ; +; |altsyncram_7u91:altsyncram5| ; 0 (0) ; 0 (0) ; 100 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ; +; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_2| ; 14 (0) ; 8 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ; +; |shift_taps_bl21:auto_generated| ; 14 (8) ; 8 (4) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ; +; |altsyncram_rr91:altsyncram5| ; 0 (0) ; 0 (0) ; 108 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ; +; |cntr_0if:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_3| ; 8 (0) ; 6 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ; +; |shift_taps_9l21:auto_generated| ; 8 (5) ; 6 (3) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ; +; |altsyncram_lr91:altsyncram4| ; 0 (0) ; 0 (0) ; 80 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ; +; |cntr_uhf:cntr1| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_4| ; 14 (0) ; 6 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ; +; |shift_taps_cl21:auto_generated| ; 14 (7) ; 6 (3) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ; +; |altsyncram_hr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ; +; |cntr_thf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_5| ; 13 (0) ; 6 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ; +; |shift_taps_dl21:auto_generated| ; 13 (6) ; 6 (3) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ; +; |altsyncram_mr91:altsyncram5| ; 0 (0) ; 0 (0) ; 72 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ; +; |cntr_shf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_6| ; 14 (0) ; 6 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ; +; |shift_taps_4l21:auto_generated| ; 14 (7) ; 6 (3) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ; +; |altsyncram_dr91:altsyncram5| ; 0 (0) ; 0 (0) ; 50 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ; +; |cntr_rhf:cntr1| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_7| ; 6 (0) ; 4 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ; +; |shift_taps_3l21:auto_generated| ; 6 (4) ; 4 (2) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ; +; |altsyncram_9r91:altsyncram4| ; 0 (0) ; 0 (0) ; 40 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ; +; |cntr_phf:cntr1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ; +; |altshift_taps:DFFNumerator_rtl_8| ; 7 (0) ; 4 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ; +; |shift_taps_5l21:auto_generated| ; 7 (2) ; 4 (2) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ; +; |altsyncram_br91:altsyncram4| ; 0 (0) ; 0 (0) ; 36 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ; +; |cntr_ohf:cntr1| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ; +; |altshift_taps:DFF_Num_Sign_rtl_0| ; 13 (0) ; 8 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ; +; |shift_taps_7l21:auto_generated| ; 13 (7) ; 8 (4) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ; +; |altsyncram_kr91:altsyncram5| ; 0 (0) ; 0 (0) ; 70 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ; +; |cntr_8jf:cntr1| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ; +; |mulsu:mul_su| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ; +; |lpm_mult:lpm_mult_component| ; 38 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ; +; |mult_61n:auto_generated| ; 38 (38) ; 0 (0) ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ; +; |mult:mul| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ; +; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ; +; |mult_b8n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ; +; |mult_s:mul_s| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ; +; |lpm_mult:lpm_mult_component| ; 46 (0) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ; +; |mult_81n:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ; ++----------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -496,11 +508,28 @@ Encoding Type: One-Hot +------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Protected by Synthesis ; ++----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; ++----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; yes ; yes ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; yes ; yes ; ++----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ + + +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[10..15] ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[0..9] ; Stuck at GND due to stuck port clock_enable ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[9] ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|irq ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[0..7] ; Stuck at GND due to stuck port clock_enable ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; Stuck at VCC due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; Stuck at GND due to stuck port data_in ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[31] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[11] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[63] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[10] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[95] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[9] ; @@ -513,6 +542,7 @@ Encoding Type: One-Hot ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[319] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[2] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[351] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[383] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx2 ; Merged with altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[0] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[0] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[32] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[32] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[64] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[64] ; @@ -525,26 +555,104 @@ Encoding Type: One-Hot ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[288] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[320] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[352] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_overrun ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0..9] ; Stuck at GND due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd ; Stuck at VCC due to stuck port clock_enable ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; Stuck at VCC due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_clk_en ; Lost fanout ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ; Stuck at VCC due to stuck port data_in ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[0..8] ; Lost fanout ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[2..6] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[2] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[3] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[4..6] ; Lost fanout ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[0,1,7,8] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[1,7] ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ; Lost fanout ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[0] ; Lost fanout ; ; riscv_core:core|state~10 ; Lost fanout ; ; riscv_core:core|state~11 ; Lost fanout ; ; riscv_core:core|state~12 ; Lost fanout ; ; riscv_core:core|state~13 ; Lost fanout ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[1] ; Stuck at GND due to stuck port data_in ; -; Total Number of Removed Registers = 29 ; ; +; Total Number of Removed Registers = 102 ; ; +----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+ +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[7] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8], ; +; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd, ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_clk_en, ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[8], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[7], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[6], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[5], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[4], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[3], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[2], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[1], ; +; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[0] ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[8] ; Stuck at GND ; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|irq, ; +; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect, ; +; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun, ; +; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[9] ; Stuck at GND ; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[9], ; +; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[7] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[7] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[6] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[6] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[5] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[5] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[4] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[4] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[3] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[3] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[2] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[2] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[1] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[1] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[0] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[0] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[6] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[5] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[4] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[3] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[2] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[1] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[0] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] ; +; ; due to stuck port clock_enable ; ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; Stuck at VCC ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ; +; ; due to stuck port data_in ; ; +; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; +; ; due to stuck port data_in ; ; ++-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 1608 ; +; Total registers ; 1636 ; ; Number of registers using Synchronous Clear ; 95 ; ; Number of registers using Synchronous Load ; 493 ; -; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Clear ; 28 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 306 ; +; Number of registers using Clock Enable ; 316 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -554,7 +662,7 @@ Encoding Type: One-Hot +-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ ; Inverted Register ; Fan out ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 34 ; +; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 35 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; 3 ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; 4 ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[353] ; 1 ; @@ -708,47 +816,72 @@ Encoding Type: One-Hot +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ -; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de1_riscv|riscv_core:core|ldaddr[0] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[8] ; -; 5:1 ; 19 bits ; 57 LEs ; 0 LEs ; 57 LEs ; Yes ; |de1_riscv|readaddr[20] ; -; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |de1_riscv|led3[6] ; -; 6:1 ; 24 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |de1_riscv|led1[5] ; -; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[5] ; -; 14:1 ; 6 bits ; 54 LEs ; 6 LEs ; 48 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[10] ; -; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de1_riscv|led4[6] ; -; 7:1 ; 12 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |de1_riscv|led4[0] ; -; 7:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |de1_riscv|riscv_core:core|divclk[3] ; -; 15:1 ; 8 bits ; 80 LEs ; 0 LEs ; 80 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[18] ; -; 16:1 ; 4 bits ; 40 LEs ; 8 LEs ; 32 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[1] ; -; 10:1 ; 11 bits ; 66 LEs ; 0 LEs ; 66 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[29] ; -; 14:1 ; 2 bits ; 18 LEs ; 4 LEs ; 14 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[0] ; -; 14:1 ; 25 bits ; 225 LEs ; 50 LEs ; 175 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[22] ; -; 14:1 ; 4 bits ; 36 LEs ; 8 LEs ; 28 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[2] ; -; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[22] ; -; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[31] ; -; 22:1 ; 5 bits ; 70 LEs ; 25 LEs ; 45 LEs ; Yes ; |de1_riscv|riscv_core:core|dstreg[4] ; -; 60:1 ; 12 bits ; 480 LEs ; 276 LEs ; 204 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[24] ; -; 63:1 ; 7 bits ; 294 LEs ; 238 LEs ; 56 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[8] ; -; 64:1 ; 3 bits ; 126 LEs ; 102 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[28] ; -; 65:1 ; 3 bits ; 129 LEs ; 102 LEs ; 27 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[5] ; -; 69:1 ; 2 bits ; 92 LEs ; 72 LEs ; 20 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[2] ; -; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[9] ; -; 3:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[19] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ; -; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|bReadAddr[11] ; -; 5:1 ; 6 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de1_riscv|ramaddr[3] ; -; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|Selector163 ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+ +; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; +; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de1_riscv|riscv_core:core|ldaddr[1] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[14] ; +; 5:1 ; 19 bits ; 57 LEs ; 0 LEs ; 57 LEs ; Yes ; |de1_riscv|readaddr[17] ; +; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |de1_riscv|led1[6] ; +; 6:1 ; 24 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |de1_riscv|led2[3] ; +; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[1] ; +; 14:1 ; 6 bits ; 54 LEs ; 6 LEs ; 48 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[5] ; +; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de1_riscv|led4[6] ; +; 7:1 ; 12 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |de1_riscv|led4[4] ; +; 7:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |de1_riscv|riscv_core:core|divclk[1] ; +; 15:1 ; 8 bits ; 80 LEs ; 0 LEs ; 80 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[12] ; +; 16:1 ; 4 bits ; 40 LEs ; 8 LEs ; 32 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[3] ; +; 10:1 ; 11 bits ; 66 LEs ; 0 LEs ; 66 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[27] ; +; 14:1 ; 2 bits ; 18 LEs ; 4 LEs ; 14 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[0] ; +; 14:1 ; 25 bits ; 225 LEs ; 50 LEs ; 175 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[18] ; +; 14:1 ; 4 bits ; 36 LEs ; 8 LEs ; 28 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[2] ; +; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[19] ; +; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[27] ; +; 22:1 ; 5 bits ; 70 LEs ; 25 LEs ; 45 LEs ; Yes ; |de1_riscv|riscv_core:core|dstreg[0] ; +; 60:1 ; 12 bits ; 480 LEs ; 276 LEs ; 204 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[25] ; +; 63:1 ; 7 bits ; 294 LEs ; 238 LEs ; 56 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[8] ; +; 64:1 ; 3 bits ; 126 LEs ; 102 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[30] ; +; 65:1 ; 3 bits ; 129 LEs ; 102 LEs ; 27 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[6] ; +; 69:1 ; 2 bits ; 92 LEs ; 72 LEs ; 20 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[3] ; +; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[9] ; +; 3:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[23] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft1 ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|bReadAddr[8] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[2] ; +; 5:1 ; 6 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de1_riscv|uartaddr[0] ; +; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|Selector162 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------+ +; Source assignments for altera_uart:uart ; ++-----------------------------+-------+------+----+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+----+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+----+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; +; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; +; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; +; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; +; PRESERVE_REGISTER ; ON ; - ; din_s1 ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------+ @@ -2030,226 +2163,236 @@ Encoding Type: One-Hot +---------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; -+--------------------------------------+----------------+-------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------------+----------------+-------------------------------------------------------+ -; reference_clock_frequency ; 50.0 MHz ; String ; -; fractional_vco_multiplier ; false ; String ; -; pll_type ; General ; String ; -; pll_subtype ; General ; String ; -; number_of_clocks ; 2 ; Signed Integer ; -; operation_mode ; direct ; String ; -; deserialization_factor ; 4 ; Signed Integer ; -; data_rate ; 0 ; Signed Integer ; -; sim_additional_refclk_cycles_to_lock ; 0 ; Signed Integer ; -; output_clock_frequency0 ; 100.000000 MHz ; String ; -; phase_shift0 ; 0 ps ; String ; -; duty_cycle0 ; 50 ; Signed Integer ; -; output_clock_frequency1 ; 75.000000 MHz ; String ; -; phase_shift1 ; 0 ps ; String ; -; duty_cycle1 ; 50 ; Signed Integer ; -; output_clock_frequency2 ; 0 MHz ; String ; -; phase_shift2 ; 0 ps ; String ; -; duty_cycle2 ; 50 ; Signed Integer ; -; output_clock_frequency3 ; 0 MHz ; String ; -; phase_shift3 ; 0 ps ; String ; -; duty_cycle3 ; 50 ; Signed Integer ; -; output_clock_frequency4 ; 0 MHz ; String ; -; phase_shift4 ; 0 ps ; String ; -; duty_cycle4 ; 50 ; Signed Integer ; -; output_clock_frequency5 ; 0 MHz ; String ; -; phase_shift5 ; 0 ps ; String ; -; duty_cycle5 ; 50 ; Signed Integer ; -; output_clock_frequency6 ; 0 MHz ; String ; -; phase_shift6 ; 0 ps ; String ; -; duty_cycle6 ; 50 ; Signed Integer ; -; output_clock_frequency7 ; 0 MHz ; String ; -; phase_shift7 ; 0 ps ; String ; -; duty_cycle7 ; 50 ; Signed Integer ; -; output_clock_frequency8 ; 0 MHz ; String ; -; phase_shift8 ; 0 ps ; String ; -; duty_cycle8 ; 50 ; Signed Integer ; -; output_clock_frequency9 ; 0 MHz ; String ; -; phase_shift9 ; 0 ps ; String ; -; duty_cycle9 ; 50 ; Signed Integer ; -; output_clock_frequency10 ; 0 MHz ; String ; -; phase_shift10 ; 0 ps ; String ; -; duty_cycle10 ; 50 ; Signed Integer ; -; output_clock_frequency11 ; 0 MHz ; String ; -; phase_shift11 ; 0 ps ; String ; -; duty_cycle11 ; 50 ; Signed Integer ; -; output_clock_frequency12 ; 0 MHz ; String ; -; phase_shift12 ; 0 ps ; String ; -; duty_cycle12 ; 50 ; Signed Integer ; -; output_clock_frequency13 ; 0 MHz ; String ; -; phase_shift13 ; 0 ps ; String ; -; duty_cycle13 ; 50 ; Signed Integer ; -; output_clock_frequency14 ; 0 MHz ; String ; -; phase_shift14 ; 0 ps ; String ; -; duty_cycle14 ; 50 ; Signed Integer ; -; output_clock_frequency15 ; 0 MHz ; String ; -; phase_shift15 ; 0 ps ; String ; -; duty_cycle15 ; 50 ; Signed Integer ; -; output_clock_frequency16 ; 0 MHz ; String ; -; phase_shift16 ; 0 ps ; String ; -; duty_cycle16 ; 50 ; Signed Integer ; -; output_clock_frequency17 ; 0 MHz ; String ; -; phase_shift17 ; 0 ps ; String ; -; duty_cycle17 ; 50 ; Signed Integer ; -; m_cnt_hi_div ; 1 ; Signed Integer ; -; m_cnt_lo_div ; 1 ; Signed Integer ; -; m_cnt_bypass_en ; false ; String ; -; m_cnt_odd_div_duty_en ; false ; String ; -; n_cnt_hi_div ; 1 ; Signed Integer ; -; n_cnt_lo_div ; 1 ; Signed Integer ; -; n_cnt_bypass_en ; false ; String ; -; n_cnt_odd_div_duty_en ; false ; String ; -; c_cnt_hi_div0 ; 1 ; Signed Integer ; -; c_cnt_lo_div0 ; 1 ; Signed Integer ; -; c_cnt_bypass_en0 ; false ; String ; -; c_cnt_in_src0 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en0 ; false ; String ; -; c_cnt_prst0 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst0 ; 0 ; Signed Integer ; -; c_cnt_hi_div1 ; 1 ; Signed Integer ; -; c_cnt_lo_div1 ; 1 ; Signed Integer ; -; c_cnt_bypass_en1 ; false ; String ; -; c_cnt_in_src1 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en1 ; false ; String ; -; c_cnt_prst1 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst1 ; 0 ; Signed Integer ; -; c_cnt_hi_div2 ; 1 ; Signed Integer ; -; c_cnt_lo_div2 ; 1 ; Signed Integer ; -; c_cnt_bypass_en2 ; false ; String ; -; c_cnt_in_src2 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en2 ; false ; String ; -; c_cnt_prst2 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst2 ; 0 ; Signed Integer ; -; c_cnt_hi_div3 ; 1 ; Signed Integer ; -; c_cnt_lo_div3 ; 1 ; Signed Integer ; -; c_cnt_bypass_en3 ; false ; String ; -; c_cnt_in_src3 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en3 ; false ; String ; -; c_cnt_prst3 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst3 ; 0 ; Signed Integer ; -; c_cnt_hi_div4 ; 1 ; Signed Integer ; -; c_cnt_lo_div4 ; 1 ; Signed Integer ; -; c_cnt_bypass_en4 ; false ; String ; -; c_cnt_in_src4 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en4 ; false ; String ; -; c_cnt_prst4 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst4 ; 0 ; Signed Integer ; -; c_cnt_hi_div5 ; 1 ; Signed Integer ; -; c_cnt_lo_div5 ; 1 ; Signed Integer ; -; c_cnt_bypass_en5 ; false ; String ; -; c_cnt_in_src5 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en5 ; false ; String ; -; c_cnt_prst5 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst5 ; 0 ; Signed Integer ; -; c_cnt_hi_div6 ; 1 ; Signed Integer ; -; c_cnt_lo_div6 ; 1 ; Signed Integer ; -; c_cnt_bypass_en6 ; false ; String ; -; c_cnt_in_src6 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en6 ; false ; String ; -; c_cnt_prst6 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst6 ; 0 ; Signed Integer ; -; c_cnt_hi_div7 ; 1 ; Signed Integer ; -; c_cnt_lo_div7 ; 1 ; Signed Integer ; -; c_cnt_bypass_en7 ; false ; String ; -; c_cnt_in_src7 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en7 ; false ; String ; -; c_cnt_prst7 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst7 ; 0 ; Signed Integer ; -; c_cnt_hi_div8 ; 1 ; Signed Integer ; -; c_cnt_lo_div8 ; 1 ; Signed Integer ; -; c_cnt_bypass_en8 ; false ; String ; -; c_cnt_in_src8 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en8 ; false ; String ; -; c_cnt_prst8 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst8 ; 0 ; Signed Integer ; -; c_cnt_hi_div9 ; 1 ; Signed Integer ; -; c_cnt_lo_div9 ; 1 ; Signed Integer ; -; c_cnt_bypass_en9 ; false ; String ; -; c_cnt_in_src9 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en9 ; false ; String ; -; c_cnt_prst9 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst9 ; 0 ; Signed Integer ; -; c_cnt_hi_div10 ; 1 ; Signed Integer ; -; c_cnt_lo_div10 ; 1 ; Signed Integer ; -; c_cnt_bypass_en10 ; false ; String ; -; c_cnt_in_src10 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en10 ; false ; String ; -; c_cnt_prst10 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst10 ; 0 ; Signed Integer ; -; c_cnt_hi_div11 ; 1 ; Signed Integer ; -; c_cnt_lo_div11 ; 1 ; Signed Integer ; -; c_cnt_bypass_en11 ; false ; String ; -; c_cnt_in_src11 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en11 ; false ; String ; -; c_cnt_prst11 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst11 ; 0 ; Signed Integer ; -; c_cnt_hi_div12 ; 1 ; Signed Integer ; -; c_cnt_lo_div12 ; 1 ; Signed Integer ; -; c_cnt_bypass_en12 ; false ; String ; -; c_cnt_in_src12 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en12 ; false ; String ; -; c_cnt_prst12 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst12 ; 0 ; Signed Integer ; -; c_cnt_hi_div13 ; 1 ; Signed Integer ; -; c_cnt_lo_div13 ; 1 ; Signed Integer ; -; c_cnt_bypass_en13 ; false ; String ; -; c_cnt_in_src13 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en13 ; false ; String ; -; c_cnt_prst13 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst13 ; 0 ; Signed Integer ; -; c_cnt_hi_div14 ; 1 ; Signed Integer ; -; c_cnt_lo_div14 ; 1 ; Signed Integer ; -; c_cnt_bypass_en14 ; false ; String ; -; c_cnt_in_src14 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en14 ; false ; String ; -; c_cnt_prst14 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst14 ; 0 ; Signed Integer ; -; c_cnt_hi_div15 ; 1 ; Signed Integer ; -; c_cnt_lo_div15 ; 1 ; Signed Integer ; -; c_cnt_bypass_en15 ; false ; String ; -; c_cnt_in_src15 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en15 ; false ; String ; -; c_cnt_prst15 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst15 ; 0 ; Signed Integer ; -; c_cnt_hi_div16 ; 1 ; Signed Integer ; -; c_cnt_lo_div16 ; 1 ; Signed Integer ; -; c_cnt_bypass_en16 ; false ; String ; -; c_cnt_in_src16 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en16 ; false ; String ; -; c_cnt_prst16 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst16 ; 0 ; Signed Integer ; -; c_cnt_hi_div17 ; 1 ; Signed Integer ; -; c_cnt_lo_div17 ; 1 ; Signed Integer ; -; c_cnt_bypass_en17 ; false ; String ; -; c_cnt_in_src17 ; ph_mux_clk ; String ; -; c_cnt_odd_div_duty_en17 ; false ; String ; -; c_cnt_prst17 ; 1 ; Signed Integer ; -; c_cnt_ph_mux_prst17 ; 0 ; Signed Integer ; -; pll_vco_div ; 1 ; Signed Integer ; -; pll_output_clk_frequency ; 0 MHz ; String ; -; pll_cp_current ; 0 ; Signed Integer ; -; pll_bwctrl ; 0 ; Signed Integer ; -; pll_fractional_division ; 1 ; Signed Integer ; -; pll_fractional_cout ; 24 ; Signed Integer ; -; pll_dsm_out_sel ; 1st_order ; String ; -; mimic_fbclk_type ; gclk ; String ; -; pll_fbclk_mux_1 ; glb ; String ; -; pll_fbclk_mux_2 ; fb_1 ; String ; -; pll_m_cnt_in_src ; ph_mux_clk ; String ; -; pll_vcoph_div ; 1 ; Signed Integer ; -; refclk1_frequency ; 0 MHz ; String ; -; pll_clkin_0_src ; clk_0 ; String ; -; pll_clkin_1_src ; clk_0 ; String ; -; pll_clk_loss_sw_en ; false ; String ; -; pll_auto_clk_sw_en ; false ; String ; -; pll_manu_clk_sw_en ; false ; String ; -; pll_clk_sw_dly ; 0 ; Signed Integer ; -+--------------------------------------+----------------+-------------------------------------------------------+ ++--------------------------------------+---------------+--------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------------+---------------+--------------------------------------------------------+ +; reference_clock_frequency ; 50.0 MHz ; String ; +; fractional_vco_multiplier ; false ; String ; +; pll_type ; General ; String ; +; pll_subtype ; General ; String ; +; number_of_clocks ; 2 ; Signed Integer ; +; operation_mode ; direct ; String ; +; deserialization_factor ; 4 ; Signed Integer ; +; data_rate ; 0 ; Signed Integer ; +; sim_additional_refclk_cycles_to_lock ; 0 ; Signed Integer ; +; output_clock_frequency0 ; 50.000000 MHz ; String ; +; phase_shift0 ; 0 ps ; String ; +; duty_cycle0 ; 50 ; Signed Integer ; +; output_clock_frequency1 ; 75.000000 MHz ; String ; +; phase_shift1 ; 0 ps ; String ; +; duty_cycle1 ; 50 ; Signed Integer ; +; output_clock_frequency2 ; 0 MHz ; String ; +; phase_shift2 ; 0 ps ; String ; +; duty_cycle2 ; 50 ; Signed Integer ; +; output_clock_frequency3 ; 0 MHz ; String ; +; phase_shift3 ; 0 ps ; String ; +; duty_cycle3 ; 50 ; Signed Integer ; +; output_clock_frequency4 ; 0 MHz ; String ; +; phase_shift4 ; 0 ps ; String ; +; duty_cycle4 ; 50 ; Signed Integer ; +; output_clock_frequency5 ; 0 MHz ; String ; +; phase_shift5 ; 0 ps ; String ; +; duty_cycle5 ; 50 ; Signed Integer ; +; output_clock_frequency6 ; 0 MHz ; String ; +; phase_shift6 ; 0 ps ; String ; +; duty_cycle6 ; 50 ; Signed Integer ; +; output_clock_frequency7 ; 0 MHz ; String ; +; phase_shift7 ; 0 ps ; String ; +; duty_cycle7 ; 50 ; Signed Integer ; +; output_clock_frequency8 ; 0 MHz ; String ; +; phase_shift8 ; 0 ps ; String ; +; duty_cycle8 ; 50 ; Signed Integer ; +; output_clock_frequency9 ; 0 MHz ; String ; +; phase_shift9 ; 0 ps ; String ; +; duty_cycle9 ; 50 ; Signed Integer ; +; output_clock_frequency10 ; 0 MHz ; String ; +; phase_shift10 ; 0 ps ; String ; +; duty_cycle10 ; 50 ; Signed Integer ; +; output_clock_frequency11 ; 0 MHz ; String ; +; phase_shift11 ; 0 ps ; String ; +; duty_cycle11 ; 50 ; Signed Integer ; +; output_clock_frequency12 ; 0 MHz ; String ; +; phase_shift12 ; 0 ps ; String ; +; duty_cycle12 ; 50 ; Signed Integer ; +; output_clock_frequency13 ; 0 MHz ; String ; +; phase_shift13 ; 0 ps ; String ; +; duty_cycle13 ; 50 ; Signed Integer ; +; output_clock_frequency14 ; 0 MHz ; String ; +; phase_shift14 ; 0 ps ; String ; +; duty_cycle14 ; 50 ; Signed Integer ; +; output_clock_frequency15 ; 0 MHz ; String ; +; phase_shift15 ; 0 ps ; String ; +; duty_cycle15 ; 50 ; Signed Integer ; +; output_clock_frequency16 ; 0 MHz ; String ; +; phase_shift16 ; 0 ps ; String ; +; duty_cycle16 ; 50 ; Signed Integer ; +; output_clock_frequency17 ; 0 MHz ; String ; +; phase_shift17 ; 0 ps ; String ; +; duty_cycle17 ; 50 ; Signed Integer ; +; m_cnt_hi_div ; 1 ; Signed Integer ; +; m_cnt_lo_div ; 1 ; Signed Integer ; +; m_cnt_bypass_en ; false ; String ; +; m_cnt_odd_div_duty_en ; false ; String ; +; n_cnt_hi_div ; 1 ; Signed Integer ; +; n_cnt_lo_div ; 1 ; Signed Integer ; +; n_cnt_bypass_en ; false ; String ; +; n_cnt_odd_div_duty_en ; false ; String ; +; c_cnt_hi_div0 ; 1 ; Signed Integer ; +; c_cnt_lo_div0 ; 1 ; Signed Integer ; +; c_cnt_bypass_en0 ; false ; String ; +; c_cnt_in_src0 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en0 ; false ; String ; +; c_cnt_prst0 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst0 ; 0 ; Signed Integer ; +; c_cnt_hi_div1 ; 1 ; Signed Integer ; +; c_cnt_lo_div1 ; 1 ; Signed Integer ; +; c_cnt_bypass_en1 ; false ; String ; +; c_cnt_in_src1 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en1 ; false ; String ; +; c_cnt_prst1 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst1 ; 0 ; Signed Integer ; +; c_cnt_hi_div2 ; 1 ; Signed Integer ; +; c_cnt_lo_div2 ; 1 ; Signed Integer ; +; c_cnt_bypass_en2 ; false ; String ; +; c_cnt_in_src2 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en2 ; false ; String ; +; c_cnt_prst2 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst2 ; 0 ; Signed Integer ; +; c_cnt_hi_div3 ; 1 ; Signed Integer ; +; c_cnt_lo_div3 ; 1 ; Signed Integer ; +; c_cnt_bypass_en3 ; false ; String ; +; c_cnt_in_src3 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en3 ; false ; String ; +; c_cnt_prst3 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst3 ; 0 ; Signed Integer ; +; c_cnt_hi_div4 ; 1 ; Signed Integer ; +; c_cnt_lo_div4 ; 1 ; Signed Integer ; +; c_cnt_bypass_en4 ; false ; String ; +; c_cnt_in_src4 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en4 ; false ; String ; +; c_cnt_prst4 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst4 ; 0 ; Signed Integer ; +; c_cnt_hi_div5 ; 1 ; Signed Integer ; +; c_cnt_lo_div5 ; 1 ; Signed Integer ; +; c_cnt_bypass_en5 ; false ; String ; +; c_cnt_in_src5 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en5 ; false ; String ; +; c_cnt_prst5 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst5 ; 0 ; Signed Integer ; +; c_cnt_hi_div6 ; 1 ; Signed Integer ; +; c_cnt_lo_div6 ; 1 ; Signed Integer ; +; c_cnt_bypass_en6 ; false ; String ; +; c_cnt_in_src6 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en6 ; false ; String ; +; c_cnt_prst6 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst6 ; 0 ; Signed Integer ; +; c_cnt_hi_div7 ; 1 ; Signed Integer ; +; c_cnt_lo_div7 ; 1 ; Signed Integer ; +; c_cnt_bypass_en7 ; false ; String ; +; c_cnt_in_src7 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en7 ; false ; String ; +; c_cnt_prst7 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst7 ; 0 ; Signed Integer ; +; c_cnt_hi_div8 ; 1 ; Signed Integer ; +; c_cnt_lo_div8 ; 1 ; Signed Integer ; +; c_cnt_bypass_en8 ; false ; String ; +; c_cnt_in_src8 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en8 ; false ; String ; +; c_cnt_prst8 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst8 ; 0 ; Signed Integer ; +; c_cnt_hi_div9 ; 1 ; Signed Integer ; +; c_cnt_lo_div9 ; 1 ; Signed Integer ; +; c_cnt_bypass_en9 ; false ; String ; +; c_cnt_in_src9 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en9 ; false ; String ; +; c_cnt_prst9 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst9 ; 0 ; Signed Integer ; +; c_cnt_hi_div10 ; 1 ; Signed Integer ; +; c_cnt_lo_div10 ; 1 ; Signed Integer ; +; c_cnt_bypass_en10 ; false ; String ; +; c_cnt_in_src10 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en10 ; false ; String ; +; c_cnt_prst10 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst10 ; 0 ; Signed Integer ; +; c_cnt_hi_div11 ; 1 ; Signed Integer ; +; c_cnt_lo_div11 ; 1 ; Signed Integer ; +; c_cnt_bypass_en11 ; false ; String ; +; c_cnt_in_src11 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en11 ; false ; String ; +; c_cnt_prst11 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst11 ; 0 ; Signed Integer ; +; c_cnt_hi_div12 ; 1 ; Signed Integer ; +; c_cnt_lo_div12 ; 1 ; Signed Integer ; +; c_cnt_bypass_en12 ; false ; String ; +; c_cnt_in_src12 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en12 ; false ; String ; +; c_cnt_prst12 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst12 ; 0 ; Signed Integer ; +; c_cnt_hi_div13 ; 1 ; Signed Integer ; +; c_cnt_lo_div13 ; 1 ; Signed Integer ; +; c_cnt_bypass_en13 ; false ; String ; +; c_cnt_in_src13 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en13 ; false ; String ; +; c_cnt_prst13 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst13 ; 0 ; Signed Integer ; +; c_cnt_hi_div14 ; 1 ; Signed Integer ; +; c_cnt_lo_div14 ; 1 ; Signed Integer ; +; c_cnt_bypass_en14 ; false ; String ; +; c_cnt_in_src14 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en14 ; false ; String ; +; c_cnt_prst14 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst14 ; 0 ; Signed Integer ; +; c_cnt_hi_div15 ; 1 ; Signed Integer ; +; c_cnt_lo_div15 ; 1 ; Signed Integer ; +; c_cnt_bypass_en15 ; false ; String ; +; c_cnt_in_src15 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en15 ; false ; String ; +; c_cnt_prst15 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst15 ; 0 ; Signed Integer ; +; c_cnt_hi_div16 ; 1 ; Signed Integer ; +; c_cnt_lo_div16 ; 1 ; Signed Integer ; +; c_cnt_bypass_en16 ; false ; String ; +; c_cnt_in_src16 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en16 ; false ; String ; +; c_cnt_prst16 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst16 ; 0 ; Signed Integer ; +; c_cnt_hi_div17 ; 1 ; Signed Integer ; +; c_cnt_lo_div17 ; 1 ; Signed Integer ; +; c_cnt_bypass_en17 ; false ; String ; +; c_cnt_in_src17 ; ph_mux_clk ; String ; +; c_cnt_odd_div_duty_en17 ; false ; String ; +; c_cnt_prst17 ; 1 ; Signed Integer ; +; c_cnt_ph_mux_prst17 ; 0 ; Signed Integer ; +; pll_vco_div ; 1 ; Signed Integer ; +; pll_output_clk_frequency ; 0 MHz ; String ; +; pll_cp_current ; 0 ; Signed Integer ; +; pll_bwctrl ; 0 ; Signed Integer ; +; pll_fractional_division ; 1 ; Signed Integer ; +; pll_fractional_cout ; 24 ; Signed Integer ; +; pll_dsm_out_sel ; 1st_order ; String ; +; mimic_fbclk_type ; gclk ; String ; +; pll_fbclk_mux_1 ; glb ; String ; +; pll_fbclk_mux_2 ; fb_1 ; String ; +; pll_m_cnt_in_src ; ph_mux_clk ; String ; +; pll_vcoph_div ; 1 ; Signed Integer ; +; refclk1_frequency ; 0 MHz ; String ; +; pll_clkin_0_src ; clk_0 ; String ; +; pll_clkin_1_src ; clk_0 ; String ; +; pll_clk_loss_sw_en ; false ; String ; +; pll_auto_clk_sw_en ; false ; String ; +; pll_manu_clk_sw_en ; false ; String ; +; pll_clk_sw_dly ; 0 ; Signed Integer ; ++--------------------------------------+---------------+--------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +; depth ; 2 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". @@ -2879,11 +3022,21 @@ Note: In order to hide this table in the UI and the text report file, please set +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ -; wRead ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; bReadAddr[1..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "altera_uart:uart" ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; chipselect ; Input ; Info ; Stuck at GND ; +; writedata ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; readdata ; Output ; Warning ; Output or bidir port (16 bits) is smaller than the port expression (32 bits) it drives. The 16 most-significant bit(s) in the port expression will be connected to GND. ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + +--------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "clk100M:clk100" ; +----------+--------+----------+-------------------------------------------------------------------------------------+ @@ -2899,7 +3052,7 @@ Note: In order to hide this table in the UI and the text report file, please set +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ -; Top ; 00:00:16 ; +; Top ; 00:00:18 ; +----------------+--------------+ @@ -2909,13 +3062,15 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Fri Aug 27 17:20:51 2021 + Info: Processing started: Sat Aug 28 11:02:08 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv Warning (125092): Tcl Script File alu/add_sub.qip not found Info (125063): set_global_assignment -name QIP_FILE alu/add_sub.qip Warning (125092): Tcl Script File alu/add_sub_s.qip not found Info (125063): set_global_assignment -name QIP_FILE alu/add_sub_s.qip Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. +Info (12021): Found 1 design units, including 1 entities, in source file de1_riscv_v2.v + Info (12023): Found entity 1: de1_riscv Warning (10335): Unrecognized synthesis attribute "HDL4SE" at ../verilog/riscv_core.v(49) Warning (10335): Unrecognized synthesis attribute "CLSID" at ../verilog/riscv_core.v(50) Warning (10335): Unrecognized synthesis attribute "softmodule" at ../verilog/riscv_core.v(51) @@ -2953,55 +3108,53 @@ Info (12021): Found 1 design units, including 1 entities, in source file clk/clk Info (12023): Found entity 1: clk100M Info (12021): Found 1 design units, including 1 entities, in source file clk/clk100m/clk100m_0002.v Info (12023): Found entity 1: clk100M_0002 -Warning (12125): Using design file de1_riscv.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project - Info (12023): Found entity 1: de1_riscv Info (12127): Elaborating entity "de1_riscv" for the top level hierarchy -Warning (10036): Verilog HDL or VHDL warning at de1_riscv.v(118): object "wRead_out" assigned a value but never read -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(169): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(170): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(171): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(172): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(173): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(174): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(177): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(178): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(179): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(180): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(181): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(182): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(185): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(186): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(187): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(188): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(189): truncated value with size 8 to match size of target (7) -Warning (10230): Verilog HDL assignment warning at de1_riscv.v(190): truncated value with size 8 to match size of target (7) -Warning (10034): Output port "DRAM_ADDR" at de1_riscv.v(31) has no driver -Warning (10034): Output port "DRAM_BA" at de1_riscv.v(32) has no driver -Warning (10034): Output port "LEDR" at de1_riscv.v(63) has no driver -Warning (10034): Output port "VGA_B" at de1_riscv.v(83) has no driver -Warning (10034): Output port "VGA_G" at de1_riscv.v(85) has no driver -Warning (10034): Output port "VGA_R" at de1_riscv.v(87) has no driver -Warning (10034): Output port "ADC_CONVST" at de1_riscv.v(11) has no driver -Warning (10034): Output port "ADC_DIN" at de1_riscv.v(12) has no driver -Warning (10034): Output port "ADC_SCLK" at de1_riscv.v(14) has no driver -Warning (10034): Output port "AUD_DACDAT" at de1_riscv.v(20) has no driver -Warning (10034): Output port "AUD_XCK" at de1_riscv.v(22) has no driver -Warning (10034): Output port "DRAM_CAS_N" at de1_riscv.v(33) has no driver -Warning (10034): Output port "DRAM_CKE" at de1_riscv.v(34) has no driver -Warning (10034): Output port "DRAM_CLK" at de1_riscv.v(35) has no driver -Warning (10034): Output port "DRAM_CS_N" at de1_riscv.v(36) has no driver -Warning (10034): Output port "DRAM_LDQM" at de1_riscv.v(38) has no driver -Warning (10034): Output port "DRAM_RAS_N" at de1_riscv.v(39) has no driver -Warning (10034): Output port "DRAM_UDQM" at de1_riscv.v(40) has no driver -Warning (10034): Output port "DRAM_WE_N" at de1_riscv.v(41) has no driver -Warning (10034): Output port "FPGA_I2C_SCLK" at de1_riscv.v(44) has no driver -Warning (10034): Output port "IRDA_TXD" at de1_riscv.v(57) has no driver -Warning (10034): Output port "TD_RESET_N" at de1_riscv.v(78) has no driver -Warning (10034): Output port "VGA_BLANK_N" at de1_riscv.v(82) has no driver -Warning (10034): Output port "VGA_CLK" at de1_riscv.v(84) has no driver -Warning (10034): Output port "VGA_HS" at de1_riscv.v(86) has no driver -Warning (10034): Output port "VGA_SYNC_N" at de1_riscv.v(88) has no driver -Warning (10034): Output port "VGA_VS" at de1_riscv.v(89) has no driver +Warning (10036): Verilog HDL or VHDL warning at de1_riscv_v2.v(124): object "wRead_out" assigned a value but never read +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(197): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(198): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(199): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(200): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(201): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(202): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(205): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(206): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(207): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(208): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(209): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(210): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(213): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(214): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(215): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(216): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(217): truncated value with size 8 to match size of target (7) +Warning (10230): Verilog HDL assignment warning at de1_riscv_v2.v(218): truncated value with size 8 to match size of target (7) +Warning (10034): Output port "DRAM_ADDR" at de1_riscv_v2.v(31) has no driver +Warning (10034): Output port "DRAM_BA" at de1_riscv_v2.v(32) has no driver +Warning (10034): Output port "LEDR[9..3]" at de1_riscv_v2.v(63) has no driver +Warning (10034): Output port "VGA_B" at de1_riscv_v2.v(83) has no driver +Warning (10034): Output port "VGA_G" at de1_riscv_v2.v(85) has no driver +Warning (10034): Output port "VGA_R" at de1_riscv_v2.v(87) has no driver +Warning (10034): Output port "ADC_CONVST" at de1_riscv_v2.v(11) has no driver +Warning (10034): Output port "ADC_DIN" at de1_riscv_v2.v(12) has no driver +Warning (10034): Output port "ADC_SCLK" at de1_riscv_v2.v(14) has no driver +Warning (10034): Output port "AUD_DACDAT" at de1_riscv_v2.v(20) has no driver +Warning (10034): Output port "AUD_XCK" at de1_riscv_v2.v(22) has no driver +Warning (10034): Output port "DRAM_CAS_N" at de1_riscv_v2.v(33) has no driver +Warning (10034): Output port "DRAM_CKE" at de1_riscv_v2.v(34) has no driver +Warning (10034): Output port "DRAM_CLK" at de1_riscv_v2.v(35) has no driver +Warning (10034): Output port "DRAM_CS_N" at de1_riscv_v2.v(36) has no driver +Warning (10034): Output port "DRAM_LDQM" at de1_riscv_v2.v(38) has no driver +Warning (10034): Output port "DRAM_RAS_N" at de1_riscv_v2.v(39) has no driver +Warning (10034): Output port "DRAM_UDQM" at de1_riscv_v2.v(40) has no driver +Warning (10034): Output port "DRAM_WE_N" at de1_riscv_v2.v(41) has no driver +Warning (10034): Output port "FPGA_I2C_SCLK" at de1_riscv_v2.v(44) has no driver +Warning (10034): Output port "IRDA_TXD" at de1_riscv_v2.v(57) has no driver +Warning (10034): Output port "TD_RESET_N" at de1_riscv_v2.v(78) has no driver +Warning (10034): Output port "VGA_BLANK_N" at de1_riscv_v2.v(82) has no driver +Warning (10034): Output port "VGA_CLK" at de1_riscv_v2.v(84) has no driver +Warning (10034): Output port "VGA_HS" at de1_riscv_v2.v(86) has no driver +Warning (10034): Output port "VGA_SYNC_N" at de1_riscv_v2.v(88) has no driver +Warning (10034): Output port "VGA_VS" at de1_riscv_v2.v(89) has no driver Info (12128): Elaborating entity "clk100M" for hierarchy "clk100M:clk100" Info (12128): Elaborating entity "clk100M_0002" for hierarchy "clk100M:clk100|clk100M_0002:clk100m_inst" Info (12128): Elaborating entity "altera_pll" for hierarchy "clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i" @@ -3016,7 +3169,7 @@ Info (12133): Instantiated megafunction "clk100M:clk100|clk100M_0002:clk100m_ins Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" Info (12134): Parameter "operation_mode" = "direct" Info (12134): Parameter "number_of_clocks" = "2" - Info (12134): Parameter "output_clock_frequency0" = "100.000000 MHz" + Info (12134): Parameter "output_clock_frequency0" = "50.000000 MHz" Info (12134): Parameter "phase_shift0" = "0 ps" Info (12134): Parameter "duty_cycle0" = "50" Info (12134): Parameter "output_clock_frequency1" = "75.000000 MHz" @@ -3072,6 +3225,15 @@ Info (12133): Instantiated megafunction "clk100M:clk100|clk100M_0002:clk100m_ins Info (12134): Parameter "duty_cycle17" = "50" Info (12134): Parameter "pll_type" = "General" Info (12134): Parameter "pll_subtype" = "General" +Info (12128): Elaborating entity "altera_uart" for hierarchy "altera_uart:uart" +Info (12128): Elaborating entity "altera_uart_tx" for hierarchy "altera_uart:uart|altera_uart_tx:the_altera_uart_tx" +Info (12128): Elaborating entity "altera_uart_rx" for hierarchy "altera_uart:uart|altera_uart_rx:the_altera_uart_rx" +Info (12128): Elaborating entity "altera_uart_rx_stimulus_source" for hierarchy "altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_uart_rx_stimulus_source:the_altera_uart_rx_stimulus_source" +Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" +Info (12130): Elaborated megafunction instantiation "altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" +Info (12133): Instantiated megafunction "altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: + Info (12134): Parameter "depth" = "2" +Info (12128): Elaborating entity "altera_uart_regs" for hierarchy "altera_uart:uart|altera_uart_regs:the_altera_uart_regs" Info (12128): Elaborating entity "regfile" for hierarchy "regfile:regs" Info (12128): Elaborating entity "altsyncram" for hierarchy "regfile:regs|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "regfile:regs|altsyncram:altsyncram_component" @@ -3118,14 +3280,14 @@ Info (12021): Found 1 design units, including 1 entities, in source file db/alts Info (12023): Found entity 1: altsyncram_bdq1 Info (12128): Elaborating entity "altsyncram_bdq1" for hierarchy "ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated" Info (12128): Elaborating entity "riscv_core" for hierarchy "riscv_core:core" -Warning (10762): Verilog HDL Case Statement warning at riscv_core.v(180): can't check case statement for completeness because the case expression has too many possible states -Warning (10762): Verilog HDL Case Statement warning at riscv_core.v(200): can't check case statement for completeness because the case expression has too many possible states -Warning (10230): Verilog HDL assignment warning at riscv_core.v(251): truncated value with size 32 to match size of target (5) -Warning (10230): Verilog HDL assignment warning at riscv_core.v(288): truncated value with size 32 to match size of target (1) -Info (10264): Verilog HDL Case Statement information at riscv_core.v(274): all case item expressions in this case statement are onehot -Warning (10230): Verilog HDL assignment warning at riscv_core.v(316): truncated value with size 32 to match size of target (2) -Warning (10230): Verilog HDL assignment warning at riscv_core.v(320): truncated value with size 32 to match size of target (2) -Info (10264): Verilog HDL Case Statement information at riscv_core.v(326): all case item expressions in this case statement are onehot +Warning (10762): Verilog HDL Case Statement warning at riscv_core.v(181): can't check case statement for completeness because the case expression has too many possible states +Warning (10762): Verilog HDL Case Statement warning at riscv_core.v(201): can't check case statement for completeness because the case expression has too many possible states +Warning (10230): Verilog HDL assignment warning at riscv_core.v(252): truncated value with size 32 to match size of target (5) +Warning (10230): Verilog HDL assignment warning at riscv_core.v(289): truncated value with size 32 to match size of target (1) +Info (10264): Verilog HDL Case Statement information at riscv_core.v(275): all case item expressions in this case statement are onehot +Warning (10230): Verilog HDL assignment warning at riscv_core.v(317): truncated value with size 32 to match size of target (2) +Warning (10230): Verilog HDL assignment warning at riscv_core.v(321): truncated value with size 32 to match size of target (2) +Info (10264): Verilog HDL Case Statement information at riscv_core.v(327): all case item expressions in this case statement are onehot Info (12128): Elaborating entity "adder" for hierarchy "riscv_core:core|adder:add" Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component" Info (12130): Elaborated megafunction instantiation "riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component" @@ -3408,6 +3570,7 @@ Info (12021): Found 1 design units, including 1 entities, in source file db/cntr Info (12023): Found entity 1: cntr_ohf Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_a9c.tdf Info (12023): Found entity 1: cmpr_a9c +Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder Warning (13039): The following bidir pins have no drivers Warning (13040): Bidir "AUD_ADCLRCK" has no driver Warning (13040): Bidir "AUD_BCLK" has no driver @@ -3438,9 +3601,7 @@ Warning (13039): The following bidir pins have no drivers Warning (13040): Bidir "GPIO[2]" has no driver Warning (13040): Bidir "GPIO[3]" has no driver Warning (13040): Bidir "GPIO[4]" has no driver - Warning (13040): Bidir "GPIO[5]" has no driver Warning (13040): Bidir "GPIO[6]" has no driver - Warning (13040): Bidir "GPIO[7]" has no driver Warning (13040): Bidir "GPIO[8]" has no driver Warning (13040): Bidir "GPIO[9]" has no driver Warning (13040): Bidir "GPIO[10]" has no driver @@ -3469,6 +3630,10 @@ Warning (13039): The following bidir pins have no drivers Warning (13040): Bidir "GPIO[33]" has no driver Warning (13040): Bidir "GPIO[34]" has no driver Warning (13040): Bidir "GPIO[35]" has no driver +Warning (13032): The following tri-state nodes are fed by constants + Warning (13033): The pin "GPIO[5]" is fed by VCC +Warning (13009): TRI or OPNDRN buffers permanently enabled + Warning (13010): Node "GPIO[5]~synth" Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "ADC_CONVST" is stuck at GND Warning (13410): Pin "ADC_DIN" is stuck at GND @@ -3500,9 +3665,7 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "DRAM_WE_N" is stuck at GND Warning (13410): Pin "FPGA_I2C_SCLK" is stuck at GND Warning (13410): Pin "IRDA_TXD" is stuck at GND - Warning (13410): Pin "LEDR[0]" is stuck at GND Warning (13410): Pin "LEDR[1]" is stuck at GND - Warning (13410): Pin "LEDR[2]" is stuck at GND Warning (13410): Pin "LEDR[3]" is stuck at GND Warning (13410): Pin "LEDR[4]" is stuck at GND Warning (13410): Pin "LEDR[5]" is stuck at GND @@ -3540,7 +3703,7 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "VGA_R[7]" is stuck at GND Warning (13410): Pin "VGA_SYNC_N" is stuck at GND Warning (13410): Pin "VGA_VS" is stuck at GND -Info (17049): 4 registers lost all their fanouts during netlist optimizations. +Info (17049): 34 registers lost all their fanouts during netlist optimizations. Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 5 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 17 input pin(s) that do not drive logic @@ -3561,18 +3724,18 @@ Warning (21074): Design contains 17 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "TD_DATA[7]" Warning (15610): No output dependent on input pin "TD_HS" Warning (15610): No output dependent on input pin "TD_VS" -Info (21057): Implemented 5054 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 5105 device resources after synthesis - the final resource count might be different Info (21058): Implemented 32 input pins Info (21059): Implemented 112 output pins Info (21060): Implemented 60 bidirectional pins - Info (21061): Implemented 4672 logic cells + Info (21061): Implemented 4723 logic cells Info (21064): Implemented 167 RAM segments Info (21065): Implemented 1 PLLs Info (21062): Implemented 10 DSP elements Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 215 warnings Info: Peak virtual memory: 670 megabytes - Info: Processing ended: Fri Aug 27 17:21:13 2021 - Info: Elapsed time: 00:00:22 - Info: Total CPU time (on all processors): 00:00:22 + Info: Processing ended: Sat Aug 28 11:02:31 2021 + Info: Elapsed time: 00:00:23 + Info: Total CPU time (on all processors): 00:00:23 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.map.summary b/examples/hdl4se_riscv/de1/de1_riscv.map.summary index 743ccac97aa7901bf17c7c5b1de7f428439554df..f9856d7e486e800f94632d95669f5419d1a5f5a4 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.map.summary +++ b/examples/hdl4se_riscv/de1/de1_riscv.map.summary @@ -1,10 +1,10 @@ -Analysis & Synthesis Status : Successful - Fri Aug 27 17:21:13 2021 +Analysis & Synthesis Status : Successful - Sat Aug 28 11:02:31 2021 Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version Revision Name : de1_riscv Top-level Entity Name : de1_riscv Family : Cyclone V Logic utilization (in ALMs) : N/A -Total registers : 1608 +Total registers : 1636 Total pins : 204 Total virtual pins : 0 Total block memory bits : 67,296 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.qsf b/examples/hdl4se_riscv/de1/de1_riscv.qsf index 8b651c89d550b4a3562210aec0dfe29e628b0e92..eb89178c64d6bdb932be7610e8a3343a6f14eed7 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.qsf +++ b/examples/hdl4se_riscv/de1/de1_riscv.qsf @@ -488,6 +488,7 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE de1_riscv_v2.v set_global_assignment -name VERILOG_FILE ../verilog/riscv_core.v set_global_assignment -name VERILOG_FILE uart/altera_uart.v set_global_assignment -name VERILOG_FILE vgasig.v diff --git a/examples/hdl4se_riscv/de1/de1_riscv.qws b/examples/hdl4se_riscv/de1/de1_riscv.qws deleted file mode 100644 index 237a0d14a4d22917f0f97b8e6d42ddf1875888a6..0000000000000000000000000000000000000000 Binary files a/examples/hdl4se_riscv/de1/de1_riscv.qws and /dev/null differ diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sof b/examples/hdl4se_riscv/de1/de1_riscv.sof deleted file mode 100644 index 5d9ec9b874c15e7c0f5fb343f5aaf43f2a58bcc0..0000000000000000000000000000000000000000 Binary files a/examples/hdl4se_riscv/de1/de1_riscv.sof and /dev/null differ diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt b/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt index 5819dd315b254245329a26e955c022f07f6abc3f..30b67aae3f6eea3304216029a1d6ba521f02a562 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt +++ b/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for de1_riscv -Fri Aug 27 17:24:01 2021 +Sat Aug 28 10:56:45 2021 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -22,55 +22,63 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version 14. Hold Times 15. Clock to Output Times 16. Minimum Clock to Output Times - 17. Slow 1100mV 85C Model Metastability Report - 18. Slow 1100mV 0C Model Fmax Summary - 19. Slow 1100mV 0C Model Setup Summary - 20. Slow 1100mV 0C Model Hold Summary - 21. Slow 1100mV 0C Model Recovery Summary - 22. Slow 1100mV 0C Model Removal Summary - 23. Slow 1100mV 0C Model Minimum Pulse Width Summary - 24. Setup Times - 25. Hold Times - 26. Clock to Output Times - 27. Minimum Clock to Output Times - 28. Slow 1100mV 0C Model Metastability Report - 29. Fast 1100mV 85C Model Setup Summary - 30. Fast 1100mV 85C Model Hold Summary - 31. Fast 1100mV 85C Model Recovery Summary - 32. Fast 1100mV 85C Model Removal Summary - 33. Fast 1100mV 85C Model Minimum Pulse Width Summary - 34. Setup Times - 35. Hold Times - 36. Clock to Output Times - 37. Minimum Clock to Output Times - 38. Fast 1100mV 85C Model Metastability Report - 39. Fast 1100mV 0C Model Setup Summary - 40. Fast 1100mV 0C Model Hold Summary - 41. Fast 1100mV 0C Model Recovery Summary - 42. Fast 1100mV 0C Model Removal Summary - 43. Fast 1100mV 0C Model Minimum Pulse Width Summary - 44. Setup Times - 45. Hold Times - 46. Clock to Output Times - 47. Minimum Clock to Output Times - 48. Fast 1100mV 0C Model Metastability Report - 49. Multicorner Timing Analysis Summary + 17. MTBF Summary + 18. Synchronizer Summary + 19. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 20. Slow 1100mV 0C Model Fmax Summary + 21. Slow 1100mV 0C Model Setup Summary + 22. Slow 1100mV 0C Model Hold Summary + 23. Slow 1100mV 0C Model Recovery Summary + 24. Slow 1100mV 0C Model Removal Summary + 25. Slow 1100mV 0C Model Minimum Pulse Width Summary + 26. Setup Times + 27. Hold Times + 28. Clock to Output Times + 29. Minimum Clock to Output Times + 30. MTBF Summary + 31. Synchronizer Summary + 32. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 33. Fast 1100mV 85C Model Setup Summary + 34. Fast 1100mV 85C Model Hold Summary + 35. Fast 1100mV 85C Model Recovery Summary + 36. Fast 1100mV 85C Model Removal Summary + 37. Fast 1100mV 85C Model Minimum Pulse Width Summary + 38. Setup Times + 39. Hold Times + 40. Clock to Output Times + 41. Minimum Clock to Output Times + 42. MTBF Summary + 43. Synchronizer Summary + 44. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 45. Fast 1100mV 0C Model Setup Summary + 46. Fast 1100mV 0C Model Hold Summary + 47. Fast 1100mV 0C Model Recovery Summary + 48. Fast 1100mV 0C Model Removal Summary + 49. Fast 1100mV 0C Model Minimum Pulse Width Summary 50. Setup Times 51. Hold Times 52. Clock to Output Times 53. Minimum Clock to Output Times - 54. Board Trace Model Assignments - 55. Input Transition Times - 56. Signal Integrity Metrics (Slow 1100mv 0c Model) - 57. Signal Integrity Metrics (Slow 1100mv 85c Model) - 58. Signal Integrity Metrics (Fast 1100mv 0c Model) - 59. Signal Integrity Metrics (Fast 1100mv 85c Model) - 60. Setup Transfers - 61. Hold Transfers - 62. Report TCCS - 63. Report RSKM - 64. Unconstrained Paths - 65. TimeQuest Timing Analyzer Messages + 54. MTBF Summary + 55. Synchronizer Summary + 56. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years + 57. Multicorner Timing Analysis Summary + 58. Setup Times + 59. Hold Times + 60. Clock to Output Times + 61. Minimum Clock to Output Times + 62. Board Trace Model Assignments + 63. Input Transition Times + 64. Signal Integrity Metrics (Slow 1100mv 0c Model) + 65. Signal Integrity Metrics (Slow 1100mv 85c Model) + 66. Signal Integrity Metrics (Fast 1100mv 0c Model) + 67. Signal Integrity Metrics (Fast 1100mv 85c Model) + 68. Setup Transfers + 69. Hold Transfers + 70. Report TCCS + 71. Report RSKM + 72. Unconstrained Paths + 73. TimeQuest Timing Analyzer Messages @@ -114,12 +122,12 @@ applicable agreement for further details. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.33 ; +; Average used ; 1.37 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 33.3% ; +; Processor 2 ; 36.7% ; ; Processors 3-4 ; 0.0% ; +----------------------------+-------------+ @@ -129,7 +137,7 @@ applicable agreement for further details. +---------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +---------------+--------+--------------------------+ -; de1_riscv.SDC ; OK ; Fri Aug 27 17:23:34 2021 ; +; de1_riscv.SDC ; OK ; Sat Aug 28 10:56:17 2021 ; +---------------+--------+--------------------------+ @@ -157,7 +165,7 @@ applicable agreement for further details. +-----------+-----------------+----------------------------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+----------------------------------------------------------------------------+------+ -; 85.26 MHz ; 85.26 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; +; 89.31 MHz ; 89.31 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; +-----------+-----------------+----------------------------------------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -173,7 +181,7 @@ HTML report is unavailable in plain text report export. +----------------------------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+--------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.729 ; -126.223 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.197 ; -95.783 ; +----------------------------------------------------------------------------+--------+---------------+ @@ -182,7 +190,7 @@ HTML report is unavailable in plain text report export. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.281 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.266 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -209,28 +217,28 @@ No paths to report. +----------------------------------------------------------------------------+-------+---------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.848 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.848 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.800 ; 1.535 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.537 ; 1.036 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.698 ; 1.590 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 2.301 ; 3.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.438 ; 0.353 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.707 ; 1.571 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.197 ; 0.867 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.380 ; 1.376 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 0.163 ; 0.850 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.322 ; 0.217 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 1.129 ; 2.049 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 2.286 ; 3.285 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 1.216 ; 2.080 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 2.301 ; 3.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.834 ; 1.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.187 ; 0.869 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.416 ; 0.790 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.534 ; 0.859 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.605 ; 0.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -0.912 ; 0.016 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.577 ; 0.402 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 0.128 ; 1.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.518 ; -1.025 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.963 ; 1.365 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.752 ; 2.499 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.529 ; 2.464 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -238,22 +246,22 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 4.072 ; 3.504 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 3.249 ; 2.498 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 3.192 ; 2.501 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 3.722 ; 3.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 4.072 ; 3.504 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 3.232 ; 2.671 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 2.271 ; 1.612 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 1.286 ; 0.605 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 2.758 ; 2.185 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 2.390 ; 1.679 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 2.878 ; 2.400 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 2.565 ; 1.980 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 2.732 ; 2.097 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 2.977 ; 2.395 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 2.888 ; 2.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 3.232 ; 2.671 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[*] ; CLOCK_50 ; 4.302 ; 3.725 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 3.367 ; 2.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 3.157 ; 2.342 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 3.591 ; 2.859 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 4.302 ; 3.725 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 3.581 ; 3.092 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 1.571 ; 1.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 2.354 ; 1.795 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 3.058 ; 2.482 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 3.291 ; 2.737 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 2.945 ; 2.456 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 3.581 ; 3.092 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 2.675 ; 2.107 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 3.114 ; 2.543 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 3.218 ; 2.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 3.468 ; 2.939 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -262,54 +270,57 @@ No paths to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 14.397 ; 13.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 14.397 ; 13.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 12.554 ; 12.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 13.186 ; 12.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 13.466 ; 12.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 13.073 ; 12.669 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 13.697 ; 13.039 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 13.855 ; 13.136 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 14.821 ; 13.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 14.821 ; 13.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 14.193 ; 13.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 14.321 ; 13.382 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 13.918 ; 13.105 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 12.323 ; 12.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 13.546 ; 12.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 14.493 ; 13.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 14.577 ; 13.594 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 14.577 ; 13.594 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 13.334 ; 12.689 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 13.293 ; 12.654 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 13.415 ; 12.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 13.271 ; 12.652 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 12.836 ; 12.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 13.395 ; 12.746 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 15.528 ; 14.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 13.620 ; 12.915 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 12.933 ; 12.507 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 12.936 ; 12.659 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 15.528 ; 14.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 13.518 ; 12.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 13.765 ; 13.151 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 13.270 ; 12.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 14.396 ; 13.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 12.762 ; 12.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 13.611 ; 12.890 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 14.396 ; 13.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 14.278 ; 13.400 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 12.923 ; 12.634 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 13.863 ; 13.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 12.517 ; 12.337 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 13.665 ; 13.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 13.665 ; 12.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 12.819 ; 12.431 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 11.916 ; 11.815 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 12.759 ; 12.363 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 12.719 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 12.148 ; 11.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 13.601 ; 13.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 14.002 ; 13.202 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 13.120 ; 12.618 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 13.313 ; 12.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 13.693 ; 13.119 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 13.759 ; 12.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 12.800 ; 12.470 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 12.430 ; 12.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 11.957 ; 11.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 12.990 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 13.273 ; 12.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 13.295 ; 12.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 12.618 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 13.457 ; 12.840 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 13.921 ; 13.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 12.588 ; 12.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 12.623 ; 12.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 13.284 ; 12.846 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 13.455 ; 12.789 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 12.868 ; 12.384 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 13.020 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 13.452 ; 12.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 13.575 ; 12.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 13.547 ; 12.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 12.700 ; 12.379 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 13.197 ; 12.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 13.581 ; 12.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 13.297 ; 12.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 12.741 ; 12.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 12.477 ; 12.232 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 12.414 ; 12.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 13.948 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 13.425 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 13.810 ; 13.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 13.826 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 12.646 ; 12.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 13.948 ; 13.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 13.937 ; 13.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 12.793 ; 12.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 12.782 ; 12.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ @@ -318,61 +329,123 @@ No paths to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 11.271 ; 11.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 12.710 ; 12.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 11.271 ; 11.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 11.831 ; 11.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 12.124 ; 11.715 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 11.734 ; 11.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 12.073 ; 11.665 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 12.216 ; 11.763 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 11.082 ; 10.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 13.083 ; 12.344 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 12.665 ; 12.095 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 12.648 ; 11.993 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 12.266 ; 11.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 11.082 ; 10.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 12.033 ; 11.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 12.754 ; 12.116 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 11.423 ; 11.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 12.885 ; 12.185 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 11.738 ; 11.349 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 11.700 ; 11.316 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 11.826 ; 11.425 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 11.702 ; 11.324 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 11.423 ; 11.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 11.815 ; 11.417 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 11.516 ; 11.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 12.012 ; 11.562 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 11.516 ; 11.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 11.582 ; 11.397 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 13.726 ; 12.803 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 11.907 ; 11.481 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 12.228 ; 11.807 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 11.891 ; 11.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 11.250 ; 11.122 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 11.420 ; 11.229 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 11.974 ; 11.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 12.712 ; 12.064 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 12.595 ; 12.000 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 11.579 ; 11.379 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 12.208 ; 11.706 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 11.250 ; 11.122 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 10.700 ; 10.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 12.062 ; 11.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 11.406 ; 11.171 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 10.700 ; 10.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 11.342 ; 11.109 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 11.418 ; 11.250 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 10.895 ; 10.767 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 12.182 ; 11.779 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 11.448 ; 11.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 12.320 ; 11.814 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 11.662 ; 11.334 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 11.854 ; 11.468 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 12.274 ; 11.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 12.093 ; 11.596 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 11.448 ; 11.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 12.491 ; 11.917 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 10.744 ; 10.741 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 12.415 ; 11.868 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 11.163 ; 11.018 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 10.744 ; 10.741 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 11.442 ; 11.163 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 11.689 ; 11.310 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 11.714 ; 11.343 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 11.320 ; 11.228 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 11.310 ; 11.149 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 11.931 ; 11.522 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 12.275 ; 11.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 11.312 ; 11.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 11.310 ; 11.149 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 11.867 ; 11.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 11.854 ; 11.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 12.395 ; 11.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 11.333 ; 11.073 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 11.333 ; 11.073 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 11.451 ; 11.144 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 12.096 ; 11.657 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 12.042 ; 11.656 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 11.982 ; 11.544 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 11.955 ; 11.506 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 11.390 ; 11.162 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 11.118 ; 10.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 11.716 ; 11.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 11.932 ; 11.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 11.706 ; 11.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 12.243 ; 11.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 11.302 ; 11.098 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 11.152 ; 10.999 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 11.118 ; 10.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 11.339 ; 11.229 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 11.817 ; 11.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 12.120 ; 11.626 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 12.178 ; 11.750 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 11.339 ; 11.229 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 12.302 ; 11.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 12.258 ; 11.718 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 11.474 ; 11.243 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 10.599 ; 10.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 10.623 ; 10.733 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 10.599 ; 10.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ----------------------------------------------- -; Slow 1100mV 85C Model Metastability Report ; ----------------------------------------------- -No synchronizer chains to report. +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 17.536 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; GPIO[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO[7] ; +; Synchronization Node ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 17.536 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.080 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.456 ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + +-----------------------------------------------------------------------------------------------------------------+ @@ -380,7 +453,7 @@ No synchronizer chains to report. +-----------+-----------------+----------------------------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+----------------------------------------------------------------------------+------+ -; 84.14 MHz ; 84.14 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; +; 88.09 MHz ; 88.09 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; +-----------+-----------------+----------------------------------------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -390,7 +463,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+--------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.885 ; -158.135 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.352 ; -121.670 ; +----------------------------------------------------------------------------+--------+---------------+ @@ -399,7 +472,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.260 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.247 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -421,33 +494,33 @@ No paths to report. ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.753 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.758 ; 0.000 ; ; CLOCK_50 ; 9.673 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.702 ; 1.518 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.702 ; 1.518 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.585 ; 1.367 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.356 ; 0.888 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.490 ; 1.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 2.173 ; 3.235 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.723 ; 0.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.534 ; 1.480 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.425 ; 0.751 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.230 ; 1.305 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; -0.112 ; 0.686 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.534 ; 0.092 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 0.847 ; 1.887 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 2.173 ; 3.235 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 0.950 ; 1.919 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 2.109 ; 3.221 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 0.981 ; 2.410 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.699 ; 1.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 0.981 ; 2.410 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.379 ; 0.805 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.703 ; 0.621 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.585 ; 4.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.417 ; 0.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.805 ; -0.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -1.104 ; -0.076 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.767 ; 0.312 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; -0.065 ; 0.911 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.669 ; -1.138 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.758 ; 1.223 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 2.585 ; 4.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.516 ; 2.359 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.239 ; 2.310 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -455,22 +528,22 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 4.197 ; 3.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 3.311 ; 2.588 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 3.283 ; 2.577 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 3.831 ; 3.218 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 4.197 ; 3.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 3.341 ; 2.720 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 2.465 ; 1.724 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 1.393 ; 0.663 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 2.898 ; 2.280 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 2.472 ; 1.701 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 3.051 ; 2.517 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 2.728 ; 2.072 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 2.934 ; 2.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 3.061 ; 2.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 3.081 ; 2.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 3.341 ; 2.720 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[*] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 3.381 ; 2.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 3.217 ; 2.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 3.644 ; 2.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 1.617 ; 1.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 2.455 ; 1.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 3.152 ; 2.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 3.415 ; 2.830 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 3.069 ; 2.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 2.788 ; 2.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 3.171 ; 2.538 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 3.327 ; 2.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 3.589 ; 2.995 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -479,54 +552,57 @@ No paths to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 14.181 ; 13.254 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 14.181 ; 13.254 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 12.223 ; 11.986 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 12.906 ; 12.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 13.182 ; 12.652 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 12.782 ; 12.350 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 13.425 ; 12.752 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 13.532 ; 12.811 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 14.619 ; 13.557 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 14.619 ; 13.557 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 13.960 ; 13.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 14.121 ; 13.171 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 13.698 ; 12.875 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 11.994 ; 11.831 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 13.287 ; 12.707 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 14.228 ; 13.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 14.369 ; 13.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 14.369 ; 13.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 13.096 ; 12.446 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 13.044 ; 12.404 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 13.160 ; 12.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 13.022 ; 12.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 12.544 ; 12.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 13.151 ; 12.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 15.365 ; 14.099 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 13.360 ; 12.645 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 12.661 ; 12.205 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 12.572 ; 12.267 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 15.365 ; 14.099 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 13.289 ; 12.592 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 13.513 ; 12.858 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 12.949 ; 12.487 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 14.189 ; 13.246 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 12.442 ; 12.133 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 13.320 ; 12.599 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 14.189 ; 13.246 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 14.055 ; 13.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 12.632 ; 12.297 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 13.604 ; 12.815 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 12.182 ; 11.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 13.429 ; 12.737 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 13.429 ; 12.671 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 12.530 ; 12.125 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 11.609 ; 11.493 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 12.474 ; 12.059 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 12.348 ; 12.086 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 11.845 ; 11.640 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 13.305 ; 12.737 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 13.992 ; 13.085 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 13.779 ; 12.963 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 12.857 ; 12.333 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 13.056 ; 12.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 13.462 ; 12.860 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 13.546 ; 12.751 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 12.535 ; 12.172 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 13.992 ; 13.085 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 13.862 ; 13.007 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 13.862 ; 13.007 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 12.110 ; 11.866 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 11.676 ; 11.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 12.760 ; 12.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 13.042 ; 12.404 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 13.041 ; 12.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 12.305 ; 12.109 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 13.878 ; 12.987 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 13.237 ; 12.601 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 13.715 ; 12.900 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 12.278 ; 12.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 12.364 ; 12.091 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 13.022 ; 12.549 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 13.230 ; 12.555 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 13.878 ; 12.987 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 13.372 ; 12.708 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 12.627 ; 12.136 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 12.790 ; 12.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 13.372 ; 12.708 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 13.222 ; 12.682 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 13.327 ; 12.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 13.321 ; 12.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 12.410 ; 12.059 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 13.696 ; 12.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 12.951 ; 12.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 13.367 ; 12.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 13.056 ; 12.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 13.696 ; 12.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 12.463 ; 12.069 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 12.210 ; 11.946 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 12.148 ; 11.895 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 13.741 ; 12.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 13.199 ; 12.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 13.591 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 13.591 ; 12.868 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 12.339 ; 12.122 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 13.741 ; 12.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 13.734 ; 12.882 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 12.540 ; 12.184 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 12.502 ; 12.619 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 12.502 ; 12.619 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 12.467 ; 12.583 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ @@ -535,61 +611,123 @@ No paths to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 11.043 ; 10.875 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 12.584 ; 11.944 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 11.043 ; 10.875 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 11.654 ; 11.295 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 11.937 ; 11.501 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 11.548 ; 11.212 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 11.903 ; 11.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 11.989 ; 11.538 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 10.855 ; 10.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 12.965 ; 12.214 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 12.519 ; 11.939 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 12.535 ; 11.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 12.139 ; 11.596 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 10.855 ; 10.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 11.894 ; 11.480 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 12.595 ; 11.926 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 11.251 ; 10.993 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 12.772 ; 12.051 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 11.604 ; 11.202 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 11.558 ; 11.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 11.681 ; 11.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 11.569 ; 11.167 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 11.251 ; 10.993 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 11.682 ; 11.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 11.313 ; 11.040 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 11.867 ; 11.390 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 11.353 ; 11.040 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 11.313 ; 11.115 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 13.632 ; 12.704 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 11.777 ; 11.342 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 12.078 ; 11.613 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 11.673 ; 11.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 11.020 ; 10.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 11.200 ; 10.986 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 11.790 ; 11.336 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 12.588 ; 11.934 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 12.462 ; 11.843 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 11.400 ; 11.148 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 12.062 ; 11.531 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 11.020 ; 10.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 10.504 ; 10.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 11.932 ; 11.417 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 11.236 ; 10.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 10.504 ; 10.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 11.180 ; 10.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 11.145 ; 10.970 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 10.699 ; 10.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 11.979 ; 11.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 11.294 ; 11.028 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 12.204 ; 11.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 11.509 ; 11.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 11.711 ; 11.299 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 12.135 ; 11.666 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 11.979 ; 11.466 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 11.294 ; 11.028 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 12.384 ; 11.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 10.569 ; 10.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 12.299 ; 11.713 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 10.953 ; 10.778 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 10.569 ; 10.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 11.316 ; 11.019 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 11.563 ; 11.168 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 11.584 ; 11.176 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 11.106 ; 10.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 11.106 ; 10.914 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 11.803 ; 11.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 12.160 ; 11.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 11.106 ; 10.914 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 11.149 ; 10.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 11.705 ; 11.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 11.725 ; 11.308 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 12.281 ; 11.684 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 11.198 ; 10.920 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 11.198 ; 10.920 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 11.328 ; 10.990 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 11.962 ; 11.483 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 11.900 ; 11.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 11.854 ; 11.381 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 11.833 ; 11.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 11.224 ; 10.947 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 10.953 ; 10.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 11.582 ; 11.195 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 11.814 ; 11.348 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 11.568 ; 11.160 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 12.126 ; 11.585 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 11.139 ; 10.898 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 10.989 ; 10.814 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 10.953 ; 10.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 11.126 ; 10.988 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 11.686 ; 11.277 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 12.006 ; 11.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 12.050 ; 11.575 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 11.126 ; 10.988 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 12.183 ; 11.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 12.145 ; 11.586 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 11.318 ; 11.058 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 10.411 ; 10.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 10.448 ; 10.545 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 10.411 ; 10.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ---------------------------------------------- -; Slow 1100mV 0C Model Metastability Report ; ---------------------------------------------- -No synchronizer chains to report. +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 17.571 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; GPIO[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO[7] ; +; Synchronization Node ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 17.571 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.075 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.496 ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + +----------------------------------------------------------------------------------------------------+ @@ -597,7 +735,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.113 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.503 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -606,7 +744,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.163 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.154 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -628,113 +766,116 @@ No paths to report. ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.889 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.888 ; 0.000 ; ; CLOCK_50 ; 9.336 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.528 ; 1.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.528 ; 1.626 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.435 ; 1.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.395 ; 1.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.439 ; 1.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 1.507 ; 2.852 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.329 ; 0.796 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.338 ; 1.504 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.119 ; 1.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.200 ; 1.570 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 0.058 ; 1.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.306 ; 0.687 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 0.505 ; 1.707 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 1.180 ; 2.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 0.581 ; 1.871 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 1.507 ; 2.852 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 2.296 ; 1.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 1.836 ; 0.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 1.807 ; 0.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 2.095 ; 1.189 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 2.296 ; 1.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 1.854 ; 0.915 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 1.250 ; 0.246 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.712 ; -0.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 1.529 ; 0.579 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 1.267 ; 0.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 1.586 ; 0.679 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 1.451 ; 0.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 1.505 ; 0.527 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 1.694 ; 0.736 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 1.639 ; 0.710 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 1.854 ; 0.915 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 9.066 ; 8.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 9.066 ; 8.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 7.579 ; 7.326 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 8.077 ; 7.640 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 8.313 ; 7.803 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 8.021 ; 7.593 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 8.475 ; 7.871 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 8.569 ; 7.932 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 9.398 ; 8.457 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 9.398 ; 8.457 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 8.901 ; 8.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 9.008 ; 8.156 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 8.746 ; 8.001 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 7.379 ; 7.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 8.397 ; 7.855 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 9.069 ; 8.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 9.268 ; 8.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 9.268 ; 8.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 8.269 ; 7.674 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 8.248 ; 7.661 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 8.306 ; 7.712 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 8.201 ; 7.630 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 7.861 ; 7.475 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 8.320 ; 7.718 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 10.029 ; 8.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 8.507 ; 7.852 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 7.987 ; 7.570 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 7.846 ; 7.543 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 10.029 ; 8.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 8.417 ; 7.779 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 8.566 ; 7.972 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 8.144 ; 7.689 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 9.134 ; 8.285 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 7.753 ; 7.435 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 8.425 ; 7.786 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 9.134 ; 8.285 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 9.022 ; 8.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 7.926 ; 7.591 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 8.681 ; 7.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 7.564 ; 7.339 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 8.532 ; 7.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 8.532 ; 7.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 7.856 ; 7.463 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 7.175 ; 7.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 7.805 ; 7.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 7.679 ; 7.414 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 7.338 ; 7.104 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 8.370 ; 7.827 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 0.692 ; 2.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.464 ; 1.837 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 0.692 ; 2.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.037 ; 1.200 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.145 ; 1.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 1.719 ; 3.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.339 ; 1.060 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.452 ; 0.600 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -0.605 ; 0.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.373 ; 0.897 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; -0.021 ; 1.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.060 ; -0.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.487 ; 1.358 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 1.719 ; 3.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 0.986 ; 2.118 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 0.864 ; 2.176 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 2.443 ; 1.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 1.878 ; 0.901 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 1.722 ; 0.631 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 2.001 ; 1.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 2.443 ; 1.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.083 ; 1.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.781 ; 0.016 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 1.352 ; 0.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 1.693 ; 0.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 1.821 ; 0.909 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 1.684 ; 0.801 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 2.083 ; 1.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 1.499 ; 0.536 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 1.689 ; 0.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.846 ; 0.908 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.921 ; 0.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; HEX0[*] ; CLOCK_50 ; 8.963 ; 8.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 8.774 ; 8.038 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 8.038 ; 7.547 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 8.213 ; 7.680 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 8.510 ; 7.943 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 8.604 ; 7.891 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 7.795 ; 7.441 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 8.963 ; 8.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 8.830 ; 8.062 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 8.830 ; 8.062 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 7.520 ; 7.281 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 7.183 ; 7.067 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 8.034 ; 7.547 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 8.211 ; 7.628 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 8.222 ; 7.645 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 7.666 ; 7.468 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 8.818 ; 8.043 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 8.414 ; 7.834 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 8.726 ; 7.989 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 7.631 ; 7.371 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 7.716 ; 7.434 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 8.192 ; 7.738 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 8.385 ; 7.763 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 8.818 ; 8.043 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 8.516 ; 7.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 7.959 ; 7.496 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 8.090 ; 7.575 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 8.516 ; 7.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 8.404 ; 7.901 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 8.423 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 8.452 ; 7.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 7.795 ; 7.442 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 8.761 ; 8.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 8.176 ; 7.663 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 8.521 ; 7.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 8.253 ; 7.670 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 8.761 ; 8.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 7.808 ; 7.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 7.635 ; 7.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 7.586 ; 7.331 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 8.793 ; 8.026 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 8.388 ; 7.773 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 8.657 ; 7.930 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 8.658 ; 8.001 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 7.697 ; 7.485 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 8.776 ; 8.019 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 8.793 ; 8.026 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 7.831 ; 7.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 7.522 ; 7.658 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 7.522 ; 7.658 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 7.508 ; 7.634 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -742,61 +883,123 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 6.913 ; 6.715 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 8.097 ; 7.500 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 6.913 ; 6.715 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 7.368 ; 7.005 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 7.606 ; 7.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 7.316 ; 6.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 7.554 ; 7.151 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 7.645 ; 7.214 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 6.751 ; 6.603 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 8.391 ; 7.694 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 8.055 ; 7.493 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 8.052 ; 7.425 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 7.799 ; 7.278 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 6.751 ; 6.603 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 7.560 ; 7.168 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 8.075 ; 7.469 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 7.095 ; 6.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 8.296 ; 7.623 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 7.361 ; 6.971 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 7.344 ; 6.961 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 7.407 ; 7.005 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 7.315 ; 6.937 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 7.095 ; 6.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 7.427 ; 7.024 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 7.137 ; 6.909 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 7.596 ; 7.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 7.216 ; 6.920 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 7.137 ; 6.909 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 8.976 ; 8.098 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 7.500 ; 7.076 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 7.717 ; 7.277 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 7.419 ; 7.057 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 6.912 ; 6.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 7.049 ; 6.805 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 7.505 ; 7.079 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 8.168 ; 7.545 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 8.058 ; 7.481 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 7.216 ; 6.956 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 7.740 ; 7.243 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 6.912 ; 6.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 6.557 ; 6.447 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 7.625 ; 7.149 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 7.091 ; 6.822 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 6.557 ; 6.447 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 7.041 ; 6.776 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 7.009 ; 6.801 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 6.694 ; 6.515 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 7.610 ; 7.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 7.076 ; 6.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 7.807 ; 7.305 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 7.246 ; 6.893 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 7.419 ; 7.024 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 7.744 ; 7.282 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 7.644 ; 7.162 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 7.076 ; 6.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 7.979 ; 7.421 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 6.562 ; 6.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 7.870 ; 7.329 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 6.868 ; 6.686 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 6.562 ; 6.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 7.159 ; 6.860 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 7.314 ; 6.932 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 7.332 ; 6.952 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 6.982 ; 6.841 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 6.969 ; 6.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 7.558 ; 7.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 7.784 ; 7.269 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 6.969 ; 6.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 7.018 ; 6.813 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 7.422 ; 7.075 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 7.475 ; 7.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 7.849 ; 7.308 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 7.095 ; 6.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 7.095 ; 6.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 7.198 ; 6.883 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 7.669 ; 7.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 7.634 ; 7.235 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 7.524 ; 7.079 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 7.550 ; 7.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 7.108 ; 6.833 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 6.901 ; 6.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 7.360 ; 6.996 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 7.572 ; 7.128 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 7.355 ; 6.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 7.809 ; 7.295 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 7.024 ; 6.779 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 6.925 ; 6.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 6.901 ; 6.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 7.009 ; 6.856 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 7.473 ; 7.071 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 7.678 ; 7.189 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 7.718 ; 7.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 7.009 ; 6.856 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 7.835 ; 7.301 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 7.822 ; 7.292 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 7.132 ; 6.865 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 6.378 ; 6.474 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 6.396 ; 6.507 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 6.378 ; 6.474 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ----------------------------------------------- -; Fast 1100mV 85C Model Metastability Report ; ----------------------------------------------- -No synchronizer chains to report. +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 18.511 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; GPIO[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO[7] ; +; Synchronization Node ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.511 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.479 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.032 ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + +----------------------------------------------------------------------------------------------------+ @@ -804,7 +1007,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.512 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.812 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -813,7 +1016,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.147 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.141 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ @@ -835,57 +1038,57 @@ No paths to report. ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------------------------+-------+---------------+ ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.889 ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.888 ; 0.000 ; ; CLOCK_50 ; 9.286 ; 0.000 ; +----------------------------------------------------------------------------+-------+---------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.358 ; 1.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.358 ; 1.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.224 ; 1.352 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.218 ; 1.080 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.232 ; 1.452 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 1.251 ; 2.616 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.493 ; 0.677 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.158 ; 1.348 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.236 ; 1.107 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.096 ; 1.456 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; -0.124 ; 1.046 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.447 ; 0.600 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 0.313 ; 1.552 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 0.958 ; 2.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 0.364 ; 1.670 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 1.251 ; 2.616 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 2.324 ; 1.403 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 1.863 ; 0.839 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 1.856 ; 0.833 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 2.119 ; 1.175 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 2.324 ; 1.403 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 1.903 ; 0.919 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 1.368 ; 0.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.814 ; -0.244 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 1.581 ; 0.596 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 1.300 ; 0.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 1.670 ; 0.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 1.545 ; 0.529 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 1.590 ; 0.571 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 1.737 ; 0.742 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 1.746 ; 0.758 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 1.903 ; 0.919 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+-------+--------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 0.539 ; 2.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.338 ; 1.679 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 0.539 ; 2.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.167 ; 1.103 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.291 ; 1.104 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 1.447 ; 3.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.193 ; 0.984 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.563 ; 0.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -0.671 ; 0.548 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.456 ; 0.823 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; -0.154 ; 1.118 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.126 ; -0.193 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.332 ; 1.250 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 1.447 ; 3.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 0.755 ; 1.924 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 0.643 ; 1.975 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 2.428 ; 1.516 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 1.868 ; 0.876 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 1.733 ; 0.631 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 1.997 ; 0.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 2.428 ; 1.516 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.105 ; 1.207 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.858 ; 0.041 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 1.411 ; 0.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 1.696 ; 0.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 1.844 ; 0.898 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 1.735 ; 0.799 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 2.105 ; 1.207 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 1.529 ; 0.529 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 1.691 ; 0.712 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.898 ; 0.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.951 ; 0.959 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -893,54 +1096,57 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 8.559 ; 7.863 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 8.559 ; 7.863 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 7.125 ; 6.894 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 7.596 ; 7.215 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 7.830 ; 7.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 7.543 ; 7.173 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 7.987 ; 7.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 8.029 ; 7.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 8.872 ; 8.078 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 8.872 ; 8.078 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 8.387 ; 7.796 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 8.503 ; 7.787 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 8.251 ; 7.625 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 6.941 ; 6.762 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 7.908 ; 7.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 8.520 ; 7.800 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 8.728 ; 7.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 8.728 ; 7.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 7.812 ; 7.313 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 7.778 ; 7.289 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 7.840 ; 7.340 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 7.743 ; 7.268 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 7.401 ; 7.070 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 7.848 ; 7.346 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 9.456 ; 8.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 8.000 ; 7.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 7.513 ; 7.153 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 7.334 ; 7.050 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 9.456 ; 8.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 7.957 ; 7.420 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 8.055 ; 7.547 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 7.620 ; 7.223 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 8.610 ; 7.891 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 7.267 ; 6.980 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 7.903 ; 7.363 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 8.610 ; 7.891 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 8.497 ; 7.816 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 7.453 ; 7.154 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 8.167 ; 7.563 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 7.087 ; 6.880 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 8.033 ; 7.466 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 8.033 ; 7.466 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 7.398 ; 7.062 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 6.748 ; 6.610 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 7.334 ; 7.001 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 7.183 ; 6.936 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 6.895 ; 6.690 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 7.868 ; 7.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 8.459 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 8.289 ; 7.667 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 7.574 ; 7.154 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 7.728 ; 7.276 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 8.034 ; 7.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 8.116 ; 7.518 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 7.353 ; 7.044 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 8.459 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 8.329 ; 7.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 8.329 ; 7.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 7.063 ; 6.844 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 6.786 ; 6.678 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 7.590 ; 7.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 7.757 ; 7.268 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 7.747 ; 7.262 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 7.206 ; 7.013 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 8.305 ; 7.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 7.930 ; 7.432 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 8.242 ; 7.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 7.166 ; 6.926 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 7.294 ; 7.042 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 7.730 ; 7.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 7.911 ; 7.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 8.305 ; 7.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 8.007 ; 7.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 7.502 ; 7.117 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 7.631 ; 7.194 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 8.007 ; 7.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 7.921 ; 7.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 7.944 ; 7.405 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 7.954 ; 7.411 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 7.324 ; 7.014 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 8.258 ; 7.636 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 7.697 ; 7.257 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 8.037 ; 7.469 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 7.772 ; 7.278 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 8.258 ; 7.636 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 7.344 ; 7.017 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 7.193 ; 6.953 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 7.145 ; 6.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 8.289 ; 7.647 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 7.905 ; 7.387 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 8.167 ; 7.552 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 8.153 ; 7.592 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 7.224 ; 7.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 8.278 ; 7.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 8.289 ; 7.647 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 7.393 ; 7.091 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 7.159 ; 7.266 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 7.159 ; 7.266 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 7.141 ; 7.244 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -949,61 +1155,123 @@ No paths to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 6.503 ; 6.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 7.656 ; 7.159 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 6.503 ; 6.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 6.938 ; 6.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 7.170 ; 6.798 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 6.891 ; 6.589 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 7.131 ; 6.795 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 7.170 ; 6.810 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 6.355 ; 6.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 7.931 ; 7.354 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 7.592 ; 7.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 7.613 ; 7.095 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 7.371 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 6.355 ; 6.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 7.142 ; 6.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 7.601 ; 7.088 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 6.700 ; 6.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 7.825 ; 7.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 6.974 ; 6.650 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 6.945 ; 6.628 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 7.011 ; 6.676 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 6.930 ; 6.615 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 6.700 ; 6.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 7.027 ; 6.690 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 6.669 ; 6.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 7.166 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 6.803 ; 6.544 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 6.669 ; 6.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 8.464 ; 7.738 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 7.108 ; 6.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 7.266 ; 6.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 6.949 ; 6.633 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 6.480 ; 6.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 6.610 ; 6.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 7.056 ; 6.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 7.708 ; 7.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 7.598 ; 7.116 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 6.796 ; 6.560 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 7.301 ; 6.879 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 6.480 ; 6.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 6.175 ; 6.074 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 7.197 ; 6.799 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 6.698 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 6.175 ; 6.074 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 6.639 ; 6.405 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 6.555 ; 6.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 6.298 ; 6.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 7.160 ; 6.785 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 7.398 ; 6.973 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 6.848 ; 6.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 7.003 ; 6.660 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 7.320 ; 6.923 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 7.230 ; 6.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 7.543 ; 7.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 7.449 ; 6.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 6.460 ; 6.290 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 6.782 ; 6.534 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 6.930 ; 6.612 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 6.938 ; 6.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 6.566 ; 6.430 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 7.134 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 7.369 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 6.644 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 7.014 ; 6.709 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 7.070 ; 6.731 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 7.408 ; 6.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 6.706 ; 6.472 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 6.807 ; 6.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 7.230 ; 6.845 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 7.198 ; 6.857 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 7.123 ; 6.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 7.125 ; 6.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 6.949 ; 6.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 7.158 ; 6.787 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 6.943 ; 6.617 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 7.374 ; 6.948 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 6.627 ; 6.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 6.533 ; 6.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 7.059 ; 6.723 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 7.263 ; 6.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 7.287 ; 6.903 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 7.404 ; 6.962 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 7.388 ; 6.951 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 6.741 ; 6.509 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 6.068 ; 6.158 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ---------------------------------------------- -; Fast 1100mV 0C Model Metastability Report ; ---------------------------------------------- -No synchronizer chains to report. +---------------- +; MTBF Summary ; +---------------- +Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 18.610 ns + +Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2 +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Worst-Case MTBF (Years) ; Typical MTBF (Years) ; Included in Design MTBF ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ +; GPIO[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Greater than 1 Billion ; Yes ; ++-------------+---------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO[7] ; +; Synchronization Node ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.610 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO[7] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.504 ; +; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.106 ; ++-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + +-------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1011,39 +1279,39 @@ No synchronizer chains to report. +-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+ -; Worst-case Slack ; -1.885 ; 0.147 ; N/A ; N/A ; 1.666 ; +; Worst-case Slack ; -1.352 ; 0.141 ; N/A ; N/A ; 1.666 ; ; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 9.286 ; ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.666 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.885 ; 0.147 ; N/A ; N/A ; 3.753 ; -; Design-wide TNS ; -158.135 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.352 ; 0.141 ; N/A ; N/A ; 3.758 ; +; Design-wide TNS ; -121.67 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ; -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -158.135 ; 0.000 ; N/A ; N/A ; 0.000 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -121.670 ; 0.000 ; N/A ; N/A ; 0.000 ; +-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 0.848 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 0.848 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 0.800 ; 1.535 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 0.537 ; 1.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 0.698 ; 1.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 2.301 ; 3.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; -0.329 ; 0.796 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 0.707 ; 1.571 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; -0.119 ; 1.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 0.380 ; 1.570 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 0.163 ; 1.178 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; -0.306 ; 0.687 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 1.129 ; 2.049 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 2.286 ; 3.285 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 1.216 ; 2.080 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 2.301 ; 3.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -+-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +; KEY[*] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 0.834 ; 1.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; -0.037 ; 1.200 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; -0.145 ; 1.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 0.534 ; 1.060 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; -0.452 ; 0.600 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; -0.605 ; 0.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; -0.373 ; 0.897 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 0.128 ; 1.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; -1.060 ; -0.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 0.963 ; 1.365 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 1.752 ; 2.499 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 1.529 ; 2.464 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ++-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------+ @@ -1051,22 +1319,22 @@ No synchronizer chains to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; KEY[*] ; CLOCK_50 ; 4.197 ; 3.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[0] ; CLOCK_50 ; 3.311 ; 2.588 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[1] ; CLOCK_50 ; 3.283 ; 2.577 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[2] ; CLOCK_50 ; 3.831 ; 3.218 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; KEY[3] ; CLOCK_50 ; 4.197 ; 3.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[*] ; CLOCK_50 ; 3.341 ; 2.720 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[0] ; CLOCK_50 ; 2.465 ; 1.724 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[1] ; CLOCK_50 ; 1.393 ; 0.663 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[2] ; CLOCK_50 ; 2.898 ; 2.280 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[3] ; CLOCK_50 ; 2.472 ; 1.701 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[4] ; CLOCK_50 ; 3.051 ; 2.517 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[5] ; CLOCK_50 ; 2.728 ; 2.072 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[6] ; CLOCK_50 ; 2.934 ; 2.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[7] ; CLOCK_50 ; 3.061 ; 2.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[8] ; CLOCK_50 ; 3.081 ; 2.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; SW[9] ; CLOCK_50 ; 3.341 ; 2.720 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[*] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[0] ; CLOCK_50 ; 3.381 ; 2.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[1] ; CLOCK_50 ; 3.217 ; 2.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[2] ; CLOCK_50 ; 3.644 ; 2.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; KEY[3] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[*] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[0] ; CLOCK_50 ; 1.617 ; 1.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[1] ; CLOCK_50 ; 2.455 ; 1.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[2] ; CLOCK_50 ; 3.152 ; 2.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[3] ; CLOCK_50 ; 3.415 ; 2.830 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[4] ; CLOCK_50 ; 3.069 ; 2.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[5] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[6] ; CLOCK_50 ; 2.788 ; 2.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[7] ; CLOCK_50 ; 3.171 ; 2.543 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[8] ; CLOCK_50 ; 3.327 ; 2.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; SW[9] ; CLOCK_50 ; 3.589 ; 2.995 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -1075,54 +1343,57 @@ No synchronizer chains to report. +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 14.397 ; 13.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 14.397 ; 13.497 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 12.554 ; 12.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 13.186 ; 12.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 13.466 ; 12.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 13.073 ; 12.669 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 13.697 ; 13.039 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 13.855 ; 13.136 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 14.821 ; 13.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 14.821 ; 13.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 14.193 ; 13.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 14.321 ; 13.382 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 13.918 ; 13.105 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 12.323 ; 12.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 13.546 ; 12.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 14.493 ; 13.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 14.577 ; 13.594 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 14.577 ; 13.594 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 13.334 ; 12.689 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 13.293 ; 12.654 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 13.415 ; 12.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 13.271 ; 12.652 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 12.836 ; 12.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 13.395 ; 12.746 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 15.528 ; 14.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 13.620 ; 12.915 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 12.933 ; 12.507 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 12.936 ; 12.659 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 15.528 ; 14.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 13.518 ; 12.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 13.765 ; 13.151 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 13.270 ; 12.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 14.396 ; 13.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 12.762 ; 12.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 13.611 ; 12.890 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 14.396 ; 13.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 14.278 ; 13.400 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 12.923 ; 12.634 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 13.863 ; 13.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 12.517 ; 12.337 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 13.665 ; 13.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 13.665 ; 12.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 12.819 ; 12.431 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 11.916 ; 11.815 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 12.759 ; 12.363 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 12.719 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 12.148 ; 11.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 13.601 ; 13.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 14.002 ; 13.202 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 13.120 ; 12.618 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 13.313 ; 12.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 13.693 ; 13.119 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 13.759 ; 12.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 12.800 ; 12.470 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 12.430 ; 12.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 11.957 ; 11.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 12.990 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 13.273 ; 12.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 13.295 ; 12.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 12.618 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 13.457 ; 12.840 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 13.921 ; 13.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 12.588 ; 12.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 12.623 ; 12.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 13.284 ; 12.846 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 13.455 ; 12.789 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 12.868 ; 12.384 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 13.020 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 13.452 ; 12.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 13.575 ; 12.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 13.547 ; 12.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 12.700 ; 12.379 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 13.197 ; 12.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 13.581 ; 12.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 13.297 ; 12.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 12.741 ; 12.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 12.477 ; 12.232 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 12.414 ; 12.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 13.948 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 13.425 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 13.810 ; 13.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 13.826 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 12.646 ; 12.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 13.948 ; 13.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 13.937 ; 13.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 12.793 ; 12.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 12.782 ; 12.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+ @@ -1131,54 +1402,57 @@ No synchronizer chains to report. +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ -; HEX0[*] ; CLOCK_50 ; 6.503 ; 6.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[0] ; CLOCK_50 ; 7.656 ; 7.159 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[1] ; CLOCK_50 ; 6.503 ; 6.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[2] ; CLOCK_50 ; 6.938 ; 6.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[3] ; CLOCK_50 ; 7.170 ; 6.798 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[4] ; CLOCK_50 ; 6.891 ; 6.589 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[5] ; CLOCK_50 ; 7.131 ; 6.795 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX0[6] ; CLOCK_50 ; 7.170 ; 6.810 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[*] ; CLOCK_50 ; 6.355 ; 6.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[0] ; CLOCK_50 ; 7.931 ; 7.354 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[1] ; CLOCK_50 ; 7.592 ; 7.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[2] ; CLOCK_50 ; 7.613 ; 7.095 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[3] ; CLOCK_50 ; 7.371 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[4] ; CLOCK_50 ; 6.355 ; 6.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[5] ; CLOCK_50 ; 7.142 ; 6.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX1[6] ; CLOCK_50 ; 7.601 ; 7.088 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[*] ; CLOCK_50 ; 6.700 ; 6.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[0] ; CLOCK_50 ; 7.825 ; 7.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[1] ; CLOCK_50 ; 6.974 ; 6.650 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[2] ; CLOCK_50 ; 6.945 ; 6.628 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[3] ; CLOCK_50 ; 7.011 ; 6.676 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[4] ; CLOCK_50 ; 6.930 ; 6.615 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[5] ; CLOCK_50 ; 6.700 ; 6.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX2[6] ; CLOCK_50 ; 7.027 ; 6.690 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[*] ; CLOCK_50 ; 6.669 ; 6.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[0] ; CLOCK_50 ; 7.166 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[1] ; CLOCK_50 ; 6.803 ; 6.544 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[2] ; CLOCK_50 ; 6.669 ; 6.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[3] ; CLOCK_50 ; 8.464 ; 7.738 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[4] ; CLOCK_50 ; 7.108 ; 6.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[5] ; CLOCK_50 ; 7.266 ; 6.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX3[6] ; CLOCK_50 ; 6.949 ; 6.633 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[*] ; CLOCK_50 ; 6.480 ; 6.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[0] ; CLOCK_50 ; 6.610 ; 6.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[1] ; CLOCK_50 ; 7.056 ; 6.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[2] ; CLOCK_50 ; 7.708 ; 7.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[3] ; CLOCK_50 ; 7.598 ; 7.116 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[4] ; CLOCK_50 ; 6.796 ; 6.560 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[5] ; CLOCK_50 ; 7.301 ; 6.879 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX4[6] ; CLOCK_50 ; 6.480 ; 6.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[*] ; CLOCK_50 ; 6.175 ; 6.074 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[0] ; CLOCK_50 ; 7.197 ; 6.799 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[1] ; CLOCK_50 ; 6.698 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[2] ; CLOCK_50 ; 6.175 ; 6.074 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[3] ; CLOCK_50 ; 6.639 ; 6.405 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[4] ; CLOCK_50 ; 6.555 ; 6.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[5] ; CLOCK_50 ; 6.298 ; 6.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -; HEX5[6] ; CLOCK_50 ; 7.160 ; 6.785 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[*] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[0] ; CLOCK_50 ; 7.398 ; 6.973 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[1] ; CLOCK_50 ; 6.848 ; 6.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[2] ; CLOCK_50 ; 7.003 ; 6.660 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[3] ; CLOCK_50 ; 7.320 ; 6.923 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[4] ; CLOCK_50 ; 7.230 ; 6.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[5] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX0[6] ; CLOCK_50 ; 7.543 ; 7.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[*] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[0] ; CLOCK_50 ; 7.449 ; 6.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[1] ; CLOCK_50 ; 6.460 ; 6.290 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[2] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[3] ; CLOCK_50 ; 6.782 ; 6.534 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[4] ; CLOCK_50 ; 6.930 ; 6.612 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[5] ; CLOCK_50 ; 6.938 ; 6.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX1[6] ; CLOCK_50 ; 6.566 ; 6.430 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[*] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[0] ; CLOCK_50 ; 7.134 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[1] ; CLOCK_50 ; 7.369 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[2] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[3] ; CLOCK_50 ; 6.644 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[4] ; CLOCK_50 ; 7.014 ; 6.709 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[5] ; CLOCK_50 ; 7.070 ; 6.731 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX2[6] ; CLOCK_50 ; 7.408 ; 6.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[*] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[0] ; CLOCK_50 ; 6.706 ; 6.472 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[1] ; CLOCK_50 ; 6.807 ; 6.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[2] ; CLOCK_50 ; 7.230 ; 6.845 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[3] ; CLOCK_50 ; 7.198 ; 6.857 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[4] ; CLOCK_50 ; 7.123 ; 6.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[5] ; CLOCK_50 ; 7.125 ; 6.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX3[6] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[*] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[0] ; CLOCK_50 ; 6.949 ; 6.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[1] ; CLOCK_50 ; 7.158 ; 6.787 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[2] ; CLOCK_50 ; 6.943 ; 6.617 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[3] ; CLOCK_50 ; 7.374 ; 6.948 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[4] ; CLOCK_50 ; 6.627 ; 6.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[5] ; CLOCK_50 ; 6.533 ; 6.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX4[6] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[*] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[0] ; CLOCK_50 ; 7.059 ; 6.723 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[1] ; CLOCK_50 ; 7.263 ; 6.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[2] ; CLOCK_50 ; 7.287 ; 6.903 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[3] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[4] ; CLOCK_50 ; 7.404 ; 6.962 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[5] ; CLOCK_50 ; 7.388 ; 6.951 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; HEX5[6] ; CLOCK_50 ; 6.741 ; 6.509 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[*] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[0] ; CLOCK_50 ; 6.068 ; 6.158 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +; LEDR[2] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; +-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+ @@ -1328,9 +1602,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; GPIO[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; GPIO[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; @@ -1359,6 +1631,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[34] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO[35] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ @@ -1413,9 +1687,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; GPIO[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; GPIO[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; @@ -1444,6 +1716,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[34] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO[35] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; GPIO[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; KEY[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; @@ -1608,9 +1882,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; ; GPIO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; ; GPIO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; -; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; ; GPIO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; -; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; ; GPIO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; @@ -1639,6 +1911,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; ; GPIO[34] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[35] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; +; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -1788,9 +2062,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; ; GPIO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; ; GPIO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; -; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; ; GPIO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; -; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ; GPIO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; ; GPIO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ; GPIO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; @@ -1819,6 +2091,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; ; GPIO[34] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; ; GPIO[35] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; +; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; +; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -1968,9 +2242,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; ; GPIO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; -; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; -; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ; GPIO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; ; GPIO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ; GPIO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; @@ -1999,6 +2271,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; ; GPIO[34] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; ; GPIO[35] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; +; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -2148,9 +2422,7 @@ No synchronizer chains to report. ; GPIO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; ; GPIO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; ; GPIO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; -; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; ; GPIO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; -; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ; GPIO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; ; GPIO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ; GPIO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; @@ -2179,6 +2451,8 @@ No synchronizer chains to report. ; GPIO[33] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; ; GPIO[34] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; ; GPIO[35] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +; GPIO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; +; GPIO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -2187,7 +2461,7 @@ No synchronizer chains to report. +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 49532597 ; 0 ; 0 ; 0 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 47863402 ; 0 ; 0 ; 0 ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -2197,7 +2471,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ -; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 49532597 ; 0 ; 0 ; 0 ; +; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 47863402 ; 0 ; 0 ; 0 ; +----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -2222,9 +2496,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 14 ; 14 ; -; Unconstrained Input Port Paths ; 323 ; 323 ; -; Unconstrained Output Ports ; 42 ; 42 ; -; Unconstrained Output Port Paths ; 42 ; 42 ; +; Unconstrained Input Port Paths ; 351 ; 351 ; +; Unconstrained Output Ports ; 44 ; 44 ; +; Unconstrained Output Port Paths ; 44 ; 44 ; +---------------------------------+-------+------+ @@ -2238,12 +2512,15 @@ Warning (125092): Tcl Script File alu/add_sub_s.qip not found Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Fri Aug 27 17:23:29 2021 + Info: Processing started: Sat Aug 28 10:56:13 2021 Info: Command: quartus_sta de1_riscv -c de1_riscv Info: qsta_default_script.tcl version: #1 Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332104): Reading SDC File: 'de1_riscv.SDC' Warning (332049): Ignored create_clock at de1_riscv.sdc(20): Time value "1.536 MH" is not valid Info (332050): create_clock -period "1.536 MH" -name clk_audbck [get_ports AUD_BCLK] @@ -2386,14 +2663,14 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1100mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.729 +Info (332146): Worst-case setup slack is -1.197 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.729 -126.223 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk -Info (332146): Worst-case hold slack is 0.281 + Info (332119): -1.197 -95.783 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk +Info (332146): Worst-case hold slack is 0.266 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.281 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 0.266 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.666 @@ -2402,6 +2679,19 @@ Info (332146): Worst-case minimum pulse width slack is 1.666 Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332119): 3.775 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.670 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 17.536 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 Info: Analyzing Slow 1100mV 0C Model Info (334003): Started post-fitting delay annotation Warning (334000): Timing characteristics of device 5CSEMA5F31C6 are preliminary @@ -2517,22 +2807,35 @@ Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQue Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.885 +Info (332146): Worst-case setup slack is -1.352 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.885 -158.135 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk -Info (332146): Worst-case hold slack is 0.260 + Info (332119): -1.352 -121.670 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk +Info (332146): Worst-case hold slack is 0.247 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.260 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 0.247 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] - Info (332119): 3.753 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 3.758 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.673 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 17.571 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 Info: Analyzing Fast 1100mV 85C Model Info (334003): Started post-fitting delay annotation Warning (334000): Timing characteristics of device 5CSEMA5F31C6 are preliminary @@ -2646,22 +2949,35 @@ Info (332097): The following timing edges are non-unate. TimeQuest will assume Info (332098): From: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0CLKMUX_0 to: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0MEMORYREGOUT Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment. -Info (332146): Worst-case setup slack is 3.113 +Info (332146): Worst-case setup slack is 3.503 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.113 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk -Info (332146): Worst-case hold slack is 0.163 + Info (332119): 3.503 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk +Info (332146): Worst-case hold slack is 0.154 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.163 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 0.154 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] - Info (332119): 3.889 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 3.888 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.336 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 18.511 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 Info: Analyzing Fast 1100mV 0C Model Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk @@ -2772,27 +3088,40 @@ Info (332097): The following timing edges are non-unate. TimeQuest will assume Info (332098): From: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0CLKMUX_0 to: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0MEMORYREGOUT Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment. -Info (332146): Worst-case setup slack is 3.512 +Info (332146): Worst-case setup slack is 3.812 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.512 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk -Info (332146): Worst-case hold slack is 0.147 + Info (332119): 3.812 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk +Info (332146): Worst-case hold slack is 0.141 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.147 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 0.141 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] - Info (332119): 3.889 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + Info (332119): 3.888 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.286 0.000 CLOCK_50 +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 18.610 ns + Info (332114): + Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. + Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2 + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 27 warnings - Info: Peak virtual memory: 1135 megabytes - Info: Processing ended: Fri Aug 27 17:24:01 2021 + Info: Peak virtual memory: 1136 megabytes + Info: Processing ended: Sat Aug 28 10:56:45 2021 Info: Elapsed time: 00:00:32 Info: Total CPU time (on all processors): 00:00:42 diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sta.summary b/examples/hdl4se_riscv/de1/de1_riscv.sta.summary index b3f81d6b9ac0ee130a2943f2b913274e3168ff81..f5e166bb9a68cf5b31d0993865190969c79f07fb 100644 --- a/examples/hdl4se_riscv/de1/de1_riscv.sta.summary +++ b/examples/hdl4se_riscv/de1/de1_riscv.sta.summary @@ -3,11 +3,11 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : -1.729 -TNS : -126.223 +Slack : -1.197 +TNS : -95.783 Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 0.281 +Slack : 0.266 TNS : 0.000 Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]' @@ -23,11 +23,11 @@ Slack : 9.670 TNS : 0.000 Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : -1.885 -TNS : -158.135 +Slack : -1.352 +TNS : -121.670 Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 0.260 +Slack : 0.247 TNS : 0.000 Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]' @@ -35,7 +35,7 @@ Slack : 1.666 TNS : 0.000 Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.753 +Slack : 3.758 TNS : 0.000 Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50' @@ -43,11 +43,11 @@ Slack : 9.673 TNS : 0.000 Type : Fast 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.113 +Slack : 3.503 TNS : 0.000 Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 0.163 +Slack : 0.154 TNS : 0.000 Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]' @@ -55,7 +55,7 @@ Slack : 1.666 TNS : 0.000 Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.889 +Slack : 3.888 TNS : 0.000 Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50' @@ -63,11 +63,11 @@ Slack : 9.336 TNS : 0.000 Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.512 +Slack : 3.812 TNS : 0.000 Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 0.147 +Slack : 0.141 TNS : 0.000 Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]' @@ -75,7 +75,7 @@ Slack : 1.666 TNS : 0.000 Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk' -Slack : 3.889 +Slack : 3.888 TNS : 0.000 Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50' diff --git a/examples/hdl4se_riscv/de1/de1_riscv_v2.v b/examples/hdl4se_riscv/de1/de1_riscv_v2.v new file mode 100644 index 0000000000000000000000000000000000000000..901b54b3f0da88eb758c73b43bd1a264ae7bfe18 --- /dev/null +++ b/examples/hdl4se_riscv/de1/de1_riscv_v2.v @@ -0,0 +1,235 @@ + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= + +`define USECLOCK50_1 + +module de1_riscv( + + //////////// ADC ////////// + output ADC_CONVST, + output ADC_DIN, + input ADC_DOUT, + output ADC_SCLK, + + //////////// Audio ////////// + input AUD_ADCDAT, + inout AUD_ADCLRCK, + inout AUD_BCLK, + output AUD_DACDAT, + inout AUD_DACLRCK, + output AUD_XCK, + + //////////// CLOCK ////////// + input CLOCK2_50, + input CLOCK3_50, + input CLOCK4_50, + input CLOCK_50, + + //////////// SDRAM ////////// + output [12:0] DRAM_ADDR, + output [1:0] DRAM_BA, + output DRAM_CAS_N, + output DRAM_CKE, + output DRAM_CLK, + output DRAM_CS_N, + inout [15:0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_RAS_N, + output DRAM_UDQM, + output DRAM_WE_N, + + //////////// I2C for Audio and Video-In ////////// + output FPGA_I2C_SCLK, + inout FPGA_I2C_SDAT, + + //////////// SEG7 ////////// + output [6:0] HEX0, + output [6:0] HEX1, + output [6:0] HEX2, + output [6:0] HEX3, + output [6:0] HEX4, + output [6:0] HEX5, + + //////////// IR ////////// + input IRDA_RXD, + output IRDA_TXD, + + //////////// KEY ////////// + input [3:0] KEY, + + //////////// LED ////////// + output [9:0] LEDR, + + //////////// PS2 ////////// + inout PS2_CLK, + inout PS2_CLK2, + inout PS2_DAT, + inout PS2_DAT2, + + //////////// SW ////////// + input [9:0] SW, + + //////////// Video-In ////////// + input TD_CLK27, + input [7:0] TD_DATA, + input TD_HS, + output TD_RESET_N, + input TD_VS, + + //////////// VGA ////////// + output VGA_BLANK_N, + output [7:0] VGA_B, + output VGA_CLK, + output [7:0] VGA_G, + output VGA_HS, + output [7:0] VGA_R, + output VGA_SYNC_N, + output VGA_VS, + + //////////// GPIO_0, GPIO_0 connect to GPIO Default ////////// + inout [35:0] GPIO +); + + wire uart_tx; + wire uart_rx; + assign GPIO[5] = uart_tx; + assign GPIO[7] = 1'bz; + assign uart_rx = GPIO[7]; + +`ifdef USECLOCK50 + wire wClk = CLOCK_50; +`else + wire clk100MHz, clk75MHz, clklocked; + clk100M clk100(.refclk(CLOCK_50), + .rst(~KEY[3]), + .outclk_0(clk100MHz), + .outclk_1(clk75MHz), + .locked(clklocked)); + + wire wClk = clk100MHz; +`endif + wire nwReset = KEY[3]; + + wire wWrite, wRead; + wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart; + wire [3:0] bWriteMask; + + assign bReadDataKey = {18'b0, KEY, SW}; + + reg readcmd; + reg [31:0] readaddr; + + wire wRead_out = readcmd; + wire [31:0] bReadAddr_out = readaddr; + + + always @(posedge wClk) begin + if (!nwReset) begin + readcmd <= 1'b0; + readaddr <= 32'b0; + end else begin + readcmd <= wRead; + readaddr <= bReadAddr; + end + end + + assign bReadData = + ((bReadAddr_out & 32'hffffff00) == 32'hf0000000) ? bReadDataKey : ( + ((bReadAddr_out & 32'hffffc000) == 32'h00000000) ? bReadDataRam : ( + ((bReadAddr_out & 32'hffffff00) == 32'h00000100) ? bReadDataUart : (0) + ) + ); + + wire [10:0] ramaddr; + assign ramaddr = wWrite?bWriteAddr[12:2]:bReadAddr[12:2]; + + wire [4:0] regno; + wire [3:0] regena; + wire [31:0] regwrdata; + wire regwren; + wire [31:0] regrddata; + wire [2:0] uartaddr; + assign uartaddr = wWrite?bWriteAddr[4:2]:bReadAddr[4:2]; + altera_uart uart( + // inputs: + .address(uartaddr), + .begintransfer(SW[0]), + .chipselect((uartaddr & 32'hffffff00)==32'hf0000100), + .clk(wClk), + .read_n(~wRead), + .reset_n(nwReset), + .rxd(uart_rx), + .write_n(~wWrite), + .writedata(bWriteData), + + // outputs: + .dataavailable(LEDR[0]), + .irq(LEDR[1]), + .readdata(bReadDataUart), + .readyfordata(LEDR[2]), + .txd(uart_tx) + ); + + regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata); + ram8kb ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hffffc000) == 0)?wWrite:1'b0, bReadDataRam); + riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData, + regno, regena, regwrdata, regwren, regrddata); + + reg [6:0] led0; + reg [6:0] led1; + reg [6:0] led2; + reg [6:0] led3; + reg [6:0] led4; + reg [6:0] led5; + assign HEX0 = ~led0; + assign HEX1 = ~led1; + assign HEX2 = ~led2; + assign HEX3 = ~led3; + assign HEX4 = ~led4; + assign HEX5 = ~led5; + + + + always @(posedge wClk) begin + if (!nwReset) begin + led0 <= 8'h3f; + led1 <= 8'h3f; + led2 <= 8'h3f; + led3 <= 8'h3f; + led4 <= 8'h3f; + led5 <= 8'h3f; + end else begin + if (SW[8]) begin + led0 <= 8'h06; + led1 <= 8'h06; + led2 <= 8'h06; + led3 <= 8'h07; + led4 <= 8'h07; + led5 <= 8'h07; + end + else if (SW[9]) begin + led0 <= 8'h3f; + led1 <= 8'h06; + led2 <= 8'h5b; + led3 <= 8'h4f; + led4 <= 8'h66; + led5 <= 8'h6d; + end + else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin + if (bWriteAddr[7:0] == 8'h10) begin + led0 <= bWriteData[6:0]; + led1 <= bWriteData[14:8]; + led2 <= bWriteData[22:16]; + led3 <= bWriteData[30:24]; + end else if (bWriteAddr[7:0] == 8'h14) begin + led4 <= bWriteData[6:0]; + led5 <= bWriteData[14:8]; + end + end + end + end + +endmodule + diff --git a/examples/hdl4se_riscv/de1/qsys/.qsys_edit/i-qsys.xml b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/i-qsys.xml new file mode 100644 index 0000000000000000000000000000000000000000..42540c844d1523c1626ad768b6fc7ebffadf9c38 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/i-qsys.xml @@ -0,0 +1,1848 @@ + + + + + + + + + + + + + ccontrol center + true + + false + + + + + + + + + + + + + + + + + + + + + + + + + dock.CContentArea.center + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Library + + true + + id + index + placeholder + + 0 + 0 + dock.single.Library + + + + + + + + + Library + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Hierarchy + + true + + id + index + placeholder + + 0 + 0 + dock.single.Hierarchy + + + + + + + + + Hierarchy + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.System\ Contents + + true + + id + index + placeholder + + 0 + 0 + dock.single.System\ Contents + + + + dock.single.Address\ Map + + true + + id + index + placeholder + + 1 + 1 + dock.single.Address\ Map + + + + dock.single.Instrumentation + + true + + id + index + placeholder + + 2 + 2 + dock.single.Instrumentation + + + + dock.single.Clock\ Settings + + true + + id + index + placeholder + + 3 + 3 + dock.single.Clock\ Settings + + + + dock.single.Instance\ Parameters + + true + + id + index + placeholder + + 4 + 4 + dock.single.Instance\ Parameters + + + + dock.single.Project\ Settings + + true + + id + index + placeholder + + 5 + 5 + dock.single.Project\ Settings + + + + dock.single.HDL\ Example + + true + + id + index + placeholder + + 6 + 6 + dock.single.HDL\ Example + + + + dock.single.Generation + + true + + id + index + placeholder + + 7 + 7 + dock.single.Generation + + + + dock.single.Connections + + true + + id + index + placeholder + + 8 + 8 + dock.single.Connections + + + + dock.single.Data\ Path + + true + + id + index + placeholder + + 9 + 9 + dock.single.Data\ Path + + + + dock.single.Domains + + true + + id + index + placeholder + + 10 + 10 + dock.single.Domains + + + + + + + + + System Contents + + + + + + + + + + Address Map + + + + + + + + + + Instrumentation + + + + + + + + + + Clock Settings + + + + + + + + + + Instance Parameters + + + + + + + + + + Project Settings + + + + + + + + + + HDL Example + + + + + + + + + + Generation + + + + + + + + + + Connections + + + + + + + + + + Data Path + + + + + + + + + + Domains + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Parameter\ Editor + + true + + id + index + placeholder + + 0 + 0 + dock.single.Parameter\ Editor + + + + + + + + + Parameter Editor + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Block\ Symbol + + true + + id + index + placeholder + + 0 + 0 + dock.single.Block\ Symbol + + + + dock.single.Element\ Docs + + true + + id + index + placeholder + + 1 + 1 + dock.single.Element\ Docs + + + + + + + + + Block Symbol + + + + + + + + + + Element Docs + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Presets + + true + + id + index + placeholder + + 0 + 0 + dock.single.Presets + + + + + + + + + Presets + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Messages + + true + + id + index + placeholder + + 0 + 0 + dock.single.Messages + + + + + + + + + Messages + + + + + + + + + + + + + + ccontrol south + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol north + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + external + true + + + 0 + dock.PlaceholderList + + + + + + + dock.CExternalizeArea + + + + + + + + + ccontrol east + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol west + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ccontrol center + true + + false + + + + + dock.single.Library + + + 0 + dock.PlaceholderList + + + + + dock.single.Hierarchy + + + + + + + + + dock.single.Clocks + dock.single.Project\ Settings + dock.single.Generation + dock.single.Instrumentation\ \-\ Beta + dock.single.Connections + dock.single.Parameters + dock.single.Connections\ \-\ Beta + dock.single.Clock\ Settings + dock.single.Address\ Map + dock.single.System\ Contents + dock.single.Interconnect\ Requirements + dock.single.Instance\ Parameters + dock.single.Clock\ Domains\ \-\ Beta + dock.single.Data\ Path + dock.single.Data\ Path\ \-\ Beta + dock.single.Instrumentation + dock.single.Domains + dock.single.HDL\ Example + + + 0 + dock.PlaceholderList + + + + + dock.single.Parameter\ Editor + + + + + + + dock.single.Element\ Docs + dock.single.Block\ Symbol + + + + + dock.single.Presets + + + + + + + dock.single.Messages + + + 0 + dock.PlaceholderList + + + + + + + + + + dock.CContentArea.center + + + + + + + + Library + + + + + + + + + + Hierarchy + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.System\ Contents + + true + + id + index + placeholder + + 0 + 0 + dock.single.System\ Contents + + + + dock.single.Address\ Map + + true + + id + index + placeholder + + 1 + 1 + dock.single.Address\ Map + + + + dock.single.Instrumentation\ \-\ Beta + + + + + dock.single.Instance\ Parameters + + + + + dock.single.Project\ Settings + + true + + id + index + placeholder + + 2 + 2 + dock.single.Project\ Settings + + + + dock.single.Clocks + + + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + dock.single.Connections\ \-\ Beta + + + + + dock.single.Interconnect\ Requirements + + + + + dock.single.Data\ Path\ \-\ Beta + + + + + dock.single.Parameters + + + + + + + + + + System Contents + + + + + + + + + + Address Map + + + + + + + + + + Project Settings + + + + + + + + + + + + Messages + + + + + + + + + + + + true + + + 0 + dock.PlaceholderList + + + + + + + dock.CExternalizeArea + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + dock.single.Hierarchy + + + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + + + 6 + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + Clock Domains - Beta + + + + + + + + + + dock.single.Instance\ Parameters + + + + + + + + + + 3 + dock.single.Instance\ Parameters + + + + + + + Instance Parameters + + + + + + + + + + dock.single.Clocks + + + + + + + + + + 5 + dock.single.Clocks + + + + + + + Clocks + + + + + + + + + + dock.single.Connections\ \-\ Beta + + + + + + + + + + 7 + dock.single.Connections\ \-\ Beta + + + + + + + Connections - Beta + + + + + + + + + + dock.single.Parameters + + + + + + + + + + 10 + dock.single.Parameters + + + + + + + Parameters + + + + + + + + + + dock.single.Presets + + + + + + + + + + + + + + Presets + + + + + + + + + + dock.single.Instrumentation\ \-\ Beta + + + + + + + + + + 2 + dock.single.Instrumentation\ \-\ Beta + + + + + + + Instrumentation - Beta + + + + + + + + + + dock.single.Interconnect\ Requirements + + + + + + + + + + 8 + dock.single.Interconnect\ Requirements + + + + + + + Interconnect Requirements + + + + + + + + + + dock.single.Block\ Symbol + + + + + + + + + + + + + + Block Symbol + + + + + + + + + + dock.single.Data\ Path\ \-\ Beta + + + + + + + + + + 9 + dock.single.Data\ Path\ \-\ Beta + + + + + + + Data Path - Beta + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Project\ Settings + + + + + + + + + + + 5 + dock.single.Project\ Settings + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Library + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.System\ Contents + + + + + + + + + + + 0 + dock.single.System\ Contents + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + + + + 9 + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Instance\ Parameters + + + + + + + + + + + 4 + dock.single.Instance\ Parameters + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Address\ Map + + + + + + + + + + + 1 + dock.single.Address\ Map + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Clocks + + + + + + + + + + + 3 + dock.single.Clocks + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Connections\ \-\ Beta + + + + + + + + + + + 7 + dock.single.Connections\ \-\ Beta + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Parameters + + + + + + + + + + 1 + dock.single.Parameters + + + + + dock.mode.minimized + ccontrol west + + + 0 + false + 400 + dock.single.Parameters + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Presets + + + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Messages + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Instrumentation\ \-\ Beta + + + + + + + + + + + 2 + dock.single.Instrumentation\ \-\ Beta + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Interconnect\ Requirements + + + + + + + + + + + 8 + dock.single.Interconnect\ Requirements + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Block\ Symbol + + + + + + + + + + 0 + dock.single.Block\ Symbol + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Data\ Path\ \-\ Beta + + + + + + + + + + + 8 + dock.single.Data\ Path\ \-\ Beta + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Hierarchy + + + + + + + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Hierarchy + + + + + + + + + + + + + + + + eclipse + + \ No newline at end of file diff --git a/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml index 48fdb7a4943136ef2956a36cfbdc8893999d9d52..67f454926a64b3326025bf50e8a891475a5f0748 100644 --- a/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml +++ b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml @@ -14,7 +14,7 @@ - + + expandedCategories="Library/Window Bridge,Library/Peripherals/Microcontroller Peripherals,Library/Peripherals,Library/Verification,Library,Project" /> diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.bsf b/examples/hdl4se_riscv/de1/qsys/i-qsys.bsf new file mode 100644 index 0000000000000000000000000000000000000000..025cf1e32646c28f5af04aa7b40efd28884c997a --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys.bsf @@ -0,0 +1,143 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 496 328) + (text "i-qsys" (rect 231 -1 254 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 312 20 324)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 192 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 192 112)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "vic_0_clk_clk" (rect 0 0 55 12)(font "Arial" (font_size 8))) + (text "vic_0_clk_clk" (rect 4 141 82 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 192 152)(line_width 1)) + ) + (port + (pt 0 192) + (input) + (text "vic_0_clk_reset_reset" (rect 0 0 90 12)(font "Arial" (font_size 8))) + (text "vic_0_clk_reset_reset" (rect 4 181 130 192)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 192 192)(line_width 1)) + ) + (port + (pt 0 232) + (input) + (text "vic_0_csr_access_read" (rect 0 0 99 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_read" (rect 4 221 130 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 192 232)(line_width 1)) + ) + (port + (pt 0 248) + (input) + (text "vic_0_csr_access_write" (rect 0 0 99 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_write" (rect 4 237 136 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 192 248)(line_width 1)) + ) + (port + (pt 0 264) + (input) + (text "vic_0_csr_access_address[7..0]" (rect 0 0 133 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_address[7..0]" (rect 4 253 184 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 192 264)(line_width 3)) + ) + (port + (pt 0 280) + (input) + (text "vic_0_csr_access_writedata[31..0]" (rect 0 0 139 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_writedata[31..0]" (rect 4 269 202 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 192 280)(line_width 3)) + ) + (port + (pt 0 296) + (output) + (text "vic_0_csr_access_readdata[31..0]" (rect 0 0 139 12)(font "Arial" (font_size 8))) + (text "vic_0_csr_access_readdata[31..0]" (rect 4 285 196 296)(font "Arial" (font_size 8))) + (line (pt 0 296)(pt 192 296)(line_width 3)) + ) + (port + (pt 496 72) + (output) + (text "vic_0_interrupt_controller_out_valid" (rect 0 0 142 12)(font "Arial" (font_size 8))) + (text "vic_0_interrupt_controller_out_valid" (rect 317 61 533 72)(font "Arial" (font_size 8))) + (line (pt 496 72)(pt 272 72)(line_width 1)) + ) + (port + (pt 496 88) + (output) + (text "vic_0_interrupt_controller_out_data[44..0]" (rect 0 0 168 12)(font "Arial" (font_size 8))) + (text "vic_0_interrupt_controller_out_data[44..0]" (rect 288 77 540 88)(font "Arial" (font_size 8))) + (line (pt 496 88)(pt 272 88)(line_width 3)) + ) + (drawing + (text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 163 83 356 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 197 107 436 224)(font "Arial" (color 0 0 0))) + (text "vic_0_clk" (rect 139 123 332 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 197 147 412 304)(font "Arial" (color 0 0 0))) + (text "vic_0_clk_reset" (rect 101 163 292 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 197 187 424 384)(font "Arial" (color 0 0 0))) + (text "vic_0_csr_access" (rect 89 203 274 419)(font "Arial" (color 128 0 0)(font_size 9))) + (text "read" (rect 197 227 418 464)(font "Arial" (color 0 0 0))) + (text "write" (rect 197 243 424 496)(font "Arial" (color 0 0 0))) + (text "address" (rect 197 259 436 528)(font "Arial" (color 0 0 0))) + (text "writedata" (rect 197 275 448 560)(font "Arial" (color 0 0 0))) + (text "readdata" (rect 197 291 442 592)(font "Arial" (color 0 0 0))) + (text "vic_0_interrupt_controller_out" (rect 273 43 726 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "valid" (rect 249 67 528 144)(font "Arial" (color 0 0 0))) + (text "data" (rect 251 83 526 176)(font "Arial" (color 0 0 0))) + (text " i-qsys " (rect 467 312 982 634)(font "Arial" )) + (line (pt 193 52)(pt 193 76)(line_width 1)) + (line (pt 194 52)(pt 194 76)(line_width 1)) + (line (pt 193 92)(pt 193 116)(line_width 1)) + (line (pt 194 92)(pt 194 116)(line_width 1)) + (line (pt 193 132)(pt 193 156)(line_width 1)) + (line (pt 194 132)(pt 194 156)(line_width 1)) + (line (pt 193 172)(pt 193 196)(line_width 1)) + (line (pt 194 172)(pt 194 196)(line_width 1)) + (line (pt 193 212)(pt 193 300)(line_width 1)) + (line (pt 194 212)(pt 194 300)(line_width 1)) + (line (pt 271 52)(pt 271 92)(line_width 1)) + (line (pt 270 52)(pt 270 92)(line_width 1)) + (line (pt 192 32)(pt 272 32)(line_width 1)) + (line (pt 272 32)(pt 272 312)(line_width 1)) + (line (pt 192 312)(pt 272 312)(line_width 1)) + (line (pt 192 32)(pt 192 312)(line_width 1)) + (line (pt 0 0)(pt 496 0)(line_width 1)) + (line (pt 496 0)(pt 496 328)(line_width 1)) + (line (pt 0 328)(pt 496 328)(line_width 1)) + (line (pt 0 0)(pt 0 328)(line_width 1)) + ) +) diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.cmp b/examples/hdl4se_riscv/de1/qsys/i-qsys.cmp new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.html b/examples/hdl4se_riscv/de1/qsys/i-qsys.html new file mode 100644 index 0000000000000000000000000000000000000000..e69a54384dfe81b063237b242bf8c6fb84549ba3 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys.html @@ -0,0 +1,231 @@ + + + + + datasheet for i-qsys + + + + + + + + +
i-qsys +
+
+
+ + + + + +
2021.08.28.08:45:04Datasheet
+
+
Overview
+
+
+ + + + + + + + +
  clk_0 i-qsys
+
+
+
All Components +
   + vic_0 + altera_vic 13.1 +
+
+
+
Memory Map
+ + + + + + + + + + +
  + vic_0 + +
csr_access 
+ +
+
+

clk_0

clock_source v13.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + +
clockFrequency50000000
clockFrequencyKnowntrue
inputClockFrequency0
resetSynchronousEdgesNONE
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ +
+
+

vic_0

altera_vic v13.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NUMBER_OF_INT_PORTS8
RIL_WIDTH4
DAISY_CHAIN_ENABLE0
AUTO_DEVICE_FAMILYCYCLONEV
AUTO_DEVICE5CSEMA5F31C6
deviceFamilyCyclone V
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + +
DAISY_CHAIN_ENABLE0
NUMBER_OF_INT_PORTS8
RIL_WIDTH4
+
+
+ + + + + +
generation took 0.01 secondsrendering took 0.02 seconds
+ + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.qsys b/examples/hdl4se_riscv/de1/qsys/i-qsys.qsys new file mode 100644 index 0000000000000000000000000000000000000000..1d1e574821d497f752de673753fa31f374acc5a0 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys.qsys @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys.sopcinfo b/examples/hdl4se_riscv/de1/qsys/i-qsys.sopcinfo new file mode 100644 index 0000000000000000000000000000000000000000..497e476d01205f1a26327d0aa4d6c3a9fee65707 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys.sopcinfo @@ -0,0 +1,1206 @@ + + + + + + + java.lang.Integer + 1630111504 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + 5CSEMA5F31C6 + false + true + false + true + + + java.lang.Long + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.Long + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + boolean + false + false + true + true + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + embeddedsw.CMacro.DAISY_CHAIN_ENABLE + 0 + + + embeddedsw.CMacro.NUMBER_OF_INT_PORTS + 8 + + + embeddedsw.CMacro.RIL_WIDTH + 4 + + + int + 8 + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + 5CSEMA5F31C6 + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + clk_reset_reset + Input + 1 + reset + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + irq_input_irq + Input + 8 + irq + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_access_read + Input + 1 + read + + + csr_access_write + Input + 1 + write + + + csr_access_address + Input + 8 + address + + + csr_access_writedata + Input + 32 + writedata + + + csr_access_readdata + Output + 32 + readdata + + + + + + embeddedsw.configuration.isInterruptControllerSender + 1 + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 45 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + interrupt_controller_out_valid + Output + 1 + valid + + + interrupt_controller_out_data + Output + 45 + data + + + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 13.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.1 + + + 1 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 13.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 13.1 + + + 1 + altera_vic + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Vectored Interrupt Controller + 13.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 13.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 13.1 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 13.1 + + 13.1 162 + + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.debuginfo b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.debuginfo new file mode 100644 index 0000000000000000000000000000000000000000..ff9638d7ae7dfd46585afd5fe4b5bf79188bd206 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.debuginfo @@ -0,0 +1,1503 @@ + + + + + + + com.altera.sopcmodel.ensemble.EClockAdapter + HANDSHAKE + false + true + true + true + + + java.lang.String + 5CSEMA5F31C6 + false + true + true + true + + + java.lang.String + CYCLONEV + false + true + true + true + + + java.lang.String + 6 + false + true + false + true + + + com.altera.sopcmodel.ensemble.Ensemble$EFabricMode + QSYS + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1630111504 + false + true + true + true + + + boolean + false + false + true + false + true + + + com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage + VERILOG + false + false + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 0 + false + true + false + true + + + long + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + embeddedsw.CMacro.DAISY_CHAIN_ENABLE + 0 + + + embeddedsw.CMacro.NUMBER_OF_INT_PORTS + 8 + + + embeddedsw.CMacro.RIL_WIDTH + 4 + + + int + 8 + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + 5CSEMA5F31C6 + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk_clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + clk_reset_reset + Input + 1 + reset + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + irq_input_irq + Input + 8 + irq + + + false + irq_mapper + sender + irq_mapper.sender + 0 + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_reset + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_access_read + Input + 1 + read + + + csr_access_write + Input + 1 + write + + + csr_access_address + Input + 8 + address + + + csr_access_writedata + Input + 32 + writedata + + + csr_access_readdata + Output + 32 + readdata + + + + + + embeddedsw.configuration.isInterruptControllerSender + 1 + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 45 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + interrupt_controller_out_valid + Output + 1 + valid + + + interrupt_controller_out_data + Output + 45 + data + + + + + + + int + 0 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + CYCLONEV + false + true + false + true + + + java.lang.String + Cyclone V + false + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + clk_reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + sender_irq + Output + 8 + irq + + + + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + vic_0 + irq_input + irq_mapper + sender + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.1 + + + 1 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 13.1 + + + 2 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 13.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 13.1 + + + 1 + altera_irq_mapper + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Merlin IRQ Mapper + 13.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 13.1 + + + 2 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 13.1 + + + 1 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 13.1 + + + 1 + altera_vic + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Vectored Interrupt Controller + 13.1 + + + 1 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 13.1 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 13.1 + + 13.1 162 + 00000000000000E00000017B8A3798AD + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.qip b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.qip new file mode 100644 index 0000000000000000000000000000000000000000..38653ac30daf5765b47e2ae9ee0fa9500dc9e5b5 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.qip @@ -0,0 +1,34 @@ +set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_NAME "Qsys" +set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "i-qsys" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -library "i-qsys" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../i-qsys.sopcinfo"] +set_global_assignment -entity "i-qsys" -library "i-qsys" -name SLD_INFO "QSYS_NAME i-qsys HAS_SOPCINFO 1 GENERATION_ID 1630111504" +set_global_assignment -library "i-qsys" -name MISC_FILE [file join $::quartus(qip_path) "../../i-qsys.cmp"] +set_global_assignment -library "i-qsys" -name SLD_FILE [file join $::quartus(qip_path) "i-qsys.debuginfo"] +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "i-qsys" -name MISC_FILE [file join $::quartus(qip_path) "../../i-qsys.qsys"] + +set_global_assignment -library "i-qsys" -name VERILOG_FILE [file join $::quartus(qip_path) "i-qsys.v"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/i-qsys_irq_mapper.sv"] +set_global_assignment -library "i-qsys" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/i-qsys_vic_0.v"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_vector.sv"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_priority.sv"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_compare2.sv"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_compare4.sv"] +set_global_assignment -library "i-qsys" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_vic_csr.sv"] + +set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_NAME "altera_irq_mapper" +set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "i-qsys_irq_mapper" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_NAME "altera_vic" +set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "i-qsys_vic_0" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_vector" +set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "altera_vic_vector" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_priority" +set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "altera_vic_priority" -library "i-qsys" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_NAME "altera_vic_csr" +set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_VERSION "13.1" +set_global_assignment -entity "altera_vic_csr" -library "i-qsys" -name IP_TOOL_ENV "Qsys" diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.v b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.v new file mode 100644 index 0000000000000000000000000000000000000000..efe9eaa54fb4fa62099779a0b485c928140d3afa --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/i-qsys.v @@ -0,0 +1,41 @@ +// i-qsys.v + +// Generated using ACDS version 13.1 162 at 2021.08.28.08:45:04 + +`timescale 1 ps / 1 ps +module i-qsys ( + input wire clk_clk, // clk.clk + input wire reset_reset_n, // reset.reset_n + input wire vic_0_clk_clk, // vic_0_clk.clk + input wire vic_0_clk_reset_reset, // vic_0_clk_reset.reset + input wire vic_0_csr_access_read, // vic_0_csr_access.read + input wire vic_0_csr_access_write, // .write + input wire [7:0] vic_0_csr_access_address, // .address + input wire [31:0] vic_0_csr_access_writedata, // .writedata + output wire [31:0] vic_0_csr_access_readdata, // .readdata + output wire vic_0_interrupt_controller_out_valid, // vic_0_interrupt_controller_out.valid + output wire [44:0] vic_0_interrupt_controller_out_data // .data + ); + + wire [7:0] vic_0_irq_input_irq; // irq_mapper:sender_irq -> vic_0:irq_input_irq + + i-qsys_vic_0 vic_0 ( + .clk_clk (vic_0_clk_clk), // clk.clk + .clk_reset_reset (vic_0_clk_reset_reset), // clk_reset.reset + .irq_input_irq (vic_0_irq_input_irq), // irq_input.irq + .csr_access_read (vic_0_csr_access_read), // csr_access.read + .csr_access_write (vic_0_csr_access_write), // .write + .csr_access_address (vic_0_csr_access_address), // .address + .csr_access_writedata (vic_0_csr_access_writedata), // .writedata + .csr_access_readdata (vic_0_csr_access_readdata), // .readdata + .interrupt_controller_out_valid (vic_0_interrupt_controller_out_valid), // interrupt_controller_out.valid + .interrupt_controller_out_data (vic_0_interrupt_controller_out_data) // .data + ); + + i-qsys_irq_mapper irq_mapper ( + .clk (), // clk.clk + .reset (), // clk_reset.reset + .sender_irq (vic_0_irq_input_irq) // sender.irq + ); + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare2.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare2.sv new file mode 100644 index 0000000000000000000000000000000000000000..9e6cebbf1616b050410a7b79a117c825e871ec79 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare2.sv @@ -0,0 +1,65 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_compare2 #(parameter PRIORITY_WIDTH = 6, + parameter DATA_WIDTH = 20) +( + input wire int_validA, + input wire [DATA_WIDTH-1:0] int_dataA, + + input wire int_validB, + input wire [DATA_WIDTH-1:0] int_dataB, + + output reg int_validZ, + output reg [DATA_WIDTH-1:0] int_dataZ, + + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +wire [PRIORITY_WIDTH:0] LevelA; +wire [PRIORITY_WIDTH:0] LevelB; + +reg [PRIORITY_WIDTH+1:0] LevelDiffZ; + + +// ******************************************************************** +// Module Logic - 1st compare stage clocked + +assign LevelA = {int_validA, int_dataA[PRIORITY_WIDTH-1:0]}; +assign LevelB = {int_validB, int_dataB[PRIORITY_WIDTH-1:0]}; + + +always @(LevelA, LevelB) begin + LevelDiffZ = (LevelA - LevelB); +end + + +always @(posedge clk) begin + if (LevelDiffZ[PRIORITY_WIDTH+1]) begin + int_validZ <= int_validB; + int_dataZ <= int_dataB; + end + else begin + int_validZ <= int_validA; + int_dataZ <= int_dataA; + end +end + + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare4.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare4.sv new file mode 100644 index 0000000000000000000000000000000000000000..fc66769552464caa56a0350e0dbd69052fd8f589 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_compare4.sv @@ -0,0 +1,128 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_compare4 #(parameter PRIORITY_WIDTH = 6, + parameter DATA_WIDTH = 20) +( + input wire int_validA, + input wire [DATA_WIDTH-1:0] int_dataA, + + input wire int_validB, + input wire [DATA_WIDTH-1:0] int_dataB, + + input wire int_validC, + input wire [DATA_WIDTH-1:0] int_dataC, + + input wire int_validD, + input wire [DATA_WIDTH-1:0] int_dataD, + + output reg int_validZ, + output reg [DATA_WIDTH-1:0] int_dataZ, + + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +wire [PRIORITY_WIDTH:0] LevelA; +wire [PRIORITY_WIDTH:0] LevelB; +wire [PRIORITY_WIDTH:0] LevelC; +wire [PRIORITY_WIDTH:0] LevelD; + +wire [PRIORITY_WIDTH:0] LevelX; +wire [PRIORITY_WIDTH:0] LevelY; + +reg [PRIORITY_WIDTH+1:0] LevelDiffX; +reg [PRIORITY_WIDTH+1:0] LevelDiffY; +reg [PRIORITY_WIDTH+1:0] LevelDiffZ; + +reg int_validX; +reg [DATA_WIDTH-1:0] int_dataX; + +reg int_validY; +reg [DATA_WIDTH-1:0] int_dataY; + + +// ******************************************************************** +// Module Logic - 1st and 2nd compare stages combinational + +assign LevelA = {int_validA, int_dataA[PRIORITY_WIDTH-1:0]}; +assign LevelB = {int_validB, int_dataB[PRIORITY_WIDTH-1:0]}; +assign LevelC = {int_validC, int_dataC[PRIORITY_WIDTH-1:0]}; +assign LevelD = {int_validD, int_dataD[PRIORITY_WIDTH-1:0]}; + + +always @(LevelA, LevelB) begin + LevelDiffX = (LevelA - LevelB); +end + + +always @(LevelDiffX, int_validA, int_dataA, int_validB, int_dataB) begin + if (LevelDiffX[PRIORITY_WIDTH+1]) begin + int_validX <= int_validB; + int_dataX <= int_dataB; + end + else begin + int_validX <= int_validA; + int_dataX <= int_dataA; + end +end + + +always @(LevelC, LevelD) begin + LevelDiffY = (LevelC - LevelD); +end + + +always @(LevelDiffY, int_validC, int_dataC, int_validD, int_dataD) begin + if (LevelDiffY[PRIORITY_WIDTH+1]) begin + int_validY <= int_validD; + int_dataY <= int_dataD; + end + else begin + int_validY <= int_validC; + int_dataY <= int_dataC; + end +end + + + +// ******************************************************************** +// Module Logic - 3rd compare stage clocked + +assign LevelX = {int_validX, int_dataX[PRIORITY_WIDTH-1:0]}; +assign LevelY = {int_validY, int_dataY[PRIORITY_WIDTH-1:0]}; + + +always @(LevelX, LevelY) begin + LevelDiffZ = (LevelX - LevelY); +end + + +always @(posedge clk) begin + if (LevelDiffZ[PRIORITY_WIDTH+1]) begin + int_validZ <= int_validY; + int_dataZ <= int_dataY; + end + else begin + int_validZ <= int_validX; + int_dataZ <= int_dataX; + end +end + + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_csr.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_csr.sv new file mode 100644 index 0000000000000000000000000000000000000000..45a478fbb37348a2062ae4a41f50b2851d74817d --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_csr.sv @@ -0,0 +1,800 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_csr #(parameter NUMBER_OF_INT_PORTS = 32, + parameter RRS_WIDTH = 6, + parameter RIL_WIDTH = 6, + parameter DAISY_CHAIN_ENABLE = 0) +( + input wire [NUMBER_OF_INT_PORTS-1:0] inr_i1_irq, + + input wire [7:0] avs_s1_address, + input wire avs_s1_read, + input wire avs_s1_write, + input wire [31:0] avs_s1_writedata, + output reg [31:0] avs_s1_readdata, + + input wire dc_in_valid, + input wire [44:0] dc_in_data, + + output reg dc_out_valid, + output reg [31:0] dc_out_data, + + output wire out0_valid, + output wire [18:0] out0_data, + + output wire out1_valid, + output wire [18:0] out1_data, + + output wire out2_valid, + output wire [18:0] out2_data, + + output wire out3_valid, + output wire [18:0] out3_data, + + output wire out4_valid, + output wire [18:0] out4_data, + + output wire out5_valid, + output wire [18:0] out5_data, + + output wire out6_valid, + output wire [18:0] out6_data, + + output wire out7_valid, + output wire [18:0] out7_data, + + output wire out8_valid, + output wire [18:0] out8_data, + + output wire out9_valid, + output wire [18:0] out9_data, + + output wire out10_valid, + output wire [18:0] out10_data, + + output wire out11_valid, + output wire [18:0] out11_data, + + output wire out12_valid, + output wire [18:0] out12_data, + + output wire out13_valid, + output wire [18:0] out13_data, + + output wire out14_valid, + output wire [18:0] out14_data, + + output wire out15_valid, + output wire [18:0] out15_data, + + output wire out16_valid, + output wire [18:0] out16_data, + + output wire out17_valid, + output wire [18:0] out17_data, + + output wire out18_valid, + output wire [18:0] out18_data, + + output wire out19_valid, + output wire [18:0] out19_data, + + output wire out20_valid, + output wire [18:0] out20_data, + + output wire out21_valid, + output wire [18:0] out21_data, + + output wire out22_valid, + output wire [18:0] out22_data, + + output wire out23_valid, + output wire [18:0] out23_data, + + output wire out24_valid, + output wire [18:0] out24_data, + + output wire out25_valid, + output wire [18:0] out25_data, + + output wire out26_valid, + output wire [18:0] out26_data, + + output wire out27_valid, + output wire [18:0] out27_data, + + output wire out28_valid, + output wire [18:0] out28_data, + + output wire out29_valid, + output wire [18:0] out29_data, + + output wire out30_valid, + output wire [18:0] out30_data, + + output wire out31_valid, + output wire [18:0] out31_data, + + output wire out32_valid, + output wire [18:0] out32_data, + + output reg control_valid, + output reg [34:0] control_data, + + input wire status_valid, + input wire [37:0] status_data, + + input wire reset_n, + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +reg Reset; + +reg [NUMBER_OF_INT_PORTS-1:0] IntInput; + +reg DcInValid; +reg [44:0] DcInData; + +wire DcOutValid; +wire [31:0] DcOutData; + +reg [5:0] DcRrsValue; +reg DcNmiValue; +reg [5:0] DcRilValue; +reg [5:0] DcRilAdjust; +wire [5:0] RilMaxValue; + +reg [7:0] AvsAddr; +reg AvsRead; +reg AvsWrite; +reg [31:0] AvsWrData; +reg [31:0] AvsRdData; + +reg ConfRegRead; +reg ConfRegWrite; +reg [31:0] ConfRegSelect; +reg [12:0] ConfRegWrData; +wire [12:0] ConfRegRdData [31:0]; +reg ConfRegReset; +reg [12:0] ConfRegRdMux; + +reg CtrlRegRead; +reg CtrlRegWrite; +reg [11:0] CtrlRegSelect; +reg [31:0] CtrlRegWrData; +reg CtrlRegReset; +reg [31:0] CtrlRegRdMux; +reg ControlValid; + +wire [NUMBER_OF_INT_PORTS-1:0] IntEnableRdData; + +reg [NUMBER_OF_INT_PORTS-1:0] IntPendingWrData; +wire [NUMBER_OF_INT_PORTS-1:0] IntPendingRdData; + +reg [NUMBER_OF_INT_PORTS-1:0] IntRawStatusWrData; +wire [NUMBER_OF_INT_PORTS-1:0] IntRawStatusRdData; + +wire [NUMBER_OF_INT_PORTS-1:0] SwTriggerRdData; + +wire [DAISY_CHAIN_ENABLE+2:0] VicConfigRdData; + +reg [31:0] VicStatusWrData; +wire [31:0] VicStatusRdData; + +wire [31:0] VecTableBaseRdData; + +reg [31:0] VecTableAddrWrData; +wire [31:0] VecTableAddrRdData; + +wire [32:0] IntOutputValid; +wire [18:0] IntOutputData [32:0]; +wire [5:0] IntPortId [32:0]; + +genvar i, j, k, l; + + +// ******************************************************************** +// Module Logic + +always @(posedge clk) begin + Reset <= ~reset_n; + ConfRegReset <= Reset; + CtrlRegReset <= Reset; +end + + +always @(posedge clk) begin + IntInput <= inr_i1_irq; + + DcInValid <= dc_in_valid; + DcInData <= dc_in_data; + DcRrsValue <= dc_in_data[12:7]; + DcNmiValue <= dc_in_data[6]; + DcRilValue <= dc_in_data[5:0]; + + AvsAddr <= avs_s1_address; + AvsRead <= avs_s1_read; + AvsWrite <= avs_s1_write; + AvsWrData <= avs_s1_writedata; + + avs_s1_readdata <= AvsRdData; + + dc_out_valid <= DcOutValid; + dc_out_data <= DcOutData; +end + + +generate + case (RIL_WIDTH) + 1: begin assign RilMaxValue = 6'b000001; end + 2: begin assign RilMaxValue = 6'b000011; end + 3: begin assign RilMaxValue = 6'b000111; end + 4: begin assign RilMaxValue = 6'b001111; end + 5: begin assign RilMaxValue = 6'b011111; end + default: begin assign RilMaxValue = 6'b111111; end + endcase +endgenerate + + +always @(DcRilValue, RilMaxValue) begin + if (DcRilValue > RilMaxValue) + DcRilAdjust <= RilMaxValue; + else + DcRilAdjust <= DcRilValue; +end + + +always @(posedge clk) begin + if (AvsAddr[7:5] == 3'b000) begin + ConfRegRead <= AvsRead; + ConfRegWrite <= AvsWrite; + CtrlRegRead <= 1'b0; + CtrlRegWrite <= 1'b0; + end + + else begin + ConfRegRead <= 1'b0; + ConfRegWrite <= 1'b0; + CtrlRegRead <= AvsRead; + CtrlRegWrite <= AvsWrite; + end +end + + +always @(posedge clk) begin + case (AvsAddr[4:0]) + 5'h00: ConfRegSelect <= 32'h00000001; + 5'h01: ConfRegSelect <= 32'h00000002; + 5'h02: ConfRegSelect <= 32'h00000004; + 5'h03: ConfRegSelect <= 32'h00000008; + 5'h04: ConfRegSelect <= 32'h00000010; + 5'h05: ConfRegSelect <= 32'h00000020; + 5'h06: ConfRegSelect <= 32'h00000040; + 5'h07: ConfRegSelect <= 32'h00000080; + 5'h08: ConfRegSelect <= 32'h00000100; + 5'h09: ConfRegSelect <= 32'h00000200; + 5'h0A: ConfRegSelect <= 32'h00000400; + 5'h0B: ConfRegSelect <= 32'h00000800; + 5'h0C: ConfRegSelect <= 32'h00001000; + 5'h0D: ConfRegSelect <= 32'h00002000; + 5'h0E: ConfRegSelect <= 32'h00004000; + 5'h0F: ConfRegSelect <= 32'h00008000; + 5'h10: ConfRegSelect <= 32'h00010000; + 5'h11: ConfRegSelect <= 32'h00020000; + 5'h12: ConfRegSelect <= 32'h00040000; + 5'h13: ConfRegSelect <= 32'h00080000; + 5'h14: ConfRegSelect <= 32'h00100000; + 5'h15: ConfRegSelect <= 32'h00200000; + 5'h16: ConfRegSelect <= 32'h00400000; + 5'h17: ConfRegSelect <= 32'h00800000; + 5'h18: ConfRegSelect <= 32'h01000000; + 5'h19: ConfRegSelect <= 32'h02000000; + 5'h1A: ConfRegSelect <= 32'h04000000; + 5'h1B: ConfRegSelect <= 32'h08000000; + 5'h1C: ConfRegSelect <= 32'h10000000; + 5'h1D: ConfRegSelect <= 32'h20000000; + 5'h1E: ConfRegSelect <= 32'h40000000; + 5'h1F: ConfRegSelect <= 32'h80000000; + endcase +end + + +always @(posedge clk) begin + case (AvsAddr[4:0]) + 5'h00: CtrlRegSelect <= 12'h001; + 5'h01: CtrlRegSelect <= 12'h002; + 5'h02: CtrlRegSelect <= 12'h004; + 5'h03: CtrlRegSelect <= 12'h008; + 5'h04: CtrlRegSelect <= 12'h010; + 5'h05: CtrlRegSelect <= 12'h020; + 5'h06: CtrlRegSelect <= 12'h040; + 5'h07: CtrlRegSelect <= 12'h080; + 5'h08: CtrlRegSelect <= 12'h100; + 5'h09: CtrlRegSelect <= 12'h200; + 5'h0A: CtrlRegSelect <= 12'h400; + 5'h0B: CtrlRegSelect <= 12'h800; + default: CtrlRegSelect <= 12'h000; + endcase +end + + +always @(posedge clk) begin + case (AvsAddr[4:0]) + 5'h00: ConfRegRdMux <= ConfRegRdData[0]; + 5'h01: ConfRegRdMux <= ConfRegRdData[1]; + 5'h02: ConfRegRdMux <= ConfRegRdData[2]; + 5'h03: ConfRegRdMux <= ConfRegRdData[3]; + 5'h04: ConfRegRdMux <= ConfRegRdData[4]; + 5'h05: ConfRegRdMux <= ConfRegRdData[5]; + 5'h06: ConfRegRdMux <= ConfRegRdData[6]; + 5'h07: ConfRegRdMux <= ConfRegRdData[7]; + 5'h08: ConfRegRdMux <= ConfRegRdData[8]; + 5'h09: ConfRegRdMux <= ConfRegRdData[9]; + 5'h0A: ConfRegRdMux <= ConfRegRdData[10]; + 5'h0B: ConfRegRdMux <= ConfRegRdData[11]; + 5'h0C: ConfRegRdMux <= ConfRegRdData[12]; + 5'h0D: ConfRegRdMux <= ConfRegRdData[13]; + 5'h0E: ConfRegRdMux <= ConfRegRdData[14]; + 5'h0F: ConfRegRdMux <= ConfRegRdData[15]; + 5'h10: ConfRegRdMux <= ConfRegRdData[16]; + 5'h11: ConfRegRdMux <= ConfRegRdData[17]; + 5'h12: ConfRegRdMux <= ConfRegRdData[18]; + 5'h13: ConfRegRdMux <= ConfRegRdData[19]; + 5'h14: ConfRegRdMux <= ConfRegRdData[20]; + 5'h15: ConfRegRdMux <= ConfRegRdData[21]; + 5'h16: ConfRegRdMux <= ConfRegRdData[22]; + 5'h17: ConfRegRdMux <= ConfRegRdData[23]; + 5'h18: ConfRegRdMux <= ConfRegRdData[24]; + 5'h19: ConfRegRdMux <= ConfRegRdData[25]; + 5'h1A: ConfRegRdMux <= ConfRegRdData[26]; + 5'h1B: ConfRegRdMux <= ConfRegRdData[27]; + 5'h1C: ConfRegRdMux <= ConfRegRdData[28]; + 5'h1D: ConfRegRdMux <= ConfRegRdData[29]; + 5'h1E: ConfRegRdMux <= ConfRegRdData[30]; + 5'h1F: ConfRegRdMux <= ConfRegRdData[31]; + endcase +end + + +always @(posedge clk) begin + case (AvsAddr[4:0]) + 5'h00: CtrlRegRdMux <= IntEnableRdData; + + 5'h03: CtrlRegRdMux <= IntPendingRdData; + 5'h04: CtrlRegRdMux <= IntRawStatusRdData; + 5'h05: CtrlRegRdMux <= SwTriggerRdData; + + 5'h08: CtrlRegRdMux <= VicConfigRdData; + 5'h09: CtrlRegRdMux <= VicStatusRdData; + 5'h0A: CtrlRegRdMux <= VecTableBaseRdData; + 5'h0B: CtrlRegRdMux <= VecTableAddrRdData; + + default: CtrlRegRdMux <= 32'h00000000; + endcase +end + + +always @(posedge clk) begin + if (ConfRegRead) + AvsRdData <= {19'h0, ConfRegRdMux}; + + else if (CtrlRegRead) + AvsRdData <= CtrlRegRdMux; + + else + AvsRdData <= 32'h00000000; +end + + +always @(posedge clk) begin + ConfRegWrData <= AvsWrData[12:0]; + CtrlRegWrData <= AvsWrData; +end + + +always @(posedge clk) begin + IntPendingWrData <= IntEnableRdData & (IntInput | SwTriggerRdData); + IntRawStatusWrData <= IntInput; + + ControlValid <= (CtrlRegSelect[8] | CtrlRegSelect[10]) & CtrlRegWrite; + control_valid <= ControlValid; + control_data <= {VicConfigRdData[2:0], VecTableBaseRdData}; +end + + +always @(posedge clk) begin + if (status_valid) begin + VicStatusWrData[31] <= status_valid; + VicStatusWrData[30:DAISY_CHAIN_ENABLE+5] <= 0; + VicStatusWrData[DAISY_CHAIN_ENABLE+4:0] <= status_data[DAISY_CHAIN_ENABLE+36:32]; + VecTableAddrWrData <= status_data[31:0]; + end + else begin + VicStatusWrData <= 0; + VecTableAddrWrData <= 0; + end +end + + +assign IntPortId[0] = 6'h00; +assign IntPortId[1] = 6'h01; +assign IntPortId[2] = 6'h02; +assign IntPortId[3] = 6'h03; +assign IntPortId[4] = 6'h04; +assign IntPortId[5] = 6'h05; +assign IntPortId[6] = 6'h06; +assign IntPortId[7] = 6'h07; +assign IntPortId[8] = 6'h08; +assign IntPortId[9] = 6'h09; +assign IntPortId[10] = 6'h0A; +assign IntPortId[11] = 6'h0B; +assign IntPortId[12] = 6'h0C; +assign IntPortId[13] = 6'h0D; +assign IntPortId[14] = 6'h0E; +assign IntPortId[15] = 6'h0F; +assign IntPortId[16] = 6'h10; +assign IntPortId[17] = 6'h11; +assign IntPortId[18] = 6'h12; +assign IntPortId[19] = 6'h13; +assign IntPortId[20] = 6'h14; +assign IntPortId[21] = 6'h15; +assign IntPortId[22] = 6'h16; +assign IntPortId[23] = 6'h17; +assign IntPortId[24] = 6'h18; +assign IntPortId[25] = 6'h19; +assign IntPortId[26] = 6'h1A; +assign IntPortId[27] = 6'h1B; +assign IntPortId[28] = 6'h1C; +assign IntPortId[29] = 6'h1D; +assign IntPortId[30] = 6'h1E; +assign IntPortId[31] = 6'h1F; +assign IntPortId[32] = 6'h20; + + +generate + for (i=0; i < NUMBER_OF_INT_PORTS; i=i+1) begin : INT_OUT + altera_vic_output_reg U (IntPendingWrData[i], + IntPortId[i], ConfRegRdData[i], + IntOutputValid[i], + IntOutputData[i], + clk); + end +endgenerate + + +generate + if (DAISY_CHAIN_ENABLE) begin : INT_DC + altera_vic_output_reg D ((|DcRilAdjust & VicConfigRdData[3]), + 6'h20, {DcRrsValue, DcNmiValue, DcRilAdjust}, + IntOutputValid[NUMBER_OF_INT_PORTS], + IntOutputData[NUMBER_OF_INT_PORTS], + clk); + end +endgenerate + + +generate + for (j=NUMBER_OF_INT_PORTS+DAISY_CHAIN_ENABLE; j < 33; j=j+1) begin : INT_NULL + assign IntOutputValid[j] = 1'b0; + assign IntOutputData[j] = 19'h00000; + end +endgenerate + + +generate + if (DAISY_CHAIN_ENABLE) begin : OUT_DC + assign DcOutValid = DcInValid; + assign DcOutData = DcInData[44:13]; + end + else begin + assign DcOutValid = 1'b0; + assign DcOutData = 32'h00000000; + end +endgenerate + + +assign out0_valid = IntOutputValid[0]; +assign out0_data = IntOutputData[0]; + +assign out1_valid = IntOutputValid[1]; +assign out1_data = IntOutputData[1]; + +assign out2_valid = IntOutputValid[2]; +assign out2_data = IntOutputData[2]; + +assign out3_valid = IntOutputValid[3]; +assign out3_data = IntOutputData[3]; + +assign out4_valid = IntOutputValid[4]; +assign out4_data = IntOutputData[4]; + +assign out5_valid = IntOutputValid[5]; +assign out5_data = IntOutputData[5]; + +assign out6_valid = IntOutputValid[6]; +assign out6_data = IntOutputData[6]; + +assign out7_valid = IntOutputValid[7]; +assign out7_data = IntOutputData[7]; + +assign out8_valid = IntOutputValid[8]; +assign out8_data = IntOutputData[8]; + +assign out9_valid = IntOutputValid[9]; +assign out9_data = IntOutputData[9]; + +assign out10_valid = IntOutputValid[10]; +assign out10_data = IntOutputData[10]; + +assign out11_valid = IntOutputValid[11]; +assign out11_data = IntOutputData[11]; + +assign out12_valid = IntOutputValid[12]; +assign out12_data = IntOutputData[12]; + +assign out13_valid = IntOutputValid[13]; +assign out13_data = IntOutputData[13]; + +assign out14_valid = IntOutputValid[14]; +assign out14_data = IntOutputData[14]; + +assign out15_valid = IntOutputValid[15]; +assign out15_data = IntOutputData[15]; + +assign out16_valid = IntOutputValid[16]; +assign out16_data = IntOutputData[16]; + +assign out17_valid = IntOutputValid[17]; +assign out17_data = IntOutputData[17]; + +assign out18_valid = IntOutputValid[18]; +assign out18_data = IntOutputData[18]; + +assign out19_valid = IntOutputValid[19]; +assign out19_data = IntOutputData[19]; + +assign out20_valid = IntOutputValid[20]; +assign out20_data = IntOutputData[20]; + +assign out21_valid = IntOutputValid[21]; +assign out21_data = IntOutputData[21]; + +assign out22_valid = IntOutputValid[22]; +assign out22_data = IntOutputData[22]; + +assign out23_valid = IntOutputValid[23]; +assign out23_data = IntOutputData[23]; + +assign out24_valid = IntOutputValid[24]; +assign out24_data = IntOutputData[24]; + +assign out25_valid = IntOutputValid[25]; +assign out25_data = IntOutputData[25]; + +assign out26_valid = IntOutputValid[26]; +assign out26_data = IntOutputData[26]; + +assign out27_valid = IntOutputValid[27]; +assign out27_data = IntOutputData[27]; + +assign out28_valid = IntOutputValid[28]; +assign out28_data = IntOutputData[28]; + +assign out29_valid = IntOutputValid[29]; +assign out29_data = IntOutputData[29]; + +assign out30_valid = IntOutputValid[30]; +assign out30_data = IntOutputData[30]; + +assign out31_valid = IntOutputValid[31]; +assign out31_data = IntOutputData[31]; + +assign out32_valid = IntOutputValid[32]; +assign out32_data = IntOutputData[32]; + + +// ******************************************************************** +// Instantiation of CSRs + +generate + for (k=0; k < NUMBER_OF_INT_PORTS; k=k+1) begin : REG_CONFIG + altera_vic_config_reg #(RRS_WIDTH, RIL_WIDTH) U + (ConfRegSelect[k], ConfRegWrite, ConfRegWrData, ConfRegRdData[k], ConfRegReset, clk); + end +endgenerate + + +generate + for (l=NUMBER_OF_INT_PORTS; l <32; l=l+1) begin : REG_NULL + assign ConfRegRdData[l] = 13'h0000; + end +endgenerate + + +// Set Clear +altera_vic_reg_set_clear #(NUMBER_OF_INT_PORTS) INT_ENABLE + (CtrlRegSelect[2:0], CtrlRegWrite, CtrlRegWrData[NUMBER_OF_INT_PORTS-1:0], IntEnableRdData, CtrlRegReset, clk); + +// Read only +altera_vic_reg_ro #(NUMBER_OF_INT_PORTS) INT_PENDING + (IntPendingWrData, IntPendingRdData, CtrlRegReset, clk); + +// Read only +altera_vic_reg_ro #(NUMBER_OF_INT_PORTS) INT_RAW_STATUS + (IntRawStatusWrData, IntRawStatusRdData, CtrlRegReset, clk); + +// Set Clear +altera_vic_reg_set_clear #(NUMBER_OF_INT_PORTS) SW_TRIGGER + (CtrlRegSelect[7:5], CtrlRegWrite, CtrlRegWrData[NUMBER_OF_INT_PORTS-1:0], SwTriggerRdData, CtrlRegReset, clk); + +// Reg +altera_vic_reg #(DAISY_CHAIN_ENABLE+3) VIC_CONFIG + (CtrlRegSelect[8], CtrlRegWrite, CtrlRegWrData[DAISY_CHAIN_ENABLE+2:0], VicConfigRdData, CtrlRegReset, clk); + +// Read only +altera_vic_reg_ro #(32) VIC_STATUS + (VicStatusWrData, VicStatusRdData, CtrlRegReset, clk); + +// Reg +altera_vic_reg #(32) VEC_TABLE_BASE + (CtrlRegSelect[10], CtrlRegWrite, CtrlRegWrData, VecTableBaseRdData, CtrlRegReset, clk); + +// Read only +altera_vic_reg_ro #(32) VEC_TABLE_ADDR + (VecTableAddrWrData, VecTableAddrRdData, CtrlRegReset, clk); + +endmodule + + +module altera_vic_output_reg +( + input wire reg_write, + input wire [5:0] reg_portid, + input wire [12:0] reg_configdata, + output reg reg_outputvalid, + output reg [18:0] reg_outputdata, + input wire clk +); +always @(posedge clk) begin + if (reg_write) begin + reg_outputvalid <= 1'b1; + reg_outputdata <= {reg_portid, reg_configdata}; + end + else begin + reg_outputvalid <= 1'b0; + reg_outputdata <= 19'h00000; + end +end +endmodule + + +module altera_vic_config_reg #(parameter RRS_WIDTH = 6, RIL_WIDTH = 6) +( + input wire reg_select, + input wire reg_write, + input wire [12:0] reg_writedata, + output reg [12:0] reg_readdata, + input wire reg_reset, + input wire clk +); + +localparam RRS_ZEROS = 6 - RRS_WIDTH; +localparam RIL_ZEROS = 6 - RIL_WIDTH; +wire [5:0] wr_data_lsb; +wire [12:7] wr_data_msb; + +generate + if (RIL_ZEROS > 0) begin + assign wr_data_lsb = {{RIL_ZEROS{1'b0}}, reg_writedata[RIL_WIDTH-1:0]}; + end + else begin + assign wr_data_lsb = reg_writedata[RIL_WIDTH-1:0]; + end +endgenerate + +generate + if (RRS_ZEROS > 0) begin + assign wr_data_msb = {{RRS_ZEROS{1'b0}}, reg_writedata[RRS_WIDTH+6:7]}; + end + else begin + assign wr_data_msb = reg_writedata[RRS_WIDTH+6:7]; + end +endgenerate + + +always @(posedge clk) begin + if (reg_reset) + reg_readdata <= 0; + else if (reg_select && reg_write) begin + reg_readdata[12:7] <= wr_data_msb; + reg_readdata[6] <= reg_writedata[6]; + reg_readdata[5:0] <= wr_data_lsb; + end +end + +endmodule + + + +module altera_vic_reg #(parameter WIDTH = 32) +( + input wire reg_select, + input wire reg_write, + input wire [WIDTH-1:0] reg_writedata, + output reg [WIDTH-1:0] reg_readdata, + input wire reg_reset, + input wire clk +); + +always @(posedge clk) begin + if (reg_reset) + reg_readdata <= 0; + else if (reg_select && reg_write) + reg_readdata <= reg_writedata; +end + +endmodule + + + +module altera_vic_reg_ro #(parameter WIDTH = 32) +( + input wire [WIDTH-1:0] reg_writedata, + output reg [WIDTH-1:0] reg_readdata, + input wire reg_reset, + input wire clk +); + + +always @(posedge clk) begin + if (reg_reset) + reg_readdata <= 0; + else + reg_readdata <= reg_writedata; +end + +endmodule + + + +module altera_vic_reg_set_clear #(parameter WIDTH = 32) +( + input wire [2:0] reg_select, + input wire reg_write, + input wire [WIDTH-1:0] reg_writedata, + output reg [WIDTH-1:0] reg_readdata, + input wire reg_reset, + input wire clk +); + + +always @(posedge clk) begin + if (reg_reset) + reg_readdata <= 0; + else if (reg_select[0] && reg_write) + reg_readdata <= reg_writedata; + else if (reg_select[1] && reg_write) // Write 1 to Set + reg_readdata <= reg_readdata | reg_writedata; + else if (reg_select[2] && reg_write) // Write 1 to Clear + reg_readdata <= reg_readdata & ~reg_writedata; +end + +endmodule + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_priority.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_priority.sv new file mode 100644 index 0000000000000000000000000000000000000000..30eada6b66f9cc11e47c78685e6e1b70c4284999 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_priority.sv @@ -0,0 +1,351 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_priority #(parameter NUMBER_OF_INT_PORTS = 32, + parameter PRIORITY_WIDTH = 6, + parameter DATA_WIDTH = 19) +( + input wire in0_valid, + input wire [DATA_WIDTH-1:0] in0_data, + + input wire in1_valid, + input wire [DATA_WIDTH-1:0] in1_data, + + input wire in2_valid, + input wire [DATA_WIDTH-1:0] in2_data, + + input wire in3_valid, + input wire [DATA_WIDTH-1:0] in3_data, + + input wire in4_valid, + input wire [DATA_WIDTH-1:0] in4_data, + + input wire in5_valid, + input wire [DATA_WIDTH-1:0] in5_data, + + input wire in6_valid, + input wire [DATA_WIDTH-1:0] in6_data, + + input wire in7_valid, + input wire [DATA_WIDTH-1:0] in7_data, + + input wire in8_valid, + input wire [DATA_WIDTH-1:0] in8_data, + + input wire in9_valid, + input wire [DATA_WIDTH-1:0] in9_data, + + input wire in10_valid, + input wire [DATA_WIDTH-1:0] in10_data, + + input wire in11_valid, + input wire [DATA_WIDTH-1:0] in11_data, + + input wire in12_valid, + input wire [DATA_WIDTH-1:0] in12_data, + + input wire in13_valid, + input wire [DATA_WIDTH-1:0] in13_data, + + input wire in14_valid, + input wire [DATA_WIDTH-1:0] in14_data, + + input wire in15_valid, + input wire [DATA_WIDTH-1:0] in15_data, + + input wire in16_valid, + input wire [DATA_WIDTH-1:0] in16_data, + + input wire in17_valid, + input wire [DATA_WIDTH-1:0] in17_data, + + input wire in18_valid, + input wire [DATA_WIDTH-1:0] in18_data, + + input wire in19_valid, + input wire [DATA_WIDTH-1:0] in19_data, + + input wire in20_valid, + input wire [DATA_WIDTH-1:0] in20_data, + + input wire in21_valid, + input wire [DATA_WIDTH-1:0] in21_data, + + input wire in22_valid, + input wire [DATA_WIDTH-1:0] in22_data, + + input wire in23_valid, + input wire [DATA_WIDTH-1:0] in23_data, + + input wire in24_valid, + input wire [DATA_WIDTH-1:0] in24_data, + + input wire in25_valid, + input wire [DATA_WIDTH-1:0] in25_data, + + input wire in26_valid, + input wire [DATA_WIDTH-1:0] in26_data, + + input wire in27_valid, + input wire [DATA_WIDTH-1:0] in27_data, + + input wire in28_valid, + input wire [DATA_WIDTH-1:0] in28_data, + + input wire in29_valid, + input wire [DATA_WIDTH-1:0] in29_data, + + input wire in30_valid, + input wire [DATA_WIDTH-1:0] in30_data, + + input wire in31_valid, + input wire [DATA_WIDTH-1:0] in31_data, + + input wire in32_valid, + input wire [DATA_WIDTH-1:0] in32_data, + + output wire pri_valid, + output wire [DATA_WIDTH-1:0] pri_data, + + input wire reset_n, + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +wire cmp_valid_A0; +wire [DATA_WIDTH-1:0] cmp_data_A0; + +wire cmp_valid_A1; +wire [DATA_WIDTH-1:0] cmp_data_A1; + +wire cmp_valid_A2; +wire [DATA_WIDTH-1:0] cmp_data_A2; + +wire cmp_valid_A3; +wire [DATA_WIDTH-1:0] cmp_data_A3; + +wire cmp_valid_A4; +wire [DATA_WIDTH-1:0] cmp_data_A4; + +wire cmp_valid_A5; +wire [DATA_WIDTH-1:0] cmp_data_A5; + +wire cmp_valid_A6; +wire [DATA_WIDTH-1:0] cmp_data_A6; + +wire cmp_valid_A7; +wire [DATA_WIDTH-1:0] cmp_data_A7; + +wire cmp_valid_A8; +wire [DATA_WIDTH-1:0] cmp_data_A8; + +wire cmp_valid_B0; +wire [DATA_WIDTH-1:0] cmp_data_B0; + +wire cmp_valid_B1; +wire [DATA_WIDTH-1:0] cmp_data_B1; + +wire cmp_valid_B2; +wire [DATA_WIDTH-1:0] cmp_data_B2; + + +// ******************************************************************** +// Module Logic + +generate + case (NUMBER_OF_INT_PORTS) + 1: begin : port1 + assign pri_valid = in0_valid; + assign pri_data = in0_data; + end + + 2, 3, 4: begin : port2_4 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + pri_valid, pri_data, clk); + end + + 5, 6, 7, 8: begin : port5_8 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + cmp_valid_A0, cmp_data_A0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1 + (in4_valid, in4_data, in5_valid, in5_data, + in6_valid, in6_data, in7_valid, in7_data, + cmp_valid_A1, cmp_data_A1, clk); + + altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) B0 + (cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1, + pri_valid, pri_data, clk); + end + + 9, 10, 11, 12, 13, 14, 15, 16: begin : port9_16 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + cmp_valid_A0, cmp_data_A0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1 + (in4_valid, in4_data, in5_valid, in5_data, + in6_valid, in6_data, in7_valid, in7_data, + cmp_valid_A1, cmp_data_A1, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2 + (in8_valid, in8_data, in9_valid, in9_data, + in10_valid, in10_data, in11_valid, in11_data, + cmp_valid_A2, cmp_data_A2, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3 + (in12_valid, in12_data, in13_valid, in13_data, + in14_valid, in14_data, in15_valid, in15_data, + cmp_valid_A3, cmp_data_A3, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0 + (cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1, + cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3, + pri_valid, pri_data, clk); + end + + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32: begin : port17_32 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + cmp_valid_A0, cmp_data_A0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1 + (in4_valid, in4_data, in5_valid, in5_data, + in6_valid, in6_data, in7_valid, in7_data, + cmp_valid_A1, cmp_data_A1, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2 + (in8_valid, in8_data, in9_valid, in9_data, + in10_valid, in10_data, in11_valid, in11_data, + cmp_valid_A2, cmp_data_A2, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3 + (in12_valid, in12_data, in13_valid, in13_data, + in14_valid, in14_data, in15_valid, in15_data, + cmp_valid_A3, cmp_data_A3, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A4 + (in16_valid, in16_data, in17_valid, in17_data, + in18_valid, in18_data, in19_valid, in19_data, + cmp_valid_A4, cmp_data_A4, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A5 + (in20_valid, in20_data, in21_valid, in21_data, + in22_valid, in22_data, in23_valid, in23_data, + cmp_valid_A5, cmp_data_A5, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A6 + (in24_valid, in24_data, in25_valid, in25_data, + in26_valid, in26_data, in27_valid, in27_data, + cmp_valid_A6, cmp_data_A6, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A7 + (in28_valid, in28_data, in29_valid, in29_data, + in30_valid, in30_data, in31_valid, in31_data, + cmp_valid_A7, cmp_data_A7, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0 + (cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1, + cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3, + cmp_valid_B0, cmp_data_B0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B1 + (cmp_valid_A4, cmp_data_A4, cmp_valid_A5, cmp_data_A5, + cmp_valid_A6, cmp_data_A6, cmp_valid_A7, cmp_data_A7, + cmp_valid_B1, cmp_data_B1, clk); + + altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) C0 + (cmp_valid_B0, cmp_data_B0, cmp_valid_B1, cmp_data_B1, + pri_valid, pri_data, clk); + end + + default: begin : port33 + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A0 + (in0_valid, in0_data, in1_valid, in1_data, + in2_valid, in2_data, in3_valid, in3_data, + cmp_valid_A0, cmp_data_A0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A1 + (in4_valid, in4_data, in5_valid, in5_data, + in6_valid, in6_data, in7_valid, in7_data, + cmp_valid_A1, cmp_data_A1, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A2 + (in8_valid, in8_data, in9_valid, in9_data, + in10_valid, in10_data, in11_valid, in11_data, + cmp_valid_A2, cmp_data_A2, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A3 + (in12_valid, in12_data, in13_valid, in13_data, + in14_valid, in14_data, in15_valid, in15_data, + cmp_valid_A3, cmp_data_A3, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A4 + (in16_valid, in16_data, in17_valid, in17_data, + in18_valid, in18_data, in19_valid, in19_data, + cmp_valid_A4, cmp_data_A4, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A5 + (in20_valid, in20_data, in21_valid, in21_data, + in22_valid, in22_data, in23_valid, in23_data, + cmp_valid_A5, cmp_data_A5, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A6 + (in24_valid, in24_data, in25_valid, in25_data, + in26_valid, in26_data, in27_valid, in27_data, + cmp_valid_A6, cmp_data_A6, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) A7 + (in28_valid, in28_data, in29_valid, in29_data, + in30_valid, in30_data, in31_valid, in31_data, + cmp_valid_A7, cmp_data_A7, clk); + + altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) A8 + (in32_valid, in32_data, 1'b0, {DATA_WIDTH{1'b0}}, + cmp_valid_A8, cmp_data_A8, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B0 + (cmp_valid_A0, cmp_data_A0, cmp_valid_A1, cmp_data_A1, + cmp_valid_A2, cmp_data_A2, cmp_valid_A3, cmp_data_A3, + cmp_valid_B0, cmp_data_B0, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) B1 + (cmp_valid_A4, cmp_data_A4, cmp_valid_A5, cmp_data_A5, + cmp_valid_A6, cmp_data_A6, cmp_valid_A7, cmp_data_A7, + cmp_valid_B1, cmp_data_B1, clk); + + altera_vic_compare2 #(PRIORITY_WIDTH, DATA_WIDTH) B2 + (cmp_valid_A8, cmp_data_A8, 1'b0, {DATA_WIDTH{1'b0}}, + cmp_valid_B2, cmp_data_B2, clk); + + altera_vic_compare4 #(PRIORITY_WIDTH, DATA_WIDTH) C0 + (cmp_valid_B0, cmp_data_B0, cmp_valid_B1, cmp_data_B1, + cmp_valid_B2, cmp_data_B2, 1'b0, {DATA_WIDTH{1'b0}}, + pri_valid, pri_data, clk); + end + endcase +endgenerate + + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_vector.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_vector.sv new file mode 100644 index 0000000000000000000000000000000000000000..7d2f571396b214ff6e32d83e8360fd2914a203b8 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/altera_vic_vector.sv @@ -0,0 +1,136 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ns / 1ns + +module altera_vic_vector #(parameter DAISY_CHAIN_ENABLE = 0) +( + output reg out_valid, + output reg [44:0] out_data, + + output reg status_valid, + output reg [37:0] status_data, + + input wire control_valid, + input wire [34:0] control_data, + + input wire dc_valid, + input wire [31:0] dc_data, + + input wire in_valid, + input wire [18:0] in_data, + + input wire reset_n, + input wire clk +); + + +// ******************************************************************** +// Module Wiring + +wire InValid; +wire [5:0] InPortId; +wire [12:0] InConfig; + +wire OutValid; +reg [5:0] OutPortId; +reg [12:0] OutConfig; + +reg [2:0] VecSize; +reg [31:0] VecBaseAddr; + +reg [13:0] VecOffset; +reg [31:0] VecHandAddr; + +reg [31:0] DcRhaValue; + + +// ******************************************************************** +// Module Logic + +assign InValid = in_valid; +assign InPortId = in_data[18:13]; +assign InConfig = in_data[12:0]; + +assign OutValid = InValid; + + +always @(posedge clk) begin + if (control_valid) begin + VecSize <= control_data[34:32]; + VecBaseAddr <= control_data[31:0]; + end +end + + +always @(posedge clk) begin + status_valid <= OutValid; + status_data <= {OutPortId, VecHandAddr}; +end + + +always @(VecSize, InPortId) begin + case (VecSize) + 3'b000: VecOffset <= {7'b0, InPortId[4:0], 2'b0}; + 3'b001: VecOffset <= {6'b0, InPortId[4:0], 3'b0}; + 3'b010: VecOffset <= {5'b0, InPortId[4:0], 4'b0}; + 3'b011: VecOffset <= {4'b0, InPortId[4:0], 5'b0}; + 3'b100: VecOffset <= {3'b0, InPortId[4:0], 6'b0}; + 3'b101: VecOffset <= {2'b0, InPortId[4:0], 7'b0}; + 3'b110: VecOffset <= {1'b0, InPortId[4:0], 8'b0}; + 3'b111: VecOffset <= {InPortId[4:0], 9'b0}; + endcase +end + + +always @(dc_valid, dc_data) begin + if (dc_valid) + DcRhaValue <= dc_data; + else + DcRhaValue <= 32'h00000000; +end + + +always @(InValid, InPortId, DcRhaValue, VecBaseAddr, VecOffset) begin + if (InValid & InPortId[5]) + VecHandAddr <= DcRhaValue; + else if (InValid & ~InPortId[5]) + VecHandAddr <= VecBaseAddr + VecOffset; + else + VecHandAddr <= 32'h00000000; +end + + +always @(InValid, InPortId) begin + if (InValid) + OutPortId <= InPortId; + else + OutPortId <= 6'h00; +end + + +always @(InValid, InConfig) begin + if (InValid) + OutConfig <= InConfig; + else + OutConfig <= 13'h0000; +end + + +always @(posedge clk) begin + out_valid <= 1'b1; + out_data <= {VecHandAddr, OutConfig}; +end + + +endmodule diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_irq_mapper.sv b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_irq_mapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..4a7d913c1eadb1dcbfa2c18c61fbec60811badcf --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_irq_mapper.sv @@ -0,0 +1,58 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/08/11 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Altera IRQ Mapper +// +// Parameters +// NUM_RCVRS : 0 +// SENDER_IRW_WIDTH : 8 +// IRQ_MAP : +// +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module i-qsys_irq_mapper +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // IRQ Receivers + // ------------------- + + // ------------------- + // Command Source (Output) + // ------------------- + output reg [7 : 0] sender_irq +); + + initial sender_irq = 0; + + always @* begin + sender_irq = 0; + + end + +endmodule + + diff --git a/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_vic_0.v b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_vic_0.v new file mode 100644 index 0000000000000000000000000000000000000000..35053b1769095fc731eca62077c8f00f2636f418 --- /dev/null +++ b/examples/hdl4se_riscv/de1/qsys/i-qsys/synthesis/submodules/i-qsys_vic_0.v @@ -0,0 +1,229 @@ +// i-qsys_vic_0.v + +// This file was auto-generated from altera_vic_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 13.1 162 at 2021.08.28.08:45:04 + +`timescale 1 ps / 1 ps +module i-qsys_vic_0 ( + input wire clk_clk, // clk.clk + input wire clk_reset_reset, // clk_reset.reset + input wire [7:0] irq_input_irq, // irq_input.irq + input wire csr_access_read, // csr_access.read + input wire csr_access_write, // .write + input wire [7:0] csr_access_address, // .address + input wire [31:0] csr_access_writedata, // .writedata + output wire [31:0] csr_access_readdata, // .readdata + output wire interrupt_controller_out_valid, // interrupt_controller_out.valid + output wire [44:0] interrupt_controller_out_data // .data + ); + + wire vic_csr_out0_valid; // vic_csr:out0_valid -> vic_priority:in0_valid + wire [18:0] vic_csr_out0_data; // vic_csr:out0_data -> vic_priority:in0_data + wire vic_csr_out1_valid; // vic_csr:out1_valid -> vic_priority:in1_valid + wire [18:0] vic_csr_out1_data; // vic_csr:out1_data -> vic_priority:in1_data + wire vic_csr_out2_valid; // vic_csr:out2_valid -> vic_priority:in2_valid + wire [18:0] vic_csr_out2_data; // vic_csr:out2_data -> vic_priority:in2_data + wire vic_csr_out3_valid; // vic_csr:out3_valid -> vic_priority:in3_valid + wire [18:0] vic_csr_out3_data; // vic_csr:out3_data -> vic_priority:in3_data + wire vic_csr_out4_valid; // vic_csr:out4_valid -> vic_priority:in4_valid + wire [18:0] vic_csr_out4_data; // vic_csr:out4_data -> vic_priority:in4_data + wire vic_csr_out5_valid; // vic_csr:out5_valid -> vic_priority:in5_valid + wire [18:0] vic_csr_out5_data; // vic_csr:out5_data -> vic_priority:in5_data + wire vic_csr_out6_valid; // vic_csr:out6_valid -> vic_priority:in6_valid + wire [18:0] vic_csr_out6_data; // vic_csr:out6_data -> vic_priority:in6_data + wire vic_csr_out7_valid; // vic_csr:out7_valid -> vic_priority:in7_valid + wire [18:0] vic_csr_out7_data; // vic_csr:out7_data -> vic_priority:in7_data + wire vic_priority_out_valid; // vic_priority:pri_valid -> vic_vector:in_valid + wire [18:0] vic_priority_out_data; // vic_priority:pri_data -> vic_vector:in_data + wire vic_csr_control_valid; // vic_csr:control_valid -> vic_vector:control_valid + wire [34:0] vic_csr_control_data; // vic_csr:control_data -> vic_vector:control_data + wire vic_vector_status_valid; // vic_vector:status_valid -> vic_csr:status_valid + wire [37:0] vic_vector_status_data; // vic_vector:status_data -> vic_csr:status_data + + altera_vic_csr #( + .NUMBER_OF_INT_PORTS (8), + .RRS_WIDTH (6), + .RIL_WIDTH (4), + .DAISY_CHAIN_ENABLE (0) + ) vic_csr ( + .inr_i1_irq (irq_input_irq), // i1.irq + .avs_s1_read (csr_access_read), // s1.read + .avs_s1_write (csr_access_write), // .write + .avs_s1_address (csr_access_address), // .address + .avs_s1_writedata (csr_access_writedata), // .writedata + .avs_s1_readdata (csr_access_readdata), // .readdata + .out0_valid (vic_csr_out0_valid), // out0.valid + .out0_data (vic_csr_out0_data), // .data + .out1_valid (vic_csr_out1_valid), // out1.valid + .out1_data (vic_csr_out1_data), // .data + .out2_valid (vic_csr_out2_valid), // out2.valid + .out2_data (vic_csr_out2_data), // .data + .out3_valid (vic_csr_out3_valid), // out3.valid + .out3_data (vic_csr_out3_data), // .data + .out4_valid (vic_csr_out4_valid), // out4.valid + .out4_data (vic_csr_out4_data), // .data + .out5_valid (vic_csr_out5_valid), // out5.valid + .out5_data (vic_csr_out5_data), // .data + .out6_valid (vic_csr_out6_valid), // out6.valid + .out6_data (vic_csr_out6_data), // .data + .out7_valid (vic_csr_out7_valid), // out7.valid + .out7_data (vic_csr_out7_data), // .data + .control_valid (vic_csr_control_valid), // control.valid + .control_data (vic_csr_control_data), // .data + .status_valid (vic_vector_status_valid), // status.valid + .status_data (vic_vector_status_data), // .data + .clk (clk_clk), // clk.clk + .reset_n (~clk_reset_reset), // clk_reset.reset_n + .dc_in_valid (1'b0), // (terminated) + .dc_in_data (45'b000000000000000000000000000000000000000000000), // (terminated) + .dc_out_valid (), // (terminated) + .dc_out_data (), // (terminated) + .out8_valid (), // (terminated) + .out8_data (), // (terminated) + .out9_valid (), // (terminated) + .out9_data (), // (terminated) + .out10_valid (), // (terminated) + .out10_data (), // (terminated) + .out11_valid (), // (terminated) + .out11_data (), // (terminated) + .out12_valid (), // (terminated) + .out12_data (), // (terminated) + .out13_valid (), // (terminated) + .out13_data (), // (terminated) + .out14_valid (), // (terminated) + .out14_data (), // (terminated) + .out15_valid (), // (terminated) + .out15_data (), // (terminated) + .out16_valid (), // (terminated) + .out16_data (), // (terminated) + .out17_valid (), // (terminated) + .out17_data (), // (terminated) + .out18_valid (), // (terminated) + .out18_data (), // (terminated) + .out19_valid (), // (terminated) + .out19_data (), // (terminated) + .out20_valid (), // (terminated) + .out20_data (), // (terminated) + .out21_valid (), // (terminated) + .out21_data (), // (terminated) + .out22_valid (), // (terminated) + .out22_data (), // (terminated) + .out23_valid (), // (terminated) + .out23_data (), // (terminated) + .out24_valid (), // (terminated) + .out24_data (), // (terminated) + .out25_valid (), // (terminated) + .out25_data (), // (terminated) + .out26_valid (), // (terminated) + .out26_data (), // (terminated) + .out27_valid (), // (terminated) + .out27_data (), // (terminated) + .out28_valid (), // (terminated) + .out28_data (), // (terminated) + .out29_valid (), // (terminated) + .out29_data (), // (terminated) + .out30_valid (), // (terminated) + .out30_data (), // (terminated) + .out31_valid (), // (terminated) + .out31_data (), // (terminated) + .out32_valid (), // (terminated) + .out32_data () // (terminated) + ); + + altera_vic_priority #( + .NUMBER_OF_INT_PORTS (8), + .PRIORITY_WIDTH (4), + .DATA_WIDTH (19) + ) vic_priority ( + .clk (clk_clk), // clk.clk + .reset_n (~clk_reset_reset), // clk_reset.reset_n + .in0_valid (vic_csr_out0_valid), // in0.valid + .in0_data (vic_csr_out0_data), // .data + .in1_valid (vic_csr_out1_valid), // in1.valid + .in1_data (vic_csr_out1_data), // .data + .in2_valid (vic_csr_out2_valid), // in2.valid + .in2_data (vic_csr_out2_data), // .data + .in3_valid (vic_csr_out3_valid), // in3.valid + .in3_data (vic_csr_out3_data), // .data + .in4_valid (vic_csr_out4_valid), // in4.valid + .in4_data (vic_csr_out4_data), // .data + .in5_valid (vic_csr_out5_valid), // in5.valid + .in5_data (vic_csr_out5_data), // .data + .in6_valid (vic_csr_out6_valid), // in6.valid + .in6_data (vic_csr_out6_data), // .data + .in7_valid (vic_csr_out7_valid), // in7.valid + .in7_data (vic_csr_out7_data), // .data + .pri_valid (vic_priority_out_valid), // out.valid + .pri_data (vic_priority_out_data), // .data + .in8_valid (1'b0), // (terminated) + .in8_data (19'b0000000000000000000), // (terminated) + .in9_valid (1'b0), // (terminated) + .in9_data (19'b0000000000000000000), // (terminated) + .in10_valid (1'b0), // (terminated) + .in10_data (19'b0000000000000000000), // (terminated) + .in11_valid (1'b0), // (terminated) + .in11_data (19'b0000000000000000000), // (terminated) + .in12_valid (1'b0), // (terminated) + .in12_data (19'b0000000000000000000), // (terminated) + .in13_valid (1'b0), // (terminated) + .in13_data (19'b0000000000000000000), // (terminated) + .in14_valid (1'b0), // (terminated) + .in14_data (19'b0000000000000000000), // (terminated) + .in15_valid (1'b0), // (terminated) + .in15_data (19'b0000000000000000000), // (terminated) + .in16_valid (1'b0), // (terminated) + .in16_data (19'b0000000000000000000), // (terminated) + .in17_valid (1'b0), // (terminated) + .in17_data (19'b0000000000000000000), // (terminated) + .in18_valid (1'b0), // (terminated) + .in18_data (19'b0000000000000000000), // (terminated) + .in19_valid (1'b0), // (terminated) + .in19_data (19'b0000000000000000000), // (terminated) + .in20_valid (1'b0), // (terminated) + .in20_data (19'b0000000000000000000), // (terminated) + .in21_valid (1'b0), // (terminated) + .in21_data (19'b0000000000000000000), // (terminated) + .in22_valid (1'b0), // (terminated) + .in22_data (19'b0000000000000000000), // (terminated) + .in23_valid (1'b0), // (terminated) + .in23_data (19'b0000000000000000000), // (terminated) + .in24_valid (1'b0), // (terminated) + .in24_data (19'b0000000000000000000), // (terminated) + .in25_valid (1'b0), // (terminated) + .in25_data (19'b0000000000000000000), // (terminated) + .in26_valid (1'b0), // (terminated) + .in26_data (19'b0000000000000000000), // (terminated) + .in27_valid (1'b0), // (terminated) + .in27_data (19'b0000000000000000000), // (terminated) + .in28_valid (1'b0), // (terminated) + .in28_data (19'b0000000000000000000), // (terminated) + .in29_valid (1'b0), // (terminated) + .in29_data (19'b0000000000000000000), // (terminated) + .in30_valid (1'b0), // (terminated) + .in30_data (19'b0000000000000000000), // (terminated) + .in31_valid (1'b0), // (terminated) + .in31_data (19'b0000000000000000000), // (terminated) + .in32_valid (1'b0), // (terminated) + .in32_data (19'b0000000000000000000) // (terminated) + ); + + altera_vic_vector #( + .DAISY_CHAIN_ENABLE (0) + ) vic_vector ( + .clk (clk_clk), // clk.clk + .reset_n (~clk_reset_reset), // clk_reset.reset_n + .in_valid (vic_priority_out_valid), // in.valid + .in_data (vic_priority_out_data), // .data + .control_valid (vic_csr_control_valid), // control.valid + .control_data (vic_csr_control_data), // .data + .status_valid (vic_vector_status_valid), // status.valid + .status_data (vic_vector_status_data), // .data + .out_valid (interrupt_controller_out_valid), // out.valid + .out_data (interrupt_controller_out_data), // .data + .dc_valid (1'b0), // (terminated) + .dc_data (32'b00000000000000000000000000000000) // (terminated) + ); + +endmodule diff --git a/examples/hdl4se_riscv/de1/vsim.wlf b/examples/hdl4se_riscv/de1/vsim.wlf index d6cae735293234edc55d2febd5aea57de9c160b3..e15c9dba1a27ab8d59a6f7782ae232c7d21fbc76 100644 Binary files a/examples/hdl4se_riscv/de1/vsim.wlf and b/examples/hdl4se_riscv/de1/vsim.wlf differ diff --git a/examples/hdl4se_riscv/test_code/main_v2.c b/examples/hdl4se_riscv/test_code/main_v2.c new file mode 100644 index 0000000000000000000000000000000000000000..f6f7bff8497cf82787e941cb6405ddd198419e0c --- /dev/null +++ b/examples/hdl4se_riscv/test_code/main_v2.c @@ -0,0 +1,74 @@ + + +const unsigned int segcode[10] = +{ + 0x3F, + 0x06, + 0x5B,// 8'b01011011, + 0x4F,// 8'b01001111, + 0x66,// 8'b01100110, + 0x6d,// 8'b01101101, + 0x7d,// 8'b01111101, + 0x07,// 8'b00000111, + 0x7f,// 8'b01111111, + 0x6f,// 8'b01101111, +}; + +unsigned int num2seg(unsigned int num) +{ + return segcode[num % 10]; +} + +int main(int argc, char* argv[]) +{ + unsigned long long count, ctemp; + int countit = 1; + unsigned int* ledkey = (unsigned int*)0xF0000000; + unsigned int* leddata = (unsigned int*)0xf0000010; + unsigned int* uart = (unsigned int*)0xf0000100; + + count = 0; + leddata[0] = 0x6f7f077d; + leddata[1] = 0x6d664f5b; + uart[4] = 100000000 / 115200;/* set baudrate to 115200 */ + uart[1] = 'H'; + uart[1] = '\n'; + do { + unsigned int key; + unsigned int uartstate; + uartstate = uart[2]; + if (uartstate & 0x80) { /*rrdy*/ + uart[1] = uart[0]; /* writeback */ + continue; + } + key = *ledkey; + if (key & 1) { + count = 0; + } + else if (key & 2) { + countit = 0; + } + else if (key & 4) { + countit = 1; + } + if (countit) + count++; + + ctemp = count; + leddata[0] = num2seg(ctemp) | + ((num2seg(ctemp / 10ll)) << 8) | + ((num2seg(ctemp / 100ll)) << 16) | + ((num2seg(ctemp / 1000ll)) << 24); + ctemp /= 10000ll; + leddata[1] = num2seg(ctemp) | + ((num2seg(ctemp / 10ll)) << 8) | + ((num2seg(ctemp / 100ll)) << 16) | + ((num2seg(ctemp / 1000ll)) << 24); + ctemp /= 10000ll; + leddata[2] = num2seg(ctemp) | + ((num2seg(ctemp / 10ll)) << 8); + + + } while (1); + return 1; +}