de1_riscv_0.v

//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

`define USECLOCK50_1

module de1_riscv(

	//////////// ADC //////////
	output		          		ADC_CONVST,
	output		          		ADC_DIN,
	input 		          		ADC_DOUT,
	output		          		ADC_SCLK,

	//////////// Audio //////////
	input 		          		AUD_ADCDAT,
	inout 		          		AUD_ADCLRCK,
	inout 		          		AUD_BCLK,
	output		          		AUD_DACDAT,
	inout 		          		AUD_DACLRCK,
	output		          		AUD_XCK,

	//////////// CLOCK //////////
	input 		          		CLOCK2_50,
	input 		          		CLOCK3_50,
	input 		          		CLOCK4_50,
	input 		          		CLOCK_50,

	//////////// SDRAM //////////
	output		    [12:0]		DRAM_ADDR,
	output		     [1:0]		DRAM_BA,
	output		          		DRAM_CAS_N,
	output		          		DRAM_CKE,
	output		          		DRAM_CLK,
	output		          		DRAM_CS_N,
	inout 		    [15:0]		DRAM_DQ,
	output		          		DRAM_LDQM,
	output		          		DRAM_RAS_N,
	output		          		DRAM_UDQM,
	output		          		DRAM_WE_N,

	//////////// I2C for Audio and Video-In //////////
	output		          		FPGA_I2C_SCLK,
	inout 		          		FPGA_I2C_SDAT,

	//////////// SEG7 //////////
	output		     [6:0]		HEX0,
	output		     [6:0]		HEX1,
	output		     [6:0]		HEX2,
	output		     [6:0]		HEX3,
	output		     [6:0]		HEX4,
	output		     [6:0]		HEX5,

	//////////// IR //////////
	input 		          		IRDA_RXD,
	output		          		IRDA_TXD,

	//////////// KEY //////////
	input 		     [3:0]		KEY,

	//////////// LED //////////
	output		     [9:0]		LEDR,

	//////////// PS2 //////////
	inout 		          		PS2_CLK,
	inout 		          		PS2_CLK2,
	inout 		          		PS2_DAT,
	inout 		          		PS2_DAT2,

	//////////// SW //////////
	input 		     [9:0]		SW,

	//////////// Video-In //////////
	input 		          		TD_CLK27,
	input 		     [7:0]		TD_DATA,
	input 		          		TD_HS,
	output		          		TD_RESET_N,
	input 		          		TD_VS,

	//////////// VGA //////////
	output		          		VGA_BLANK_N,
	output		     [7:0]		VGA_B,
	output		          		VGA_CLK,
	output		     [7:0]		VGA_G,
	output		          		VGA_HS,
	output		     [7:0]		VGA_R,
	output		          		VGA_SYNC_N,
	output		          		VGA_VS,

	//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
	inout 		    [35:0]		GPIO
);

`ifdef USECLOCK50
	wire wClk = CLOCK_50;
`else
	wire clk100MHz, clk75MHz, clklocked;
	clk100M clk100(.refclk(CLOCK_50),
	               .rst(~KEY[3]),
				   .outclk_0(clk100MHz), 
				   .outclk_1(clk75MHz),
				   .locked(clklocked));
				   
	wire wClk = clk100MHz;
`endif
	wire nwReset = KEY[3];

    wire wWrite, wRead;
    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
    wire [3:0]  bWriteMask;

	assign bReadDataKey = {18'b0, KEY, SW};

	reg readcmd;
	reg [31:0] readaddr;

	wire wRead_out = readcmd;
    wire [31:0] bReadAddr_out = readaddr;


	always @(posedge wClk) begin
		if (!nwReset) begin
			readcmd <= 1'b0;
			readaddr <= 32'b0;
		end else begin
			readcmd <= wRead;
			readaddr <= bReadAddr;
		end
	end
    
    assign bReadData = 
            ((bReadAddr_out & 32'hffffff00) == 32'hf0000000) ? bReadDataKey : (
            ((bReadAddr_out & 32'hffffc000) == 32'h00000000) ? bReadDataRam : (0)
            );

    wire [10:0] ramaddr;
    assign ramaddr = wWrite?bWriteAddr[12:2]:bReadAddr[12:2];

    wire [4:0]  regno;
    wire [3:0]  regena;
    wire [31:0] regwrdata;
    wire        regwren;
    wire [31:0] regrddata;

    regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
    ram8kb     ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hffffc000) == 0)?wWrite:1'b0, bReadDataRam);
    //digitled   led(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadDataKey);
	riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
                regno, regena, regwrdata, regwren, regrddata);

	reg [6:0] led0;
	reg [6:0] led1;
	reg [6:0] led2;
	reg [6:0] led3;
	reg [6:0] led4;
	reg [6:0] led5;
	assign HEX0 = ~led0;
	assign HEX1 = ~led1;
	assign HEX2 = ~led2;
	assign HEX3 = ~led3;
	assign HEX4 = ~led4;
	assign HEX5 = ~led5;

	

	always @(posedge wClk) begin
		if (!nwReset) begin
			led0 <= 8'h3f;
			led1 <= 8'h3f;
			led2 <= 8'h3f;
			led3 <= 8'h3f;
			led4 <= 8'h3f;
			led5 <= 8'h3f;
		end else begin
			if (SW[8]) begin
				led0 <= 8'h06;
				led1 <= 8'h06;
				led2 <= 8'h06;
				led3 <= 8'h07;
				led4 <= 8'h07;
				led5 <= 8'h07;				
			end
			else if (SW[9]) begin
				led0 <= 8'h3f;
				led1 <= 8'h06;
				led2 <= 8'h5b;
				led3 <= 8'h4f;
				led4 <= 8'h66;
				led5 <= 8'h6d;				
			end
			else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin
				if (bWriteAddr[7:0] == 8'h10) begin
					led0 <= bWriteData[6:0];
					led1 <= bWriteData[14:8];
					led2 <= bWriteData[22:16];
					led3 <= bWriteData[30:24];
				end else if (bWriteAddr[7:0] == 8'h14) begin
					led4 <= bWriteData[6:0];
					led5 <= bWriteData[14:8];
				end
			end
		end
	end
	
endmodule