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202108270827

上级 a33968b0
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examples/hdl4se_riscv/de1/PLLJ_PLLSPE_INFO.txt
浏览文件 @ 03db2b6f
PLL_Name vga_pll_0002:vgaclock|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
PLLJITTER 27
PLL_Name clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
PLLJITTER 21
PLLSPEmax 50
PLLSPEmin -50
PLL_Name vga_pll_0002:vgaclock|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER
PLL_Name clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER
PLLJITTER NA
PLLSPEmax NA
PLLSPEmin NA
......
examples/hdl4se_riscv/de1/clk/clk100M.bsf 0 → 100644
浏览文件 @ 03db2b6f
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 184)
(text "clk100M" (rect 57 -1 88 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 20 180)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 48 112)(line_width 1))
)
(port
(pt 160 72)
(output)
(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
(line (pt 160 72)(pt 112 72)(line_width 1))
)
(port
(pt 160 112)
(output)
(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
(line (pt 160 112)(pt 112 112)(line_width 1))
)
(port
(pt 160 152)
(output)
(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
(text "locked" (rect 127 141 163 152)(font "Arial" (font_size 8)))
(line (pt 160 152)(pt 112 152)(line_width 1))
)
(drawing
(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
(text "locked" (rect 113 123 262 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 82 147 200 304)(font "Arial" (color 0 0 0)))
(text " altera_pll " (rect 118 168 308 346)(font "Arial" ))
(line (pt 49 52)(pt 49 76)(line_width 1))
(line (pt 50 52)(pt 50 76)(line_width 1))
(line (pt 49 92)(pt 49 116)(line_width 1))
(line (pt 50 92)(pt 50 116)(line_width 1))
(line (pt 111 52)(pt 111 76)(line_width 1))
(line (pt 110 52)(pt 110 76)(line_width 1))
(line (pt 111 92)(pt 111 116)(line_width 1))
(line (pt 110 92)(pt 110 116)(line_width 1))
(line (pt 111 132)(pt 111 156)(line_width 1))
(line (pt 110 132)(pt 110 156)(line_width 1))
(line (pt 48 32)(pt 112 32)(line_width 1))
(line (pt 112 32)(pt 112 168)(line_width 1))
(line (pt 48 168)(pt 112 168)(line_width 1))
(line (pt 48 32)(pt 48 168)(line_width 1))
(line (pt 0 0)(pt 160 0)(line_width 1))
(line (pt 160 0)(pt 160 184)(line_width 1))
(line (pt 0 184)(pt 160 184)(line_width 1))
(line (pt 0 0)(pt 0 184)(line_width 1))
)
)
examples/hdl4se_riscv/de1/clk/clk100M.cmp 0 → 100644
浏览文件 @ 03db2b6f
component clk100M is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
locked : out std_logic -- export
);
end component clk100M;
examples/hdl4se_riscv/de1/clk/clk100M.ppf 0 → 100644
浏览文件 @ 03db2b6f
<?xml version="1.0" encoding="UTF-8"?>
<pinplan
variation_name="clk100M"
megafunction_name="ALTERA_PLL"
intended_family="Cyclone V"
specifies="all_ports">
<global>
<pin name="refclk" direction="input" scope="external" />
<pin name="rst" direction="input" scope="external" />
<pin name="outclk_0" direction="output" scope="external" />
<pin name="outclk_1" direction="output" scope="external" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
examples/hdl4se_riscv/de1/clk/clk100M.qip 0 → 100644
浏览文件 @ 03db2b6f
set_global_assignment -entity "clk100M" -library "clk100M" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "clk100M" -library "clk100M" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "clk100M" -library "clk100M" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "clk100M" -name MISC_FILE [file join $::quartus(qip_path) "clk100M.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "clk100M" -name VERILOG_FILE [file join $::quartus(qip_path) "clk100M.v"]
set_global_assignment -library "clk100M" -name VERILOG_FILE [file join $::quartus(qip_path) "clk100M/clk100M_0002.v"]
set_global_assignment -library "clk100M" -name QIP_FILE [file join $::quartus(qip_path) "clk100M/clk100M_0002.qip"]
set_global_assignment -entity "clk100M_0002" -library "clk100M" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "clk100M_0002" -library "clk100M" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "clk100M_0002" -library "clk100M" -name IP_TOOL_ENV "mwpim"
examples/hdl4se_riscv/de1/clk/clk100M.sip 0 → 100644
浏览文件 @ 03db2b6f
set_global_assignment -entity "clk100M" -library "lib_clk100M" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "clk100M" -library "lib_clk100M" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "clk100M" -library "lib_clk100M" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lib_clk100M" -name SPD_FILE [file join $::quartus(sip_path) "clk100M.spd"]
set_global_assignment -library "lib_clk100M" -name MISC_FILE [file join $::quartus(sip_path) "clk100M_sim/clk100M.vo"]
examples/hdl4se_riscv/de1/clk/clk100M.spd 0 → 100644
浏览文件 @ 03db2b6f
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file path="clk100M_sim/clk100M.vo" type="VERILOG" />
<topLevel name="clk100M" />
<deviceFamily name="cyclonev" />
</simPackage>
examples/hdl4se_riscv/de1/clk/clk100M.v 0 → 100644
浏览文件 @ 03db2b6f
// megafunction wizard: %Altera PLL v13.1%
// GENERATION: XML
// clk100M.v
// Generated using ACDS version 13.1 162 at 2021.08.27.08:01:33
`timescale 1 ps / 1 ps
module clk100M (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
clk100M_0002 clk100m_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2021 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="13.1" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="400.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="75.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : clk100M.vo
// RELATED_FILES: clk100M.v, clk100M_0002.v
examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.qip 0 → 100644
浏览文件 @ 03db2b6f
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*clk100M_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET OFF -to "*clk100M_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*clk100M_0002*|altera_pll:altera_pll_i*|*"
examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v 0 → 100644
浏览文件 @ 03db2b6f
`timescale 1ns/10ps
module clk100M_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("400.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("75.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl 0 → 100644
浏览文件 @ 03db2b6f
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# Auto-generated simulation script
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "clk100M"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/altera/13.1/quartus/"
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
set Aldec "Riviera"
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
set Aldec "Active"
}
if { [ string match "Active" $Aldec ] } {
scripterconf -tcl
createdesign "$TOP_LEVEL_NAME" "."
opendesign "$TOP_LEVEL_NAME"
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries
ensure_lib ./libraries/work
vmap work ./libraries/work
ensure_lib ./libraries/altera_ver
vmap altera_ver ./libraries/altera_ver
ensure_lib ./libraries/lpm_ver
vmap lpm_ver ./libraries/lpm_ver
ensure_lib ./libraries/sgate_ver
vmap sgate_ver ./libraries/sgate_ver
ensure_lib ./libraries/altera_mf_ver
vmap altera_mf_ver ./libraries/altera_mf_ver
ensure_lib ./libraries/altera_lnsim_ver
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
ensure_lib ./libraries/cyclonev_ver
vmap cyclonev_ver ./libraries/cyclonev_ver
ensure_lib ./libraries/cyclonev_hssi_ver
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
ensure_lib ./libraries/cyclonev_pcie_hip_ver
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
vlog +define+SKIP_KEYWORDS_PRAGMA "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
vlog "$QSYS_SIMDIR/clk100M.vo"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with -dbg -O2 option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -dbg -O2
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Qsys base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
}
file_copy
h
examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/cds.lib 0 → 100644
浏览文件 @ 03db2b6f
DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
DEFINE work ./libraries/work/
DEFINE altera_ver ./libraries/altera_ver/
DEFINE lpm_ver ./libraries/lpm_ver/
DEFINE sgate_ver ./libraries/sgate_ver/
DEFINE altera_mf_ver ./libraries/altera_mf_ver/
DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/
DEFINE cyclonev_ver ./libraries/cyclonev_ver/
DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh 0 → 100644
浏览文件 @ 03db2b6f
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# ncsim - auto-generated simulation script
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="clk100M"
QSYS_SIMDIR="./../"
QUARTUS_INSTALL_DIR="C:/altera/13.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/altera_lnsim_ver/
mkdir -p ./libraries/cyclonev_ver/
mkdir -p ./libraries/cyclonev_hssi_ver/
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
ncvlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
ncvlog "$QSYS_SIMDIR/clk100M.vo"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
fi
examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo 0 → 100644
浏览文件 @ 03db2b6f
//IP Functional Simulation Model
//VERSION_BEGIN 13.1 cbx_mgl 2013:10:24:09:16:30:SJ cbx_simgen 2013:10:24:09:15:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).
//synopsys translate_off
//synthesis_resources = altera_pll 1
`timescale 1 ps / 1 ps
module clk100M
(
locked,
outclk_0,
outclk_1,
refclk,
rst) /* synthesis synthesis_clearbox=1 */;
output locked;
output outclk_0;
output outclk_1;
input refclk;
input rst;
wire wire_clk100m_altera_pll_altera_pll_i_1096_locked;
wire [1:0] wire_clk100m_altera_pll_altera_pll_i_1096_outclk;
altera_pll clk100m_altera_pll_altera_pll_i_1096
(
.fbclk(1'b0),
.locked(wire_clk100m_altera_pll_altera_pll_i_1096_locked),
.outclk(wire_clk100m_altera_pll_altera_pll_i_1096_outclk),
.refclk(refclk),
.rst(rst));
defparam
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en0 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en1 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en10 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en11 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en12 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en13 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en14 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en15 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en16 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en17 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en2 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en3 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en4 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en5 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en6 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en7 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en8 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en9 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div0 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div1 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div10 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div11 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div12 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div13 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div14 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div15 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div16 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div17 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div2 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div3 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div4 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div5 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div6 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div7 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div8 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div9 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src0 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src1 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src10 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src11 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src12 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src13 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src14 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src15 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src16 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src17 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src2 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src3 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src4 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src5 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src6 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src7 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src8 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src9 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div0 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div1 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div10 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div11 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div12 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div13 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div14 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div15 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div16 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div17 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div2 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div3 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div4 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div5 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div6 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div7 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div8 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div9 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en0 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en1 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en10 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en11 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en12 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en13 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en14 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en15 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en16 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en17 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en2 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en3 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en4 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en5 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en6 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en7 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en8 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en9 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst0 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst1 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst10 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst11 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst12 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst13 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst14 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst15 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst16 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst17 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst2 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst3 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst4 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst5 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst6 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst7 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst8 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst9 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst0 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst1 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst10 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst11 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst12 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst13 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst14 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst15 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst16 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst17 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst2 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst3 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst4 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst5 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst6 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst7 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst8 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst9 = 1,
clk100m_altera_pll_altera_pll_i_1096.data_rate = 0,
clk100m_altera_pll_altera_pll_i_1096.deserialization_factor = 4,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle0 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle1 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle10 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle11 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle12 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle13 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle14 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle15 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle16 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle17 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle2 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle3 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle4 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle5 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle6 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle7 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle8 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle9 = 50,
clk100m_altera_pll_altera_pll_i_1096.fractional_vco_multiplier = "false",
clk100m_altera_pll_altera_pll_i_1096.m_cnt_bypass_en = "false",
clk100m_altera_pll_altera_pll_i_1096.m_cnt_hi_div = 1,
clk100m_altera_pll_altera_pll_i_1096.m_cnt_lo_div = 1,
clk100m_altera_pll_altera_pll_i_1096.m_cnt_odd_div_duty_en = "false",
clk100m_altera_pll_altera_pll_i_1096.mimic_fbclk_type = "gclk",
clk100m_altera_pll_altera_pll_i_1096.n_cnt_bypass_en = "false",
clk100m_altera_pll_altera_pll_i_1096.n_cnt_hi_div = 1,
clk100m_altera_pll_altera_pll_i_1096.n_cnt_lo_div = 1,
clk100m_altera_pll_altera_pll_i_1096.n_cnt_odd_div_duty_en = "false",
clk100m_altera_pll_altera_pll_i_1096.number_of_clocks = 2,
clk100m_altera_pll_altera_pll_i_1096.operation_mode = "direct",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "400.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency1 = "75.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency10 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency11 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency12 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency13 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency14 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency15 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency16 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency17 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency2 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency3 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency4 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency5 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency6 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency7 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency8 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency9 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.phase_shift0 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift1 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift10 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift11 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift12 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift13 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift14 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift15 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift16 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift17 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift2 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift3 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift4 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift5 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift6 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift7 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift8 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift9 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.pll_auto_clk_sw_en = "false",
clk100m_altera_pll_altera_pll_i_1096.pll_bwctrl = 0,
clk100m_altera_pll_altera_pll_i_1096.pll_clk_loss_sw_en = "false",
clk100m_altera_pll_altera_pll_i_1096.pll_clk_sw_dly = 0,
clk100m_altera_pll_altera_pll_i_1096.pll_clkin_0_src = "clk_0",
clk100m_altera_pll_altera_pll_i_1096.pll_clkin_1_src = "clk_0",
clk100m_altera_pll_altera_pll_i_1096.pll_cp_current = 0,
clk100m_altera_pll_altera_pll_i_1096.pll_dsm_out_sel = "1st_order",
clk100m_altera_pll_altera_pll_i_1096.pll_fbclk_mux_1 = "glb",
clk100m_altera_pll_altera_pll_i_1096.pll_fbclk_mux_2 = "fb_1",
clk100m_altera_pll_altera_pll_i_1096.pll_fractional_cout = 24,
clk100m_altera_pll_altera_pll_i_1096.pll_fractional_division = 1,
clk100m_altera_pll_altera_pll_i_1096.pll_m_cnt_in_src = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.pll_manu_clk_sw_en = "false",
clk100m_altera_pll_altera_pll_i_1096.pll_output_clk_frequency = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.pll_subtype = "General",
clk100m_altera_pll_altera_pll_i_1096.pll_type = "General",
clk100m_altera_pll_altera_pll_i_1096.pll_vco_div = 1,
clk100m_altera_pll_altera_pll_i_1096.pll_vcoph_div = 1,
clk100m_altera_pll_altera_pll_i_1096.refclk1_frequency = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.reference_clock_frequency = "50.0 MHz",
clk100m_altera_pll_altera_pll_i_1096.sim_additional_refclk_cycles_to_lock = 0;
assign
locked = wire_clk100m_altera_pll_altera_pll_i_1096_locked,
outclk_0 = wire_clk100m_altera_pll_altera_pll_i_1096_outclk[0],
outclk_1 = wire_clk100m_altera_pll_altera_pll_i_1096_outclk[1];
endmodule //clk100M
//synopsys translate_on
//VALID FILE
examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl 0 → 100644
浏览文件 @ 03db2b6f
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# Auto-generated simulation script
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "clk100M"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/altera/13.1/quartus/"
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries/
ensure_lib ./libraries/work/
vmap work ./libraries/work/
vmap work_lib ./libraries/work/
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
ensure_lib ./libraries/altera_ver/
vmap altera_ver ./libraries/altera_ver/
ensure_lib ./libraries/lpm_ver/
vmap lpm_ver ./libraries/lpm_ver/
ensure_lib ./libraries/sgate_ver/
vmap sgate_ver ./libraries/sgate_ver/
ensure_lib ./libraries/altera_mf_ver/
vmap altera_mf_ver ./libraries/altera_mf_ver/
ensure_lib ./libraries/altera_lnsim_ver/
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
ensure_lib ./libraries/cyclonev_ver/
vmap cyclonev_ver ./libraries/cyclonev_ver/
ensure_lib ./libraries/cyclonev_hssi_ver/
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
ensure_lib ./libraries/cyclonev_pcie_hip_ver/
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
}
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
}
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
vlog "$QSYS_SIMDIR/clk100M.vo"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim -t ps $ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with novopt option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -novopt -t ps $ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -novopt
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with novopt option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Qsys base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
}
file_copy
h
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh 0 → 100644
浏览文件 @ 03db2b6f
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# vcs - auto-generated simulation script
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="clk100M"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/altera/13.1/quartus/"
SKIP_FILE_COPY=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# copy RAM/ROM files to simulation directory
vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
$QSYS_SIMDIR/clk100M.vo \
-top $TOP_LEVEL_NAME
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/synopsys_sim.setup 0 → 100644
浏览文件 @ 03db2b6f
WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera_ver: ./libraries/altera_ver/
lpm_ver: ./libraries/lpm_ver/
sgate_ver: ./libraries/sgate_ver/
altera_mf_ver: ./libraries/altera_mf_ver/
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
cyclonev_ver: ./libraries/cyclonev_ver/
cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/
cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
LIBRARY_SCAN = TRUE
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh 0 → 100644
浏览文件 @ 03db2b6f
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# vcsmx - auto-generated simulation script
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="clk100M"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/altera/13.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/altera_lnsim_ver/
mkdir -p ./libraries/cyclonev_ver/
mkdir -p ./libraries/cyclonev_hssi_ver/
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlogan +v2k -sverilog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
vlogan +v2k "$QSYS_SIMDIR/clk100M.vo"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi
examples/hdl4se_riscv/de1/clk100M.xml 0 → 100644
浏览文件 @ 03db2b6f
<?xml version="1.0"?>
<instance entity-name="altera_pll" version="13.1" >
<generic name="debug_print_output" value="false" />
<generic name="debug_use_rbc_taf_method" value="false" />
<generic name="device_family" value="Cyclone V" />
<generic name="device" value="Unknown" />
<generic name="gui_device_speed_grade" value="2" />
<generic name="gui_pll_mode" value="Integer-N PLL" />
<generic name="gui_reference_clock_frequency" value="50.0" />
<generic name="gui_channel_spacing" value="0.0" />
<generic name="gui_operation_mode" value="direct" />
<generic name="gui_feedback_clock" value="Global Clock" />
<generic name="gui_fractional_cout" value="32" />
<generic name="gui_dsm_out_sel" value="1st_order" />
<generic name="gui_use_locked" value="true" />
<generic name="gui_en_adv_params" value="false" />
<generic name="gui_number_of_clocks" value="2" />
<generic name="gui_multiply_factor" value="1" />
<generic name="gui_frac_multiply_factor" value="1" />
<generic name="gui_divide_factor_n" value="1" />
<generic name="gui_cascade_counter0" value="false" />
<generic name="gui_output_clock_frequency0" value="100.0" />
<generic name="gui_divide_factor_c0" value="1" />
<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
<generic name="gui_ps_units0" value="ps" />
<generic name="gui_phase_shift0" value="0" />
<generic name="gui_phase_shift_deg0" value="0.0" />
<generic name="gui_actual_phase_shift0" value="0" />
<generic name="gui_duty_cycle0" value="50" />
<generic name="gui_cascade_counter1" value="false" />
<generic name="gui_output_clock_frequency1" value="75.0" />
<generic name="gui_divide_factor_c1" value="1" />
<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
<generic name="gui_ps_units1" value="ps" />
<generic name="gui_phase_shift1" value="0" />
<generic name="gui_phase_shift_deg1" value="0.0" />
<generic name="gui_actual_phase_shift1" value="0" />
<generic name="gui_duty_cycle1" value="50" />
<generic name="gui_cascade_counter2" value="false" />
<generic name="gui_output_clock_frequency2" value="100.0" />
<generic name="gui_divide_factor_c2" value="1" />
<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
<generic name="gui_ps_units2" value="ps" />
<generic name="gui_phase_shift2" value="0" />
<generic name="gui_phase_shift_deg2" value="0.0" />
<generic name="gui_actual_phase_shift2" value="0" />
<generic name="gui_duty_cycle2" value="50" />
<generic name="gui_cascade_counter3" value="false" />
<generic name="gui_output_clock_frequency3" value="100.0" />
<generic name="gui_divide_factor_c3" value="1" />
<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
<generic name="gui_ps_units3" value="ps" />
<generic name="gui_phase_shift3" value="0" />
<generic name="gui_phase_shift_deg3" value="0.0" />
<generic name="gui_actual_phase_shift3" value="0" />
<generic name="gui_duty_cycle3" value="50" />
<generic name="gui_cascade_counter4" value="false" />
<generic name="gui_output_clock_frequency4" value="100.0" />
<generic name="gui_divide_factor_c4" value="1" />
<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
<generic name="gui_ps_units4" value="ps" />
<generic name="gui_phase_shift4" value="0" />
<generic name="gui_phase_shift_deg4" value="0.0" />
<generic name="gui_actual_phase_shift4" value="0" />
<generic name="gui_duty_cycle4" value="50" />
<generic name="gui_cascade_counter5" value="false" />
<generic name="gui_output_clock_frequency5" value="100.0" />
<generic name="gui_divide_factor_c5" value="1" />
<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
<generic name="gui_ps_units5" value="ps" />
<generic name="gui_phase_shift5" value="0" />
<generic name="gui_phase_shift_deg5" value="0.0" />
<generic name="gui_actual_phase_shift5" value="0" />
<generic name="gui_duty_cycle5" value="50" />
<generic name="gui_cascade_counter6" value="false" />
<generic name="gui_output_clock_frequency6" value="100.0" />
<generic name="gui_divide_factor_c6" value="1" />
<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
<generic name="gui_ps_units6" value="ps" />
<generic name="gui_phase_shift6" value="0" />
<generic name="gui_phase_shift_deg6" value="0.0" />
<generic name="gui_actual_phase_shift6" value="0" />
<generic name="gui_duty_cycle6" value="50" />
<generic name="gui_cascade_counter7" value="false" />
<generic name="gui_output_clock_frequency7" value="100.0" />
<generic name="gui_divide_factor_c7" value="1" />
<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
<generic name="gui_ps_units7" value="ps" />
<generic name="gui_phase_shift7" value="0" />
<generic name="gui_phase_shift_deg7" value="0.0" />
<generic name="gui_actual_phase_shift7" value="0" />
<generic name="gui_duty_cycle7" value="50" />
<generic name="gui_cascade_counter8" value="false" />
<generic name="gui_output_clock_frequency8" value="100.0" />
<generic name="gui_divide_factor_c8" value="1" />
<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
<generic name="gui_ps_units8" value="ps" />
<generic name="gui_phase_shift8" value="0" />
<generic name="gui_phase_shift_deg8" value="0.0" />
<generic name="gui_actual_phase_shift8" value="0" />
<generic name="gui_duty_cycle8" value="50" />
<generic name="gui_cascade_counter9" value="false" />
<generic name="gui_output_clock_frequency9" value="100.0" />
<generic name="gui_divide_factor_c9" value="1" />
<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
<generic name="gui_ps_units9" value="ps" />
<generic name="gui_phase_shift9" value="0" />
<generic name="gui_phase_shift_deg9" value="0.0" />
<generic name="gui_actual_phase_shift9" value="0" />
<generic name="gui_duty_cycle9" value="50" />
<generic name="gui_cascade_counter10" value="false" />
<generic name="gui_output_clock_frequency10" value="100.0" />
<generic name="gui_divide_factor_c10" value="1" />
<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
<generic name="gui_ps_units10" value="ps" />
<generic name="gui_phase_shift10" value="0" />
<generic name="gui_phase_shift_deg10" value="0.0" />
<generic name="gui_actual_phase_shift10" value="0" />
<generic name="gui_duty_cycle10" value="50" />
<generic name="gui_cascade_counter11" value="false" />
<generic name="gui_output_clock_frequency11" value="100.0" />
<generic name="gui_divide_factor_c11" value="1" />
<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
<generic name="gui_ps_units11" value="ps" />
<generic name="gui_phase_shift11" value="0" />
<generic name="gui_phase_shift_deg11" value="0.0" />
<generic name="gui_actual_phase_shift11" value="0" />
<generic name="gui_duty_cycle11" value="50" />
<generic name="gui_cascade_counter12" value="false" />
<generic name="gui_output_clock_frequency12" value="100.0" />
<generic name="gui_divide_factor_c12" value="1" />
<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
<generic name="gui_ps_units12" value="ps" />
<generic name="gui_phase_shift12" value="0" />
<generic name="gui_phase_shift_deg12" value="0.0" />
<generic name="gui_actual_phase_shift12" value="0" />
<generic name="gui_duty_cycle12" value="50" />
<generic name="gui_cascade_counter13" value="false" />
<generic name="gui_output_clock_frequency13" value="100.0" />
<generic name="gui_divide_factor_c13" value="1" />
<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
<generic name="gui_ps_units13" value="ps" />
<generic name="gui_phase_shift13" value="0" />
<generic name="gui_phase_shift_deg13" value="0.0" />
<generic name="gui_actual_phase_shift13" value="0" />
<generic name="gui_duty_cycle13" value="50" />
<generic name="gui_cascade_counter14" value="false" />
<generic name="gui_output_clock_frequency14" value="100.0" />
<generic name="gui_divide_factor_c14" value="1" />
<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
<generic name="gui_ps_units14" value="ps" />
<generic name="gui_phase_shift14" value="0" />
<generic name="gui_phase_shift_deg14" value="0.0" />
<generic name="gui_actual_phase_shift14" value="0" />
<generic name="gui_duty_cycle14" value="50" />
<generic name="gui_cascade_counter15" value="false" />
<generic name="gui_output_clock_frequency15" value="100.0" />
<generic name="gui_divide_factor_c15" value="1" />
<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
<generic name="gui_ps_units15" value="ps" />
<generic name="gui_phase_shift15" value="0" />
<generic name="gui_phase_shift_deg15" value="0.0" />
<generic name="gui_actual_phase_shift15" value="0" />
<generic name="gui_duty_cycle15" value="50" />
<generic name="gui_cascade_counter16" value="false" />
<generic name="gui_output_clock_frequency16" value="100.0" />
<generic name="gui_divide_factor_c16" value="1" />
<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
<generic name="gui_ps_units16" value="ps" />
<generic name="gui_phase_shift16" value="0" />
<generic name="gui_phase_shift_deg16" value="0.0" />
<generic name="gui_actual_phase_shift16" value="0" />
<generic name="gui_duty_cycle16" value="50" />
<generic name="gui_cascade_counter17" value="false" />
<generic name="gui_output_clock_frequency17" value="100.0" />
<generic name="gui_divide_factor_c17" value="1" />
<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
<generic name="gui_ps_units17" value="ps" />
<generic name="gui_phase_shift17" value="0" />
<generic name="gui_phase_shift_deg17" value="0.0" />
<generic name="gui_actual_phase_shift17" value="0" />
<generic name="gui_duty_cycle17" value="50" />
<generic name="gui_pll_auto_reset" value="Off" />
<generic name="gui_pll_bandwidth_preset" value="Auto" />
<generic name="gui_en_reconf" value="false" />
<generic name="gui_en_dps_ports" value="false" />
<generic name="gui_en_phout_ports" value="false" />
<generic name="gui_phout_division" value="1" />
<generic name="gui_en_lvds_ports" value="false" />
<generic name="gui_mif_generate" value="false" />
<generic name="gui_enable_mif_dps" value="false" />
<generic name="gui_dps_cntr" value="C0" />
<generic name="gui_dps_num" value="1" />
<generic name="gui_dps_dir" value="Positive" />
<generic name="gui_refclk_switch" value="false" />
<generic name="gui_refclk1_frequency" value="100.0" />
<generic name="gui_switchover_mode" value="Automatic Switchover" />
<generic name="gui_switchover_delay" value="0" />
<generic name="gui_active_clk" value="false" />
<generic name="gui_clk_bad" value="false" />
<generic name="gui_enable_cascade_out" value="false" />
<generic name="gui_cascade_outclk_index" value="0" />
<generic name="gui_enable_cascade_in" value="false" />
<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
<generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
</instance>
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
浏览文件 @ 03db2b6f
Assembler report for de1_riscv
Thu Aug 26 18:06:43 2021
Fri Aug 27 08:15:06 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
......@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Aug 26 18:06:43 2021 ;
; Assembler Status ; Successful - Fri Aug 27 08:15:06 2021 ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
......@@ -92,8 +92,8 @@ applicable agreement for further details.
; Option ; Setting ;
+----------------+--------------------------------------------------------------------+
; Device ; 5CSEMA5F31C6 ;
; JTAG usercode ; 0x00DD4A56 ;
; Checksum ; 0x00DD4A56 ;
; JTAG usercode ; 0x011D1C61 ;
; Checksum ; 0x011D1C61 ;
+----------------+--------------------------------------------------------------------+
......@@ -103,13 +103,13 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Thu Aug 26 18:06:30 2021
Info: Processing started: Fri Aug 27 08:14:57 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 627 megabytes
Info: Processing ended: Thu Aug 26 18:06:43 2021
Info: Elapsed time: 00:00:13
Info: Total CPU time (on all processors): 00:00:13
Info: Peak virtual memory: 4791 megabytes
Info: Processing ended: Fri Aug 27 08:15:06 2021
Info: Elapsed time: 00:00:09
Info: Total CPU time (on all processors): 00:00:09
examples/hdl4se_riscv/de1/de1_riscv.done
浏览文件 @ 03db2b6f
Thu Aug 26 18:07:04 2021
Fri Aug 27 08:15:20 2021
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
浏览文件 @ 03db2b6f
Fitter Status : Successful - Thu Aug 26 18:06:27 2021
Fitter Status : Successful - Fri Aug 27 08:14:55 2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Preliminary
Logic utilization (in ALMs) : 267 / 32,070 ( < 1 % )
Total registers : 215
Logic utilization (in ALMs) : 2,370 / 32,070 ( 7 % )
Total registers : 336
Total pins : 204 / 457 ( 45 % )
Total virtual pins : 0
Total block memory bits : 63,488 / 4,065,280 ( 2 % )
Total DSP Blocks : 4 / 87 ( 5 % )
Total block memory bits : 66,560 / 4,065,280 ( 2 % )
Total DSP Blocks : 10 / 87 ( 11 % )
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI TX Channels : 0
Total PLLs : 0 / 6 ( 0 % )
Total PLLs : 1 / 6 ( 17 % )
Total DLLs : 0 / 4 ( 0 % )
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
浏览文件 @ 03db2b6f
Flow report for de1_riscv
Thu Aug 26 18:07:03 2021
Fri Aug 27 08:15:19 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
......@@ -40,24 +40,24 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Aug 26 18:06:43 2021 ;
; Flow Status ; Successful - Fri Aug 27 08:15:06 2021 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ;
; Timing Models ; Preliminary ;
; Logic utilization (in ALMs) ; 267 / 32,070 ( < 1 % ) ;
; Total registers ; 215 ;
; Logic utilization (in ALMs) ; 2,370 / 32,070 ( 7 % ) ;
; Total registers ; 336 ;
; Total pins ; 204 / 457 ( 45 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 63,488 / 4,065,280 ( 2 % ) ;
; Total DSP Blocks ; 4 / 87 ( 5 % ) ;
; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ;
; Total DSP Blocks ; 10 / 87 ( 11 % ) ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI TX Channels ; 0 ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total PLLs ; 1 / 6 ( 17 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+---------------------------------------------+
......@@ -67,50 +67,66 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 08/26/2021 18:05:20 ;
; Start date & time ; 08/27/2021 08:13:50 ;
; Main task ; Compilation ;
; Revision Name ; de1_riscv ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 621136229624.162997232014788 ; -- ; -- ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_DIVIDE ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_DIVIDE ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_ADD_SUB ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_ADD_SUB ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; ram/ram8kb_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; regfile/regfile_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/mult_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/mult_s_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/div_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/div_s_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/adder_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/suber_bb.v ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+-------------------------------------+---------------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; COMPILER_SIGNATURE_ID ; 101574253398716.163002322913756 ; -- ; -- ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_DIVIDE ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_DIVIDE ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_ADD_SUB ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_ADD_SUB ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; altera_pll ; -- ; clk100M ; -- ;
; IP_TOOL_NAME ; altera_pll ; -- ; clk100M ; -- ;
; IP_TOOL_NAME ; altera_pll ; -- ; clk100M_0002 ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M_0002 ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; ram/ram8kb_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; regfile/regfile_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/mult_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/mult_s_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/div_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/div_s_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/adder_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/suber_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; alu/mulsu_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; clk/clk100M.cmp ; -- ; -- ; -- ;
; MISC_FILE ; clk/clk100M_sim/clk100M.vo ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; SPD_FILE ; clk/clk100M.spd ; -- ; -- ; -- ;
; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
......@@ -118,11 +134,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:04 ; 1.0 ; 585 MB ; 00:00:04 ;
; Fitter ; 00:01:01 ; 1.3 ; 2229 MB ; 00:01:14 ;
; Assembler ; 00:00:13 ; 1.0 ; 627 MB ; 00:00:13 ;
; TimeQuest Timing Analyzer ; 00:00:19 ; 1.1 ; 1041 MB ; 00:00:19 ;
; Total ; 00:01:37 ; -- ; -- ; 00:01:50 ;
; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4796 MB ; 00:00:09 ;
; Fitter ; 00:00:55 ; 2.6 ; 6584 MB ; 00:01:39 ;
; Assembler ; 00:00:09 ; 1.0 ; 4791 MB ; 00:00:09 ;
; TimeQuest Timing Analyzer ; 00:00:12 ; 3.1 ; 5174 MB ; 00:00:21 ;
; Total ; 00:01:25 ; -- ; -- ; 00:02:18 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
......@@ -131,10 +147,10 @@ applicable agreement for further details.
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; Fitter ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; Assembler ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; TimeQuest Timing Analyzer ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; Analysis & Synthesis ; DESKTOP-I91JIJO ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; DESKTOP-I91JIJO ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; DESKTOP-I91JIJO ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; DESKTOP-I91JIJO ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
......
examples/hdl4se_riscv/de1/de1_riscv.jdi
浏览文件 @ 03db2b6f
<sld_project_info>
<project>
<hash md5_digest_80b="789e8aa111dbf27acbbc"/>
<hash md5_digest_80b="2d43908cea7bab241e1f"/>
</project>
<file_info>
<file device="5CSEMA5F31C6" path="de1_riscv.sof" usercode="0xFFFFFFFF"/>
......
examples/hdl4se_riscv/de1/de1_riscv.map.summary
浏览文件 @ 03db2b6f
Analysis & Synthesis Status : Successful - Thu Aug 26 18:05:24 2021
Analysis & Synthesis Status : Successful - Fri Aug 27 08:13:59 2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 198
Total registers : 314
Total pins : 204
Total virtual pins : 0
Total block memory bits : 63,520
Total DSP Blocks : 4
Total block memory bits : 66,560
Total DSP Blocks : 10
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI TX Channels : 0
Total PLLs : 0
Total PLLs : 1
Total DLLs : 0
examples/hdl4se_riscv/de1/de1_riscv.qsf
浏览文件 @ 03db2b6f
......@@ -503,5 +503,7 @@ set_global_assignment -name QIP_FILE alu/div.qip
set_global_assignment -name QIP_FILE alu/div_s.qip
set_global_assignment -name QIP_FILE alu/adder.qip
set_global_assignment -name QIP_FILE alu/suber.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name QIP_FILE alu/mulsu.qip
\ No newline at end of file
set_global_assignment -name QIP_FILE alu/mulsu.qip
set_global_assignment -name QIP_FILE clk/clk100M.qip
set_global_assignment -name SIP_FILE clk/clk100M.sip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
examples/hdl4se_riscv/de1/de1_riscv.sdc
浏览文件 @ 03db2b6f
......@@ -11,6 +11,8 @@ create_clock -period 20.000ns [get_ports CLOCK3_50]
create_clock -period 20.000ns [get_ports CLOCK4_50]
create_clock -period 20.000ns [get_ports CLOCK_50]
create_clock -period 2.500ns -name clk_core
create_clock -period "27 MHz" -name tv_27m [get_ports TD_CLK27]
create_clock -period "100 MHz" -name clk_dram [get_ports DRAM_CLK]
# AUDIO : 48kHz 384fs 32-bit data
......
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
浏览文件 @ 03db2b6f
......@@ -2,52 +2,84 @@
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
Slack : 10.160
Type : Slow 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -96.771
TNS : -5620.036
Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.376
TNS : 0.000
Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.301
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -1.500
TNS : -413.435
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 1.250
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.886
Slack : 9.670
TNS : 0.000
Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
Slack : 9.895
Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -98.043
TNS : -5690.937
Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.374
TNS : 0.000
Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.284
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -1.500
TNS : -413.435
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 1.250
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.917
Slack : 9.673
TNS : 0.000
Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
Slack : 14.383
Type : Fast 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -57.032
TNS : -2855.496
Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.182
TNS : 0.000
Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.172
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -0.725
TNS : -272.467
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 1.250
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.484
Slack : 9.336
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
Slack : 14.648
Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -53.531
TNS : -2587.233
Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.173
TNS : 0.000
Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.157
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : -0.725
TNS : -272.467
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 1.250
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.438
Slack : 9.286
TNS : 0.000
------------------------------------------------------------
examples/hdl4se_riscv/de1/de1_riscv.v
浏览文件 @ 03db2b6f
......@@ -90,7 +90,14 @@ module de1_riscv(
inout [35:0] GPIO
);
wire wClk = CLOCK_50;
wire clk100MHz, clk75MHz, clklocked;
clk100M clk100(.refclk(CLOCK_50),
.rst(~KEY[3]),
.outclk_0(clk100MHz),
.outclk_1(clk75MHz),
.locked(clklocked));
wire wClk = clk100MHz;
wire nwReset = KEY[3];
wire wWrite, wRead;
......
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