de2_riscv_v4.v

//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

`define USECLOCK50
module de2_riscv_v4(

	//////////// CLOCK //////////
	CLOCK_50,
	CLOCK2_50,
	CLOCK3_50,

	//////////// Sma //////////
	SMA_CLKIN,
	SMA_CLKOUT,

	//////////// LED //////////
	LEDG,
	LEDR,

	//////////// KEY //////////
	KEY,

	//////////// EX_IO //////////
	EX_IO,

	//////////// SW //////////
	SW,

	//////////// SEG7 //////////
	HEX0,
	HEX1,
	HEX2,
	HEX3,
	HEX4,
	HEX5,
	HEX6,
	HEX7,

	//////////// LCD //////////
	LCD_BLON,
	LCD_DATA,
	LCD_EN,
	LCD_ON,
	LCD_RS,
	LCD_RW,

	//////////// RS232 //////////
	UART_CTS,
	UART_RTS,
	UART_RXD,
	UART_TXD,

	//////////// PS2 for Keyboard and Mouse //////////
	PS2_CLK,
	PS2_CLK2,
	PS2_DAT,
	PS2_DAT2,

	//////////// SDCARD //////////
	SD_CLK,
	SD_CMD,
	SD_DAT,
	SD_WP_N,

	//////////// VGA //////////
	VGA_B,
	VGA_BLANK_N,
	VGA_CLK,
	VGA_G,
	VGA_HS,
	VGA_R,
	VGA_SYNC_N,
	VGA_VS,

	//////////// Audio //////////
	AUD_ADCDAT,
	AUD_ADCLRCK,
	AUD_BCLK,
	AUD_DACDAT,
	AUD_DACLRCK,
	AUD_XCK,

	//////////// I2C for EEPROM //////////
	EEP_I2C_SCLK,
	EEP_I2C_SDAT,

	//////////// I2C for Audio Tv-Decoder  //////////
	I2C_SCLK,
	I2C_SDAT,

	//////////// Ethernet 0 //////////
	ENET0_GTX_CLK,
	ENET0_INT_N,
	ENET0_LINK100,
	ENET0_MDC,
	ENET0_MDIO,
	ENET0_RST_N,
	ENET0_RX_CLK,
	ENET0_RX_COL,
	ENET0_RX_CRS,
	ENET0_RX_DATA,
	ENET0_RX_DV,
	ENET0_RX_ER,
	ENET0_TX_CLK,
	ENET0_TX_DATA,
	ENET0_TX_EN,
	ENET0_TX_ER,
	ENETCLK_25,

	//////////// Ethernet 1 //////////
	ENET1_GTX_CLK,
	ENET1_INT_N,
	ENET1_LINK100,
	ENET1_MDC,
	ENET1_MDIO,
	ENET1_RST_N,
	ENET1_RX_CLK,
	ENET1_RX_COL,
	ENET1_RX_CRS,
	ENET1_RX_DATA,
	ENET1_RX_DV,
	ENET1_RX_ER,
	ENET1_TX_CLK,
	ENET1_TX_DATA,
	ENET1_TX_EN,
	ENET1_TX_ER,

	//////////// TV Decoder //////////
	TD_CLK27,
	TD_DATA,
	TD_HS,
	TD_RESET_N,
	TD_VS,

	//////////// USB 2.0 OTG (Cypress CY7C67200) //////////
	OTG_ADDR,
	OTG_CS_N,
	OTG_DATA,
	OTG_INT,
	OTG_RD_N,
	OTG_RST_N,
	OTG_WE_N,

	//////////// IR Receiver //////////
	IRDA_RXD,

	//////////// SDRAM //////////
	DRAM_ADDR,
	DRAM_BA,
	DRAM_CAS_N,
	DRAM_CKE,
	DRAM_CLK,
	DRAM_CS_N,
	DRAM_DQ,
	DRAM_DQM,
	DRAM_RAS_N,
	DRAM_WE_N,

	//////////// SRAM //////////
	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N,

	//////////// Flash //////////
	FL_ADDR,
	FL_CE_N,
	FL_DQ,
	FL_OE_N,
	FL_RST_N,
	FL_RY,
	FL_WE_N,
	FL_WP_N,

	//////////// GPIO, GPIO connect to GPIO Default //////////
	GPIO 
);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input 		          		CLOCK_50;
input 		          		CLOCK2_50;
input 		          		CLOCK3_50;

//////////// Sma //////////
input 		          		SMA_CLKIN;
output		          		SMA_CLKOUT;

//////////// LED //////////
output		     [8:0]		LEDG;
output		    [17:0]		LEDR;

//////////// KEY //////////
input 		     [3:0]		KEY;

//////////// EX_IO //////////
inout 		     [6:0]		EX_IO;

//////////// SW //////////
input 		    [17:0]		SW;

//////////// SEG7 //////////
output		     [6:0]		HEX0;
output		     [6:0]		HEX1;
output		     [6:0]		HEX2;
output		     [6:0]		HEX3;
output		     [6:0]		HEX4;
output		     [6:0]		HEX5;
output		     [6:0]		HEX6;
output		     [6:0]		HEX7;

//////////// LCD //////////
output		          		LCD_BLON;
inout 		     [7:0]		LCD_DATA;
output		          		LCD_EN;
output		          		LCD_ON;
output		          		LCD_RS;
output		          		LCD_RW;

//////////// RS232 //////////
input 		          		UART_CTS;
output		          		UART_RTS;
input 		          		UART_RXD;
output		          		UART_TXD;

//////////// PS2 for Keyboard and Mouse //////////
inout 		          		PS2_CLK;
inout 		          		PS2_CLK2;
inout 		          		PS2_DAT;
inout 		          		PS2_DAT2;

//////////// SDCARD //////////
output		          		SD_CLK;
inout 		          		SD_CMD;
inout 		     [3:0]		SD_DAT;
input 		          		SD_WP_N;

//////////// VGA //////////
output		     [7:0]		VGA_B;
output		          		VGA_BLANK_N;
output		          		VGA_CLK;
output		     [7:0]		VGA_G;
output		          		VGA_HS;
output		     [7:0]		VGA_R;
output		          		VGA_SYNC_N;
output		          		VGA_VS;

//////////// Audio //////////
input 		          		AUD_ADCDAT;
inout 		          		AUD_ADCLRCK;
inout 		          		AUD_BCLK;
output		          		AUD_DACDAT;
inout 		          		AUD_DACLRCK;
output		          		AUD_XCK;

//////////// I2C for EEPROM //////////
output		          		EEP_I2C_SCLK;
inout 		          		EEP_I2C_SDAT;

//////////// I2C for Audio Tv-Decoder  //////////
output		          		I2C_SCLK;
inout 		          		I2C_SDAT;

//////////// Ethernet 0 //////////
output		          		ENET0_GTX_CLK;
input 		          		ENET0_INT_N;
input 		          		ENET0_LINK100;
output		          		ENET0_MDC;
inout 		          		ENET0_MDIO;
output		          		ENET0_RST_N;
input 		          		ENET0_RX_CLK;
input 		          		ENET0_RX_COL;
input 		          		ENET0_RX_CRS;
input 		     [3:0]		ENET0_RX_DATA;
input 		          		ENET0_RX_DV;
input 		          		ENET0_RX_ER;
input 		          		ENET0_TX_CLK;
output		     [3:0]		ENET0_TX_DATA;
output		          		ENET0_TX_EN;
output		          		ENET0_TX_ER;
input 		          		ENETCLK_25;

//////////// Ethernet 1 //////////
output		          		ENET1_GTX_CLK;
input 		          		ENET1_INT_N;
input 		          		ENET1_LINK100;
output		          		ENET1_MDC;
inout 		          		ENET1_MDIO;
output		          		ENET1_RST_N;
input 		          		ENET1_RX_CLK;
input 		          		ENET1_RX_COL;
input 		          		ENET1_RX_CRS;
input 		     [3:0]		ENET1_RX_DATA;
input 		          		ENET1_RX_DV;
input 		          		ENET1_RX_ER;
input 		          		ENET1_TX_CLK;
output		     [3:0]		ENET1_TX_DATA;
output		          		ENET1_TX_EN;
output		          		ENET1_TX_ER;

//////////// TV Decoder //////////
input 		          		TD_CLK27;
input 		     [7:0]		TD_DATA;
input 		          		TD_HS;
output		          		TD_RESET_N;
input 		          		TD_VS;

//////////// USB 2.0 OTG (Cypress CY7C67200) //////////
output		     [1:0]		OTG_ADDR;
output		          		OTG_CS_N;
inout 		    [15:0]		OTG_DATA;
input 		          		OTG_INT;
output		          		OTG_RD_N;
output		          		OTG_RST_N;
output		          		OTG_WE_N;

//////////// IR Receiver //////////
input 		          		IRDA_RXD;

//////////// SDRAM //////////
output		    [12:0]		DRAM_ADDR;
output		     [1:0]		DRAM_BA;
output		          		DRAM_CAS_N;
output		          		DRAM_CKE;
output		          		DRAM_CLK;
output		          		DRAM_CS_N;
inout 		    [31:0]		DRAM_DQ;
output		     [3:0]		DRAM_DQM;
output		          		DRAM_RAS_N;
output		          		DRAM_WE_N;

//////////// SRAM //////////
output		    [19:0]		SRAM_ADDR;
output		          		SRAM_CE_N;
inout 		    [15:0]		SRAM_DQ;
output		          		SRAM_LB_N;
output		          		SRAM_OE_N;
output		          		SRAM_UB_N;
output		          		SRAM_WE_N;

//////////// Flash //////////
output		    [22:0]		FL_ADDR;
output		          		FL_CE_N;
inout 		     [7:0]		FL_DQ;
output		          		FL_OE_N;
output		          		FL_RST_N;
input 		          		FL_RY;
output		          		FL_WE_N;
output		          		FL_WP_N;

//////////// GPIO, GPIO connect to GPIO Default //////////
inout 		    [35:0]		GPIO;


  wire        uart_tx;
  wire        uart_rx;
  assign GPIO[5] = uart_tx;
  assign GPIO[7] = 1'bz;
  assign      uart_rx = GPIO[7];

  assign LEDR[0] = uart_tx;
  assign LEDR[1] = uart_rx;

`ifdef USECLOCK50
	wire wClk = CLOCK_50;
`else
	wire clk100MHz, clk75MHz, clklocked;
	clk100M clk100(.refclk(CLOCK_50),
	               .rst(~KEY[3]),
				   .outclk_0(clk100MHz), 
				   .outclk_1(clk75MHz),
				   .locked(clklocked));
				   
	wire wClk = clk100MHz;
`endif
	wire nwReset = KEY[3];

    wire wWrite, wRead;
    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart;
    wire [3:0]  bWriteMask;

	assign bReadDataKey = {18'b0, KEY, SW};

	reg readcmd;
	reg [31:0] readaddr;

	always @(posedge wClk) begin
		if (!nwReset) begin
			readcmd <= 1'b0;
			readaddr <= 32'b0;
		end else begin
			readcmd <= wRead;
			readaddr <= bReadAddr;
		end
	end
    
    assign bReadData = 
            ((readaddr & 32'hffffff00) == 32'hF0000000) ? bReadDataKey : (
            ((readaddr & 32'hff000000) == 32'h00000000) ? bReadDataRam : (
            ((readaddr & 32'hffffff00) == 32'hF0000100) ? bReadDataUart : (32'hffffffff)
			)
            );

    wire [29:0] ramaddr;
    assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];

    wire [4:0]  regno;
    wire [3:0]  regena;
    wire [31:0] regwrdata;
    wire        regwren;
    wire [31:0] regrddata;
    wire [4:0]  regno2;
    wire [3:0]  regena2;
    wire [31:0] regwrdata2;
    wire        regwren2;
    wire [31:0] regrddata2;

	uart_ctrl uart_ctrl(
		.wClk(wClk), 
		.nwReset(nwReset),
		.wRead(((bReadAddr & 32'hffffff00) == 32'hf0000100)?wRead:1'b0), 
		.bReadAddr(bReadAddr),
		.wWrite(((bWriteAddr & 32'hffffff00) == 32'hf0000100)?wWrite:1'b0), 
		.bWriteAddr(bWriteAddr),
		.bWriteData(bWriteData),
		.bReadData(bReadDataUart),
		.uart_tx(uart_tx), 
		.uart_rx(uart_rx),
		.dataready(LEDR[2]),
		.sendready(LEDR[3]),
		.sendfull(LEDR[4]),
		.recvempty(LEDR[5])
	);

	reg [4:0] lastregno;
	reg [4:0] lastregno2;

	always @(posedge wClk) begin
		lastregno <= regno;
		lastregno2 <= regno2;
	end

    regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
    regfile    regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
    ram16kB    ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
	riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
                regno, regena, regwrdata, regwren, (lastregno == 0) ? 0 : regrddata,
				regno2, regena2, regwrdata2, regwren2, (lastregno2 == 0) ? 0 : regrddata2
				);



//=======================================================
//  Structural coding
//=======================================================


    reg [6:0] led0;
	reg [6:0] led1;
	reg [6:0] led2;
	reg [6:0] led3;
	reg [6:0] led4;
	reg [6:0] led5;
	reg [6:0] led6;
	reg [6:0] led7;
	assign HEX0 = ~led0;
	assign HEX1 = ~led1;
	assign HEX2 = ~led2;
	assign HEX3 = ~led3;
	assign HEX4 = ~led4;
	assign HEX5 = ~led5;
	assign HEX6 = ~led6;
	assign HEX7 = ~led7;

	

	always @(posedge wClk) begin
		if (!nwReset) begin
			led0 <= 8'h3f;
			led1 <= 8'h3f;
			led2 <= 8'h3f;
			led3 <= 8'h3f;
			led4 <= 8'h3f;
			led5 <= 8'h3f;
		end else begin
			if (SW[17]) begin
				led0 <= 8'h06;
				led1 <= 8'h06;
				led2 <= 8'h06;
				led3 <= 8'h07;
				led4 <= 8'h07;
				led5 <= 8'h07;				
			end
			else if (SW[16]) begin
				led0 <= 8'h3f;
				led1 <= 8'h06;
				led2 <= 8'h5b;
				led3 <= 8'h4f;
				led4 <= 8'h66;
				led5 <= 8'h6d;				
			end
			else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin
				if (bWriteAddr[3:2] == 2'h0) begin
					if (bWriteMask[0] == 0)
						led0 <= bWriteData[6:0];
					if (bWriteMask[1] == 0)
						led1 <= bWriteData[14:8];
					if (bWriteMask[2] == 0)
						led2 <= bWriteData[22:16];
					if (bWriteMask[3] == 0)
						led3 <= bWriteData[30:24];
				end else if (bWriteAddr[3:2] == 2'h1) begin
					if (bWriteMask[0] == 0)
						led4 <= bWriteData[6:0];
					if (bWriteMask[1] == 0)
						led5 <= bWriteData[14:8];
					if (bWriteMask[2] == 0)
						led6 <= bWriteData[22:16];
					if (bWriteMask[3] == 0)
						led7 <= bWriteData[30:24];
				end
			end
		end
	end

endmodule