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202109021858 V4 start

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examples/hdl4se_riscv/de2/de2_riscv_v4.qsf
浏览文件 @ 5b9662b9
......@@ -993,6 +993,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE ../verilog/altera/regfile/regfile.v
set_global_assignment -name VERILOG_FILE qsys/pllqsys/synthesis/submodules/pllqsys_altpll_0.v
set_global_assignment -name VERILOG_FILE qsys/pllqsys/synthesis/pllqsys.v
set_global_assignment -name VERILOG_FILE ../verilog/riscv_core_v4.v
......
examples/hdl4se_riscv/de2/de2_riscv_v4.v
浏览文件 @ 5b9662b9
......@@ -2,8 +2,8 @@
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define USECLOCK50_1
`define USECLOCK50
module de2_riscv_v4(
//////////// CLOCK //////////
......@@ -365,7 +365,6 @@ output FL_WP_N;
inout [35:0] GPIO;
wire uart_tx;
wire uart_rx;
assign GPIO[5] = uart_tx;
......@@ -374,18 +373,20 @@ inout [35:0] GPIO;
assign LEDR[0] = uart_tx;
assign LEDR[1] = uart_rx;
wire nwReset = KEY[3];
`ifdef USECLOCK50
wire wClk = CLOCK_50;
`else
wire clk100MHz, clk75MHz, clklocked;
pllqsys clk100(.clk_clk(CLOCK_50),
.reset_reset_n(~KEY[3]),
.altpll_0_c0_clk(clk100MHz));
clk100M clk100(.refclk(CLOCK_50),
.rst(~KEY[3]),
.outclk_0(clk100MHz),
.outclk_1(clk75MHz),
.locked(clklocked));
wire wClk = clk100MHz;
`endif
wire nwReset = KEY[3];
wire wWrite, wRead;
wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart;
......@@ -443,8 +444,21 @@ inout [35:0] GPIO;
.sendfull(LEDR[4]),
.recvempty(LEDR[5])
);
reg [4:0] lastregno;
reg [4:0] lastregno2;
always @(posedge wClk) begin
lastregno <= regno;
lastregno2 <= regno2;
end
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
ram16kB ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
regno, regena, regwrdata, regwren, (lastregno == 0) ? 0 : regrddata,
regno2, regena2, regwrdata2, regwren2, (lastregno2 == 0) ? 0 : regrddata2
);
......
examples/hdl4se_riscv/hdl4se_riscv_sim/CMakeLists.txt
浏览文件 @ 5b9662b9
......@@ -8,6 +8,7 @@ add_executable(riscv_sim_v4
"main_v4.c"
"hdl4se_riscv_core_v4.c"
"hdl4se_riscv_ram8k.c"
"hdl4se_riscv_regfile.c"
)
add_executable(riscv_sim_v3
......
examples/hdl4se_riscv/hdl4se_riscv_sim/main_v4.c
浏览文件 @ 5b9662b9
......@@ -60,6 +60,7 @@ IHDL4SEModuleVar* hdl4seCreate_main(IHDL4SEModuleVar* parent, const char* instan
extern int (*A_u_t_o_registor_digitled)();
extern int (*A_u_t_o_registor_riscv_core)();
extern int (*A_u_t_o_registor_riscv_ram)();
extern int (*A_u_t_o_registor_riscv_regfile)();
FILE* recordfile;
THREADLOCK recordfilelock;
......@@ -85,6 +86,7 @@ int main(int argc, char* argv[])
A_u_t_o_registor_digitled();
A_u_t_o_registor_riscv_core();
A_u_t_o_registor_riscv_ram();
A_u_t_o_registor_riscv_regfile();
recordfile = fopen("d:/gitwork/recordfile.txt", "w");
recordfilelock = threadlockCreate();
sim = hdl4sesimCreateSimulator();
......@@ -92,7 +94,7 @@ int main(int argc, char* argv[])
objectCall1(sim, SetTopModule, topmodule);
objectCall1(sim, SetReset, 0);
#if RECORDVCD
vcdfile = hdl4sesimCreateVCDFile("riscv_v4.vcd");
vcdfile = hdl4sesimCreateVCDFile("riscv_v2.vcd");
objectCall2(vcdfile, AddSignal, "/top/core", "pc");
objectCall2(vcdfile, AddSignal, "/top/core", "instr");
objectCall2(vcdfile, AddSignal, "/top/core", "state");
......@@ -102,37 +104,42 @@ int main(int argc, char* argv[])
objectCall2(vcdfile, AddSignal, "/top/core", "wWrite");
objectCall2(vcdfile, AddSignal, "/top/core", "bWriteAddr");
objectCall2(vcdfile, AddSignal, "/top/core", "bWriteData");
objectCall2(vcdfile, AddSignal, "/top/core", "x1");
objectCall2(vcdfile, AddSignal, "/top/core", "x2");
objectCall2(vcdfile, AddSignal, "/top/core", "x3");
objectCall2(vcdfile, AddSignal, "/top/core", "x4");
objectCall2(vcdfile, AddSignal, "/top/core", "x5");
objectCall2(vcdfile, AddSignal, "/top/core", "x6");
objectCall2(vcdfile, AddSignal, "/top/core", "x7");
objectCall2(vcdfile, AddSignal, "/top/core", "x8");
objectCall2(vcdfile, AddSignal, "/top/core", "x9");
objectCall2(vcdfile, AddSignal, "/top/core", "x10");
objectCall2(vcdfile, AddSignal, "/top/core", "x11");
objectCall2(vcdfile, AddSignal, "/top/core", "x12");
objectCall2(vcdfile, AddSignal, "/top/core", "x13");
objectCall2(vcdfile, AddSignal, "/top/core", "x14");
objectCall2(vcdfile, AddSignal, "/top/core", "x15");
objectCall2(vcdfile, AddSignal, "/top/core", "x16");
objectCall2(vcdfile, AddSignal, "/top/core", "x17");
objectCall2(vcdfile, AddSignal, "/top/core", "x18");
objectCall2(vcdfile, AddSignal, "/top/core", "x19");
objectCall2(vcdfile, AddSignal, "/top/core", "x20");
objectCall2(vcdfile, AddSignal, "/top/core", "x21");
objectCall2(vcdfile, AddSignal, "/top/core", "x22");
objectCall2(vcdfile, AddSignal, "/top/core", "x23");
objectCall2(vcdfile, AddSignal, "/top/core", "x24");
objectCall2(vcdfile, AddSignal, "/top/core", "x25");
objectCall2(vcdfile, AddSignal, "/top/core", "x26");
objectCall2(vcdfile, AddSignal, "/top/core", "x27");
objectCall2(vcdfile, AddSignal, "/top/core", "x28");
objectCall2(vcdfile, AddSignal, "/top/core", "x29");
objectCall2(vcdfile, AddSignal, "/top/core", "x30");
objectCall2(vcdfile, AddSignal, "/top/core", "x31");
objectCall2(vcdfile, AddSignal, "/top/core", "regno");
objectCall2(vcdfile, AddSignal, "/top/core", "regena");
objectCall2(vcdfile, AddSignal, "/top/core", "regwrdata");
objectCall2(vcdfile, AddSignal, "/top/core", "regwren");
objectCall2(vcdfile, AddSignal, "/top/core", "regrddata");
objectCall2(vcdfile, AddSignal, "/top/regs", "x1");
objectCall2(vcdfile, AddSignal, "/top/regs", "x2");
objectCall2(vcdfile, AddSignal, "/top/regs", "x3");
objectCall2(vcdfile, AddSignal, "/top/regs", "x4");
objectCall2(vcdfile, AddSignal, "/top/regs", "x5");
objectCall2(vcdfile, AddSignal, "/top/regs", "x6");
objectCall2(vcdfile, AddSignal, "/top/regs", "x7");
objectCall2(vcdfile, AddSignal, "/top/regs", "x8");
objectCall2(vcdfile, AddSignal, "/top/regs", "x9");
objectCall2(vcdfile, AddSignal, "/top/regs", "x10");
objectCall2(vcdfile, AddSignal, "/top/regs", "x11");
objectCall2(vcdfile, AddSignal, "/top/regs", "x12");
objectCall2(vcdfile, AddSignal, "/top/regs", "x13");
objectCall2(vcdfile, AddSignal, "/top/regs", "x14");
objectCall2(vcdfile, AddSignal, "/top/regs", "x15");
objectCall2(vcdfile, AddSignal, "/top/regs", "x16");
objectCall2(vcdfile, AddSignal, "/top/regs", "x17");
objectCall2(vcdfile, AddSignal, "/top/regs", "x18");
objectCall2(vcdfile, AddSignal, "/top/regs", "x19");
objectCall2(vcdfile, AddSignal, "/top/regs", "x20");
objectCall2(vcdfile, AddSignal, "/top/regs", "x21");
objectCall2(vcdfile, AddSignal, "/top/regs", "x22");
objectCall2(vcdfile, AddSignal, "/top/regs", "x23");
objectCall2(vcdfile, AddSignal, "/top/regs", "x24");
objectCall2(vcdfile, AddSignal, "/top/regs", "x25");
objectCall2(vcdfile, AddSignal, "/top/regs", "x26");
objectCall2(vcdfile, AddSignal, "/top/regs", "x27");
objectCall2(vcdfile, AddSignal, "/top/regs", "x28");
objectCall2(vcdfile, AddSignal, "/top/regs", "x29");
objectCall2(vcdfile, AddSignal, "/top/regs", "x30");
objectCall2(vcdfile, AddSignal, "/top/regs", "x31");
objectCall1(vcdfile, SetTopModule, topmodule);
objectCall0(vcdfile, StartRecord);
#endif
......
examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main_v4.c
浏览文件 @ 5b9662b9
......@@ -31,7 +31,7 @@
/*
* Created by HDL4SE @ Thu Sep 2 08:47:15 2021
* Created by HDL4SE @ Thu Sep 2 18:50:33 2021
* Don't edit it.
*/
......@@ -56,6 +56,8 @@ IDLIST
VID(nwReset),
VID(wRead_out),
VID(bReadAddr_out),
VID(regrddata),
VID(regrddata2),
VID(ram_dot_byteena), /* port:ram(ram8kb).byteena, 1 */
VID(ram_dot_wren), /* port:ram(ram8kb).wren, 4 */
VID(bReadDataRam),
......@@ -66,6 +68,14 @@ IDLIST
VID(bWriteMask),
VID(wRead),
VID(bReadAddr),
VID(regno),
VID(regena),
VID(regwrdata),
VID(regwren),
VID(regno2),
VID(regena2),
VID(regwrdata2),
VID(regwren2),
VID(bReadData),
VID(ramaddr),
END_IDLIST
......@@ -96,6 +106,8 @@ GEN_MODULE_INIT
WIRE(ramaddr, 30);
WIRE(wRead_out, 1);
WIRE(bReadAddr_out, 32);
WIRE(regrddata, 32);
WIRE(regrddata2, 32);
WIRE(ram_dot_byteena, 1);
WIRE(ram_dot_wren, 1);
WIRE(bReadDataRam, 32);
......@@ -106,6 +118,14 @@ GEN_MODULE_INIT
WIRE(bWriteMask, 4);
WIRE(wRead, 1);
WIRE(bReadAddr, 32);
WIRE(regno, 5);
WIRE(regena, 4);
WIRE(regwrdata, 32);
WIRE(regwren, 1);
WIRE(regno2, 5);
WIRE(regena2, 4);
WIRE(regwrdata2, 32);
WIRE(regwren2, 1);
CELL_INST("76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", /* hdl4se_reg */
"readcmd",
"32'h1",
......@@ -114,6 +134,14 @@ GEN_MODULE_INIT
"readaddr",
"32'h20",
"wClk, bReadAddr, bReadAddr_out");
CELL_INST("2E577C6B-2FF1-425E-90B3-947EB523B863", /* regfile */
"regs",
"",
"regno, regena, wClk, regwrdata, regwren, regrddata");
CELL_INST("2E577C6B-2FF1-425E-90B3-947EB523B863", /* regfile */
"regs2",
"",
"regno2, regena2, wClk, regwrdata2, regwren2, regrddata2");
CELL_INST("EE3409B2-6D04-42B3-A44D-7F2444DDC00D", /* ram8kb */
"ram",
"",
......@@ -125,7 +153,9 @@ GEN_MODULE_INIT
CELL_INST("638E8BC3-B0E0-41DC-9EDD-D35A39FD8051", /* riscv_core */
"core",
"",
"wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData");
"wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData"
", regno, regena, regwrdata, regwren, regrddata, regno2, regena2, regwrdata2, regwren2"
", regrddata2");
GEN_FUNC("ram_dot_byteena", top_gen_ram_dot_byteena);
GEN_FUNC("ram_dot_wren", top_gen_ram_dot_wren);
GEN_FUNC("bReadData", top_gen_bReadData);
......
examples/hdl4se_riscv/test_code/console.c
浏览文件 @ 5b9662b9
#define UARTADDRESS (unsigned int *)0xf0000100
#define REFFREQ 25000000
#define REFFREQ 50000000
volatile unsigned int* _uartaddr = UARTADDRESS;
volatile unsigned int _uartstate;
......
examples/hdl4se_riscv/test_code/test.cod
浏览文件 @ 5b9662b9
......@@ -169,7 +169,7 @@ E3 90 07 FC 93 07 00 00 13 85 07 00 03 24 C1 01
83 27 84 FD 83 C7 07 00 E3 90 07 FA 93 07 00 00
13 85 07 00 03 24 C1 02 13 01 01 03 67 80 00 00
13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE
B7 87 7D 01 13 87 07 84 83 27 C4 FE 33 47 F7 02
B7 F7 FA 02 13 87 07 08 83 27 C4 FE 33 47 F7 02
83 A7 01 C3 93 87 07 01 23 A0 E7 00 93 07 00 00
13 85 07 00 03 24 C1 01 13 01 01 02 67 80 00 00
13 01 01 EC 23 2E 11 12 23 2C 81 12 13 04 01 14
......
examples/hdl4se_riscv/test_code/test.hex
浏览文件 @ 5b9662b9
......@@ -168,7 +168,7 @@
:100AE400832784FD83C70700E39007FA9307000078
:100AF400138507000324C10213010103678000006A
:100B0400130101FE232E8100130401022326A4FEF7
:100B1400B7877D01138707848327C4FE3347F70211
:100B1400B7F7FA02138707088327C4FE3347F7029F
:100B240083A701C39387070123A0E700930700006D
:100B3400138507000324C10113010102678000002B
:100B4400130101EC232E1112232C8112130401141E
......
examples/hdl4se_riscv/test_code/test.info
浏览文件 @ 5b9662b9
......@@ -10,7 +10,7 @@ ELF Header:
Version: 0x1
Entry point address: 0x8c
Start of program headers: 52 (bytes into file)
Start of section headers: 8432 (bytes into file)
Start of section headers: 8428 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
......@@ -32,10 +32,10 @@ Section Headers:
[ 8] .sbss NOBITS 00002828 001828 000008 00 WA 0 0 4
[ 9] .bss NOBITS 00002830 001828 00001c 00 WA 0 0 4
[10] .comment PROGBITS 00000000 001828 000012 01 MS 0 0 1
[11] .riscv.attributes RISCV_ATTRIBUTE 00000000 00183a 000026 00 0 0 1
[12] .symtab SYMTAB 00000000 001860 000520 10 13 41 4
[13] .strtab STRTAB 00000000 001d80 0002f2 00 0 0 1
[14] .shstrtab STRTAB 00000000 002072 00007e 00 0 0 1
[11] .riscv.attributes RISCV_ATTRIBUTE 00000000 00183a 000021 00 0 0 1
[12] .symtab SYMTAB 00000000 00185c 000520 10 13 41 4
[13] .strtab STRTAB 00000000 001d7c 0002f2 00 0 0 1
[14] .shstrtab STRTAB 00000000 00206e 00007e 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
......@@ -149,4 +149,4 @@ No version information found in this file.
Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0"
Tag_RISCV_arch: "rv32i2p0_m2p0"
examples/hdl4se_riscv/test_code/test.mif
浏览文件 @ 5b9662b9
......@@ -713,8 +713,8 @@ BEGIN
02C2 : 00812E23;
02C3 : 02010413;
02C4 : FEA42623;
02C5 : 017D87B7;
02C6 : 84078713;
02C5 : 02FAF7B7;
02C6 : 08078713;
02C7 : FEC42783;
02C8 : 02F74733;
02C9 : C301A783;
......
examples/hdl4se_riscv/test_code/test.txt
浏览文件 @ 5b9662b9
......@@ -723,8 +723,8 @@ Disassembly of section .text:
b08: 00812e23 sw x8,28(x2)
b0c: 02010413 addi x8,x2,32
b10: fea42623 sw x10,-20(x8)
b14: 017d87b7 lui x15,0x17d8
b18: 84078713 addi x14,x15,-1984 # 17d7840 <__global_pointer$+0x17d4c50>
b14: 02faf7b7 lui x15,0x2faf
b18: 08078713 addi x14,x15,128 # 2faf080 <__global_pointer$+0x2fac490>
b1c: fec42783 lw x15,-20(x8)
b20: 02f74733 div x14,x14,x15
b24: c301a783 lw x15,-976(x3) # 2820 <_uartaddr>
......@@ -1444,12 +1444,13 @@ Disassembly of section .comment:
Disassembly of section .riscv.attributes:
00000000 <.riscv.attributes>:
0: 2541 c.jal 680 <_s2d+0x4>
0: 2041 c.jal 80 <register_fini+0xc>
2: 0000 c.unimp
4: 7200 c.flw f8,32(x12)
6: 7369 c.lui x6,0xffffa
8: 01007663 bgeu x0,x16,14 <register_fini-0x60>
c: 0000001b 0x1b
c: 0016 c.slli x0,0x5
e: 0000 c.unimp
10: 1004 c.addi4spn x9,x2,32
12: 7205 c.lui x4,0xfffe1
14: 3376 c.fldsp f6,376(x2)
......@@ -1458,4 +1459,4 @@ Disassembly of section .riscv.attributes:
1a: 5f30 c.lw x12,120(x14)
1c: 326d c.jal fffff9c6 <__global_pointer$+0xffffcdd6>
1e: 3070 c.fld f12,224(x8)
20: 615f 7032 0030 0x307032615f
...
examples/hdl4se_riscv/verilog/riscv_core_v4_1.v 0 → 100644
浏览文件 @ 5b9662b9
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/* riscv_core_v4.v */
`define RISCVSTATE_STARTUP 0
`define RISCVSTATE_EXEC_INST 1
`define RISCVSTATE_WAIT_LD 2
`define RISCVSTATE_WAIT_ST 3
`define RISCVSTATE_WAIT_DIV 4
`define RAMSIZE 4096
(*
HDL4SE="LCOM",
CLSID="638E8BC3-B0E0-41DC-9EDD-D35A39FD8051",
softmodule="hdl4se"
*)
module riscv_core(
input wClk, nwReset,
output wWrite,
output [31:0] bWriteAddr,
output [31:0] bWriteData,
output [3:0] bWriteMask,
output reg wRead,
output reg [31:0] bReadAddr,
input [31:0] bReadData
);
reg [31:0] pc;
reg [31:0] x1;
reg [31:0] x2;
reg [31:0] x3;
reg [31:0] x4;
reg [31:0] x5;
reg [31:0] x6;
reg [31:0] x7;
reg [31:0] x8;
reg [31:0] x9;
reg [31:0] x10;
reg [31:0] x11;
reg [31:0] x12;
reg [31:0] x13;
reg [31:0] x14;
reg [31:0] x15;
reg [31:0] x16;
reg [31:0] x17;
reg [31:0] x18;
reg [31:0] x19;
reg [31:0] x20;
reg [31:0] x21;
reg [31:0] x22;
reg [31:0] x23;
reg [31:0] x24;
reg [31:0] x25;
reg [31:0] x26;
reg [31:0] x27;
reg [31:0] x28;
reg [31:0] x29;
reg [31:0] x30;
reg [31:0] x31;
reg [3:0] state;
reg [31:0] imm;
reg [4:0] dstreg;
reg [31:0] dstvalue;
reg [4:0] divclk;
reg write;
reg [31:0] writeaddr;
reg [31:0] writedata;
reg [3:0] writemask;
assign wWrite = write;
assign bWriteAddr = writeaddr;
assign bWriteData = writedata;
assign bWriteMask = writemask;
reg [31:0] cur_instr;
always @(posedge wClk)
if (state == `RISCVSTATE_EXEC_INST)
cur_instr <= bReadData;
wire [31:0] instr = bReadData;
wire [4:0] rs1_no = instr[19:15];
wire [4:0] rs2_no = instr[24:20];
wire [4:0] opcode = instr[6:2];
wire [4:0] rd = instr[11:7];
wire [2:0] func3 = instr[14:12];
wire [4:0] rd_r = cur_instr[11:7];
wire [2:0] func3_r = cur_instr[14:12];
reg cond;
reg [31:0] rs1;
reg [31:0] rs2;
wire signed [31:0] rs1_s = rs1;
wire signed [31:0] rs2_s = rs2;
wire signed [31:0] imm_s = imm;
wire [31:0] add_result;
wire [31:0] sub_result;
wire [63:0] mul_result;
wire [63:0] muls_result;
wire [71:0] mulsu_result;
wire [31:0] div_result_r, mod_result_r, divs_result_r, mods_result_r;
wire [31:0] div_result, mod_result, divs_result, mods_result;
adder add(rs1, rs2, add_result);
suber sub(rs1, rs2, sub_result);
mult mul(rs1, rs2, mul_result);
mult_s mul_s(rs1, rs2, muls_result);
mulsu mul_su(rs1, {8'b0, rs2}, mulsu_result);
div div(wClk, rs2, rs1, div_result_r, mod_result_r);
div_s divs(wClk, rs2, rs1, divs_result_r, mods_result_r);
assign div_result = div_result_r;
assign divs_result = divs_result_r;
assign mod_result = mod_result_r;
assign mods_result = mods_result_r;
always @(rs1_no or x31 or
x1 or x2 or x3 or x4 or x5 or x6 or x7 or x8 or x9 or x10 or
x11 or x12 or x13 or x14 or x15 or x16 or x17 or x18 or x19 or x20 or
x21 or x22 or x23 or x24 or x25 or x26 or x27 or x28 or x29 or x30
)
case (rs1_no)
5'd0: rs1 = 0;
5'd1: rs1 = x1;
5'd2: rs1 = x2;
5'd3: rs1 = x3;
5'd4: rs1 = x4;
5'd5: rs1 = x5;
5'd6: rs1 = x6;
5'd7: rs1 = x7;
5'd8: rs1 = x8;
5'd9: rs1 = x9;
5'd10: rs1 = x10;
5'd11: rs1 = x11;
5'd12: rs1 = x12;
5'd13: rs1 = x13;
5'd14: rs1 = x14;
5'd15: rs1 = x15;
5'd16: rs1 = x16;
5'd17: rs1 = x17;
5'd18: rs1 = x18;
5'd19: rs1 = x19;
5'd20: rs1 = x20;
5'd21: rs1 = x21;
5'd22: rs1 = x22;
5'd23: rs1 = x23;
5'd24: rs1 = x24;
5'd25: rs1 = x25;
5'd26: rs1 = x26;
5'd27: rs1 = x27;
5'd28: rs1 = x28;
5'd29: rs1 = x29;
5'd30: rs1 = x30;
5'd31: rs1 = x31;
endcase
always @(rs2_no or x31 or
x1 or x2 or x3 or x4 or x5 or x6 or x7 or x8 or x9 or x10 or
x11 or x12 or x13 or x14 or x15 or x16 or x17 or x18 or x19 or x20 or
x21 or x22 or x23 or x24 or x25 or x26 or x27 or x28 or x29 or x30
)
case (rs2_no)
5'd0: rs2 = 0;
5'd1: rs2 = x1;
5'd2: rs2 = x2;
5'd3: rs2 = x3;
5'd4: rs2 = x4;
5'd5: rs2 = x5;
5'd6: rs2 = x6;
5'd7: rs2 = x7;
5'd8: rs2 = x8;
5'd9: rs2 = x9;
5'd10: rs2 = x10;
5'd11: rs2 = x11;
5'd12: rs2 = x12;
5'd13: rs2 = x13;
5'd14: rs2 = x14;
5'd15: rs2 = x15;
5'd16: rs2 = x16;
5'd17: rs2 = x17;
5'd18: rs2 = x18;
5'd19: rs2 = x19;
5'd20: rs2 = x20;
5'd21: rs2 = x21;
5'd22: rs2 = x22;
5'd23: rs2 = x23;
5'd24: rs2 = x24;
5'd25: rs2 = x25;
5'd26: rs2 = x26;
5'd27: rs2 = x27;
5'd28: rs2 = x28;
5'd29: rs2 = x29;
5'd30: rs2 = x30;
5'd31: rs2 = x31;
endcase
always@(posedge wClk)
if (~nwReset) begin
x1 <= 32'h0000008c;
x2 <= `RAMSIZE * 4 - 16;
end
else
case (dstreg)
5'd0: ;//0 <= dstvalue;
5'd1: x1 <= dstvalue;
5'd2: x2 <= dstvalue;
5'd3: x3 <= dstvalue;
5'd4: x4 <= dstvalue;
5'd5: x5 <= dstvalue;
5'd6: x6 <= dstvalue;
5'd7: x7 <= dstvalue;
5'd8: x8 <= dstvalue;
5'd9: x9 <= dstvalue;
5'd10: x10 <= dstvalue;
5'd11: x11 <= dstvalue;
5'd12: x12 <= dstvalue;
5'd13: x13 <= dstvalue;
5'd14: x14 <= dstvalue;
5'd15: x15 <= dstvalue;
5'd16: x16 <= dstvalue;
5'd17: x17 <= dstvalue;
5'd18: x18 <= dstvalue;
5'd19: x19 <= dstvalue;
5'd20: x20 <= dstvalue;
5'd21: x21 <= dstvalue;
5'd22: x22 <= dstvalue;
5'd23: x23 <= dstvalue;
5'd24: x24 <= dstvalue;
5'd25: x25 <= dstvalue;
5'd26: x26 <= dstvalue;
5'd27: x27 <= dstvalue;
5'd28: x28 <= dstvalue;
5'd29: x29 <= dstvalue;
5'd30: x30 <= dstvalue;
5'd31: x31 <= dstvalue;
endcase
/* cond */
always @(rs1 or rs2 or rs1_s or rs2_s or func3)
case(func3)
0:/*beq*/ cond = rs1 == rs2;
1:/*bne*/ cond = rs1 != rs2;
4:/*blt*/ cond = rs1_s < rs2_s;
5:/*bge*/ cond = rs1_s >= rs2_s;
6:/*bltu*/cond = rs1 < rs2;
7:/*bgeu*/cond = rs1 >= rs2;
default: cond = 1'b0;
endcase
always @(instr)
case (instr[6:2])
5'h0d: imm = {instr[31:12], 12'b0};
5'h05: imm = {instr[31:12], 12'b0};
5'h1b: imm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
5'h19: imm = {{20{instr[31]}}, instr[31:20]};
5'h18: imm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
5'h00: imm = {{20{instr[31]}}, instr[31:20]};
5'h08: imm = {{20{instr[31]}}, instr[31:25], instr[11:7]};
5'h04: imm = {{20{instr[31]}}, instr[31:20]};
default: imm = 0;
endcase
/* state */
always @(posedge wClk)
if (!nwReset) begin
state <= `RISCVSTATE_STARTUP;
end else begin
case (state)
`RISCVSTATE_STARTUP: state <= `RISCVSTATE_EXEC_INST;
`RISCVSTATE_EXEC_INST: begin
if (opcode == 5'h00)
state <= `RISCVSTATE_WAIT_LD;
else if (opcode == 5'h08)
state <= `RISCVSTATE_WAIT_ST;
else if (opcode == 5'h0c && instr[25] && func3[2] && (rs2 != 0)) begin
state <= `RISCVSTATE_WAIT_DIV;
divclk <= 11;
end
end
`RISCVSTATE_WAIT_LD: state <= `RISCVSTATE_EXEC_INST;
`RISCVSTATE_WAIT_ST: state <= `RISCVSTATE_EXEC_INST;
`RISCVSTATE_WAIT_DIV: begin
if (divclk == 0)
state <= `RISCVSTATE_EXEC_INST;
else
divclk <= divclk - 1;
end
endcase
end
reg [31:0] newpc;
always @(state or pc or rs1 or imm or cond or opcode)
if (state == `RISCVSTATE_EXEC_INST) begin
case (opcode)
5'h1b: newpc = pc + imm;
5'h19: newpc = rs1 + imm;
5'h18: newpc = cond ? pc + imm : pc + 4;
default: newpc = pc + 4;
endcase
end else begin
newpc = pc;
end
/* pc */
always @(posedge wClk)
if (!nwReset) begin
pc <= 32'h00000074;
end else begin
pc <= newpc;
end
/* read and readaddr */
always @(state or pc or opcode or imm or rs1 or nwReset)
if (~nwReset) begin
wRead = 0;
bReadAddr = 0;
end else begin
wRead = 1;
bReadAddr = newpc;
if (state == `RISCVSTATE_EXEC_INST) begin
if (opcode == 5'h00) begin /*LOAD*/
wRead = 1;
bReadAddr = rs1 + imm;
end else if (opcode == 5'h08) begin /*STORE*/
wRead = 0;
bReadAddr = 0;
end
end
end
wire [31:0] newwriteaddr = rs1 + imm;
/* write */
always @(nwReset or state or opcode or newwriteaddr or rs1 or imm or rs2)
begin
write = 0;
writeaddr = 0;
writemask = 0;
writedata = 0;
if (nwReset && (state == `RISCVSTATE_EXEC_INST) && (opcode == 5'h08)) begin
/* riscv支持地址不对齐访问，但是假定写在一个32位字中 */
writeaddr = newwriteaddr;
writemask = 4'h0;
writedata = rs2;
write = 1'b1;
case (func3)
0:/*sb*/ begin
case (newwriteaddr[1:0])
0: begin
writemask = 4'he;
writedata = rs2;
end
1: begin
writemask = 4'hd;
writedata = {rs2[23:0], 8'h0};
end
2: begin
writemask = 4'hb;
writedata = {rs2[15:0], 16'h0};
end
3: begin
writemask = 4'h7;
writedata = {rs2[7:0], 24'h0};
end
endcase
end
1:/*sh*/ begin
case (newwriteaddr[1:0])
0: begin
writemask = 4'hc;
writedata = rs2;
end
1: begin
writemask = 4'h9;
writedata = {rs2[23:0], 8'h0};
end
2: begin
writemask = 4'h3;
writedata = {rs2[15:0], 16'h0};
end
endcase
end
endcase
end
end
reg [31:0] ldaddr;
always @(posedge wClk)
if (state == `RISCVSTATE_EXEC_INST) begin
ldaddr <= rs1 + imm;
end
always @(state or ldaddr or func3_r or rd_r or bReadData or divclk or imm or pc or rs1 or rs2 or instr) begin
dstvalue = 0;
dstreg = 0;
case (state)
`RISCVSTATE_WAIT_LD: begin
dstreg = rd_r;
case (func3_r)
0: begin
case (ldaddr[1:0])
0: dstvalue = {{24{bReadData[7]}}, bReadData[7:0]};
1: dstvalue = {{24{bReadData[15]}}, bReadData[15:8]};
2: dstvalue = {{24{bReadData[23]}}, bReadData[23:16]};
3: dstvalue = {{24{bReadData[31]}}, bReadData[31:24]};
endcase
end
1: begin
case (ldaddr[1:0])
0: dstvalue = {{16{bReadData[15]}}, bReadData[15:0]};
1: dstvalue = {{16{bReadData[23]}}, bReadData[23:8]};
2: dstvalue = {{16{bReadData[31]}}, bReadData[31:16]};
3: dstvalue = 32'hdeadbeef;
endcase
end
2: dstvalue = bReadData;
4: begin
case (ldaddr[1:0])
0: dstvalue = {24'b0, bReadData[7:0]};
1: dstvalue = {24'b0, bReadData[15:8]};
2: dstvalue = {24'b0, bReadData[23:16]};
3: dstvalue = {24'b0, bReadData[31:24]};
endcase
end
5: begin
case (ldaddr[1:0])
0: dstvalue = {16'b0, bReadData[15:0]};
1: dstvalue = {16'b0, bReadData[23:8]};
2: dstvalue = {16'b0, bReadData[31:16]};
3: dstvalue = 32'hdeadbeef;
endcase
end
endcase
end
`RISCVSTATE_WAIT_DIV: if (divclk == 0) begin
case (func3_r[1:0])
0: begin //div
dstreg = rd_r;
dstvalue = divs_result;
end
1: begin //divu
dstreg = rd_r;
dstvalue = div_result;
end
2: begin//rem
dstreg = rd_r;
dstvalue = mods_result;
end
3: begin //remu
dstreg = rd_r;
dstvalue = mod_result;
end
endcase
end
`RISCVSTATE_EXEC_INST: begin
dstreg = rd;
case (opcode)
5'h0d: begin
dstvalue = imm;
end
5'h05: begin
dstvalue = imm + pc;
end
5'h1b: begin
dstvalue = pc + 4;
end
5'h19: begin
dstvalue = pc + 4;
end
5'h04: begin /* alui */
case (func3)
0:/*addi*/ dstvalue = rs1 + imm;
1:/*slli*/ dstvalue = rs1 << imm[4:0];
2:/*slti*/ dstvalue = (rs1_s < imm_s) ? 1 : 0;
3:/*sltiu*/dstvalue = (rs1 < imm) ? 1 : 0;
4:/*xori*/ dstvalue = rs1 ^ imm;
5:/*srli/srai*/
dstvalue = instr[30] ? (rs1_s >> imm[4:0]) : (rs1 >> imm[4:0]);
6:/*ori*/ dstvalue = rs1 | imm;
7:/*andi*/ dstvalue = rs1 & imm;
default: begin dstreg = 0; dstvalue=0; end
endcase
end
5'h0c: begin /*alu*/
if (instr[25]) begin /* is MUL/DIV instr*/
case (func3)
0: begin //mul
dstvalue = muls_result[31:0];
end
1: begin //mulh
dstvalue = muls_result[63:32];
end
2: begin //mulhsu
dstvalue = mulsu_result[63:32];
end
3: begin //mulhu
dstvalue = mul_result[63:32];
end
4: begin //div
if (rs2 == 0) begin
dstvalue = 32'hffffffff;
end else begin
dstreg = 0;
dstvalue = 0;
end
end
5: begin //divu
if (rs2 == 0) begin
dstvalue = 32'hffffffff;
end else begin
dstreg = 0;
dstvalue = 0;
end
end
6: begin//rem
if (rs2 == 0) begin
dstvalue = rs1;
end else begin
dstreg = 0;
dstvalue = 0;
end
end
7: begin //remu
if (rs2 == 0) begin
dstvalue = rs1;
end else begin
dstreg = 0;
dstvalue = 0;
end
end
endcase
end else begin
case (func3)
0: begin
if (instr[30])
dstvalue = sub_result;
else
dstvalue = add_result;
end
1: begin //sll
dstvalue = rs1 << rs2[4:0];
end
2: begin //slt
dstvalue = (rs1_s < rs2_s) ? 1 : 0;
end
3: begin //sltu
dstvalue = (rs1 < rs2) ? 1 : 0;
end
4: begin //xor
dstvalue = rs1 ^ rs2;
end
5: begin //srl/sra
if (instr[30])
dstvalue = rs1 >> rs2[4:0];
else
dstvalue = rs1_s >> rs2[4:0];
end
6: begin //or
dstvalue = rs1 | rs2;
end
7: begin //and
dstvalue = rs1 & rs2;
end
endcase
end
end
default: begin
dstreg = 0;
dstvalue = 0;
end
endcase
end
endcase
end
endmodule
\ No newline at end of file
examples/hdl4se_riscv/verilog/riscv_sim_v4.v
浏览文件 @ 5b9662b9
......@@ -63,6 +63,21 @@ module ram8kb (
output [31:0] q);
endmodule
(*
HDL4SE="LCOM",
CLSID="2E577C6B-2FF1-425E-90B3-947EB523B863",
softmodule="hdl4se"
*)
module regfile (
input [4:0] address,
input [3:0] byteena,
input clock,
input [31:0] data,
input wren,
output [31:0] q);
endmodule
(*
HDL4SE="LCOM",
CLSID="76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2",
......@@ -98,8 +113,24 @@ module top(input wClk, nwReset);
wire [29:0] ramaddr;
assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];
wire [4:0] regno;
wire [3:0] regena;
wire [31:0] regwrdata;
wire regwren;
wire [31:0] regrddata;
wire [4:0] regno2;
wire [3:0] regena2;
wire [31:0] regwrdata2;
wire regwren2;
wire [31:0] regrddata2;
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
ram8kb ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
digitled led(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadDataKey);
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData);
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
regno, regena, regwrdata, regwren, regrddata,
regno2, regena2, regwrdata2, regwren2, regrddata2
);
endmodule
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