202109012059

examples/hdl4se_riscv/de2/de2_riscv_v3.qsf

@@ -993,8 +993,8 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE ../verilog/uart/uart_ctrl.v
 set_global_assignment -name VERILOG_FILE ../verilog/altera/uart/uart_fifo.v
-set_global_assignment -name VERILOG_FILE ../verilog/altera/uart/uart_ctrl.v
 set_global_assignment -name VERILOG_FILE ../verilog/altera/uart/altera_uart.v
 set_global_assignment -name VERILOG_FILE ../verilog/altera/regfile/regfile.v
 set_global_assignment -name VERILOG_FILE ../verilog/altera/ram/ram128kB.v

examples/hdl4se_riscv/de2/de2_riscv_v3.v

@@ -455,7 +455,7 @@ inout 		    [35:0]		GPIO;
 
     regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
     regfile    regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
-    ram128kB    ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
+    ram16kB    ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
 	riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
                 regno, regena, regwrdata, regwren, (lastregno == 0) ? 0 : regrddata,
 				regno2, regena2, regwrdata2, regwren2, (lastregno2 == 0) ? 0 : regrddata2

examples/hdl4se_riscv/de2/de2_riscv_v4.qpf

+DATE = "19:51:38 September 01, 2021"
+QUARTUS_VERSION = "12.0"
+
+# Revisions
+
+PROJECT_REVISION = "de2_riscv_v4"

examples/hdl4se_riscv/de2/de2_riscv_v4.sdc

+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 20 [get_ports CLOCK2_50]
+create_clock -period 20 [get_ports CLOCK3_50]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+

examples/hdl4se_riscv/test_code/console.c

@@ -292,7 +292,7 @@ void dispmem()
 				temp[0] = disp[i];
 			}
 			else {
-				temp[0] = ' ';
+				temp[0] = '.';
 			}
 			temp[1] = 0;
 			_strcat(buf, temp);
@@ -315,6 +315,8 @@ int main(int argc, char* argv[])
 		char buf[256];
 		_puts(">>");
 		_gets(buf, 255);
+		_puts(":");
+		_puts(buf);
 		if (_strncmp(buf, "help ", 4) == 0) {
 			_puts("  d <addr> -- display memory \n");
 			_puts("  b <baudrate> -- set baudrate \n");