PLIC interrupt number starts at 1 instead of 0.

* used to test nanhu's alias mechanism

* define `TEST_L3` in beu.c to test l3 cache ecc error
* undefine `TEST_L3` in beu.c to test beu

* Test the workflow of bus error unit when an ecc error occurs

* Now the following four testcases can be covered:
* Dma_master send write to cpu_dma, and hit the l3, so no transaction to real ddr
* Dma_master send write to cpu_dma, and miss the l3, so there will i_soc.mem port write real ddr
* Dma_master send read to cpu_dma, and hit the l3, so no transaction to real ddr
* Dma_master send read to cpu_dma, and miss the l3, so there will i_soc.mem port read read ddr

shrink PMEM size to reduce test setup time
add sfence.vma before accessing any newly mapped virtual addresses

* migrate from riscv-tests

check RTC increments during a loop to make sure that RTC does not tick too fast

MMIO llcop takes time to take effect. Delay needs to be added before
checking llcop result.

Only 64 writes now.