amtest,xsconfig: Support 256 external interrupt bits tests

am/src/xs/include/xs.h

@@ -7,15 +7,18 @@
 
 #include ISA_H // "x86.h", "mips32.h", ...
 
+#define MAX_EXTERNAL_INTR 256UL
+#define MAX_INTERNAL_INTR 10UL
+
 #if defined(__ARCH_RISCV64_NOOP) || defined(__ARCH_RISCV32_NOOP) || defined(__ARCH_RISCV64_XS)
 #define INTR_GEN_ADDR          (0x40070000UL)
-#define INTR_RANDOM            (0x40070008UL)
-#define INTR_RANDOM_MASK       (0x40070010UL)
+#define INTR_RANDOM            (INTR_GEN_ADDR + MAX_EXTERNAL_INTR)
+#define INTR_RANDOM_MASK       (INTR_GEN_ADDR + MAX_EXTERNAL_INTR*2)
 #define PLIC_BASE_ADDR         (0x3c000000UL)
 #elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
 #define INTR_GEN_ADDR          (0x1f00060000UL)
-#define INTR_RANDOM            (0x1f00060008UL)
-#define INTR_RANDOM_MASK       (0x1f00060010UL)
+#define INTR_RANDOM            (INTR_GEN_ADDR + MAX_EXTERNAL_INTR)
+#define INTR_RANDOM_MASK       (INTR_GEN_ADDR + MAX_EXTERNAL_INTR*2)
 #define PLIC_BASE_ADDR         (0x1f1c000000UL)
 #endif
 

am/src/xs/isa/riscv/plic.c

@@ -29,9 +29,6 @@
 // External interrupts start with index PLIC_EXT_INTR_OFFSET
 #define PLIC_EXT_INTR_OFFSET   1
 
-#define MAX_EXTERNAL_INTR 64
-#define MAX_INTERNAL_INTR 10
-
 // CSR.MIE
 #define MEIE 11
 #define SEIE 9

tests/amtest/src/tests/extintr.c

@@ -29,9 +29,6 @@
 // External interrupts start with index PLIC_EXT_INTR_OFFSET
 #define PLIC_EXT_INTR_OFFSET   1
 
-#define MAX_EXTERNAL_INTR 64
-#define MAX_INTERNAL_INTR 10
-
 // CSR.MIE
 #define MEIE 11
 #define SEIE 9
@@ -169,7 +166,7 @@ void random_trigger() {
   for (int i = 0; i < (MAX_EXTERNAL_INTR + 31) / 32; i++) {
     WRITE_WORD(INTR_RANDOM_ADDR(i), 0xffffffff);
   }
-  for (int i = 0; i < (MAX_EXTERNAL_INTR + 32) / 32; i++) {
+  for (int i = 0; i < (MAX_EXTERNAL_INTR + 31) / 32; i++) {
     WRITE_WORD(PLIC_ENABLE(CONTEXT_S) + i * 4, 0xffffffff);
   }
   void hello_intr_n(int n);