- 10 6月, 2023 5 次提交
-
-
由 zhanglyGit 提交于
-
由 zhanglyGit 提交于
-
由 zhanglyGit 提交于
-
由 zhanglyGit 提交于
-
由 zhanglyGit 提交于
-
- 05 6月, 2023 3 次提交
-
-
由 zhanglyGit 提交于
-
由 huxuan0307 提交于
Merge newest modification of master
-
由 Xuan Hu 提交于
-
- 04 6月, 2023 28 次提交
-
-
由 sfencevma 提交于
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
-
由 Maxpicca 提交于
-
由 sfencevma 提交于
* LoadQueueReplay: fix worst case, all oldest instructions are allocated to the same bank, and the number of instructions is greater than the number of stages in load unit. * Remove bank conflict block * Increase priority for data replay The deadlock scenario is as follows: The LoadQueueReplay entry will not be released immediately after the instruction is replayed from LoadQueueReplay. For example, after instruction a is replayed from LoadQueueReplay, entry 1 is still valid. If instruction a still needs to be replayed, Entry 1 will be updated again, otherwise entry 1 can be released. If only the time of the first enqueue is used to select replay instructions (age matrix), when there are too many instructions (in LoadQueueReplay) to be replay, some instructions may not be selected. Using the pointer ldWbPtr of the oldest instruction, when the saved lqIdx of the instruction is equal to ldWbPtr and can be replayed, LoadQueueReplay will give priority to the instruction instead of using the selection result of the age matrix. To select older instructions, LoadQueueReplay will calculate pointers such as ldWbPtr, ldWbPtr+1, ldWbPtr+2, ldWbPtr+3..., and if the lqIdx of the instruction is in these results, it will be selected first. When the pointer is compared, there will be an n-bit long mask, and LoadQueueReplay will be from 0 to n-1. When i th bit is valid, select i th instruction. The stride of the pointer comparison is larger than the number of pipeline stages of the load unit, and the selected instruction still needs to be replayed after the first replay (for example, the data is not ready). Worse, in the bit of the mask generated by pointer comparison, the instructions (lqIdx is ldWbPtr+1, ldWbPtr+2, ...) after the oldest instruction (lqIdx is equal to ldWbPtr) are in the lower bit and the oldest instruction is in the higher bit. It cannot select the oldest instruction.
-
由 sfencevma 提交于
This commit provides MDP adaptation for #2077 * fix mdp: disable LFST, ssing ssid comparison instead of LFST * add loadWaitStrict when compare SSID * fix store data wakeup logic Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
* The input of VIMac data module should be exchanged when opcode is vmadd or vnmsub, since source data are not exchanged in data module.
-
由 Xuan Hu 提交于
* Vector source data should be localed at high bits of vimacs.vs1|2, when widen=1 and vuopIdx is a odd number * The odd uop of widen insts should use high part of vs1 and vs2. * The eew of widen insts should be double of sew.
-
由 Xuan Hu 提交于
* Width of vlMapVdIdx should be 4-bit, because vl can equal to VLEN. In this case, vlMapVdIdx is 8.
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 zhanglyGit 提交于
-
由 zhanglyGit 提交于
-
由 zhanglyGit 提交于
-
由 Ziyue Zhang 提交于
-
由 xgkiri 提交于
-
由 zhanglyGit 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
- 30 5月, 2023 1 次提交
-
-
由 Xuan Hu 提交于
-
- 25 5月, 2023 3 次提交
-
-
由 Xuan Hu 提交于
# Conflicts: # .gitmodules # build.sc # src/main/scala/top/Configs.scala # src/main/scala/xiangshan/Bundle.scala # src/main/scala/xiangshan/Parameters.scala # src/main/scala/xiangshan/XSCore.scala # src/main/scala/xiangshan/backend/CtrlBlock.scala # src/main/scala/xiangshan/backend/MemBlock.scala # src/main/scala/xiangshan/backend/Scheduler.scala # src/main/scala/xiangshan/backend/issue/ReservationStation.scala # src/main/scala/xiangshan/backend/issue/StatusArray.scala # src/main/scala/xiangshan/backend/rob/Rob.scala # src/main/scala/xiangshan/mem/MemCommon.scala # src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala # src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala # src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala # src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala # src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
-
由 wakafa 提交于
* icache: Acquire -> Get to L2 * gitmodules: add coupledL2 as submodule * cpl2: merge coupledL2 into master * Changes includes: * coupledL2 integration * modify user&echo fields in i$/d$/ptw * set d$ never always-releasedata * remove hw perfcnt connection for L2 * bump utility * icache: remove unused releaseUnit * config: minimalconfig includes l2 * Otherwise, dirty bits maintainence may be broken * Known issue: L2 should have more than 1 bank to avoid compiling problem * bump Utility * bump coupledL2: fix bugs in dual-core * bump coupledL2 * icache: set icache as non-coherent node * bump coupledL2: fix dirty problem in L2 ProbeAckData --------- Co-authored-by: Nguohongyu <20373696@buaa.edu.cn> Co-authored-by: NXiChen <chenxi171@mails.ucas.ac.cn>
-
由 wakafa 提交于
* script: enable chiseldb by default on running emu by xiangshan.py * script: move db file to wave_home if emu failed
-