- 21 9月, 2020 2 次提交
- 19 9月, 2020 1 次提交
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由 Yinan Xu 提交于
MetaArray: fixed debug output format string.
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- 18 9月, 2020 1 次提交
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由 Allen 提交于
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- 17 9月, 2020 2 次提交
- 16 9月, 2020 3 次提交
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由 Allen 提交于
Now DCache has several configurable parameters: 1. nSets 2. nWays 3. blockByte(size block in bytes) 4. rowBits(basic storage unit of cache, the width of a signal sram bank) 5. wordBits(inner cpu bus width) = DataBits = XLEN = 64 6. beatBits(outer tilelink bus width) = l1BusDataWidth = 256 Now, we require beatBits >= rowBits >= wordBits.
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由 Allen 提交于
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由 Yinan Xu 提交于
Update difftest to support Linux snapshot
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- 15 9月, 2020 9 次提交
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由 Allen 提交于
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由 Allen 提交于
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由 Allen 提交于
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由 Allen 提交于
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由 Allen 提交于
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由 zhanglinjuan 提交于
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由 Allen 提交于
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由 Allen 提交于
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由 William Wang 提交于
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- 14 9月, 2020 4 次提交
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由 Allen 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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- 13 9月, 2020 2 次提交
- 12 9月, 2020 7 次提交
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由 William Wang 提交于
* It will make snapshot more precise * NEMU that includes commit d4efeb7 is needed to use difftest
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由 jinyue110 提交于
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由 jinyue110 提交于
also surport 64 bit bus
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由 linjiawei 提交于
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由 LinJiawei 提交于
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由 jinyue110 提交于
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由 zhanglinjuan 提交于
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- 11 9月, 2020 6 次提交
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由 GouLingrui 提交于
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由 GouLingrui 提交于
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由 Allen 提交于
Only assert not correctable when we hit and has valid data.
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由 Allen 提交于
Now, data array write port priority: store pipe > atomics pipe > refill. When atomics runs, store are all flushed out, new stores are blocked. So there will be no store competing for data write port. But refill may compete for data write port even if atomics runs with no spec exec! This is how it happens: speculative load misses goes to miss queue but this load was later killed and atomics starts running. Miss queue gets data and starts to refill, competing for data array write port. Atomics pipe fails to get data write port, assertion fails.
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由 Allen 提交于
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由 Allen 提交于
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- 10 9月, 2020 3 次提交