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提交 fd2e07ef 编写于 作者: J jinyue110
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Merge branch 'master' into dev-icache

上级 44c9312c 35bb7ef9
隐藏空白更改
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Showing with 122 addition and 86 deletion
src/main/scala/utils/BitUtils.scala
浏览文件 @ fd2e07ef
......@@ -22,14 +22,14 @@ object SignExt {
def apply(a: UInt, len: Int) = {
val aLen = a.getWidth
val signBit = a(aLen-1)
if (aLen == len) a else Cat(Fill(len - aLen, signBit), a)
if (aLen >= len) a(len-1,0) else Cat(Fill(len - aLen, signBit), a)
}
}
object ZeroExt {
def apply(a: UInt, len: Int) = {
val aLen = a.getWidth
if (aLen == len) a else Cat(0.U((len - aLen).W), a)
if (aLen >= len) a(len-1,0) else Cat(0.U((len - aLen).W), a)
}
}
......@@ -77,3 +77,14 @@ object HighestBit {
Reverse(LowestBit(Reverse(a), len))
}
}
object GenMask {
// generate w/r mask
def apply(high: Int, low: Int) = {
require(high > low)
VecInit(List.fill(high+1)(true.B)).asUInt >> low << low
}
def apply(pos: Int) = {
1.U << pos
}
}
\ No newline at end of file
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @ fd2e07ef
......@@ -53,11 +53,11 @@ trait HasCSRConst {
// Supervisor Protection and Translation
val Satp = 0x180
// Machine Information Registers
val Mvendorid = 0xF11
val Marchid = 0xF12
val Mimpid = 0xF13
val Mhartid = 0xF14
// Machine Information Registers
val Mvendorid = 0xF11
val Marchid = 0xF12
val Mimpid = 0xF13
val Mhartid = 0xF14
// Machine Trap Setup
val Mstatus = 0x300
......@@ -84,17 +84,18 @@ trait HasCSRConst {
val PmpaddrBase = 0x3B0
// Machine Counter/Timers
// Currently, NOOP uses perfcnt csr set instead of standard Machine Counter/Timers
// Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers
// 0xB80 - 0x89F are also used as perfcnt csr
// Machine Counter Setup (not implemented)
// Debug/Trace Registers (shared with Debug Mode) (not implemented)
// Debug Mode Registers (not implemented)
def privEcall = 0x000.U
def privMret = 0x302.U
def privSret = 0x102.U
def privUret = 0x002.U
def privEcall = 0x000.U
def privEbreak = 0x001.U
def privMret = 0x302.U
def privSret = 0x102.U
def privUret = 0x002.U
def ModeM = 0x3.U
def ModeH = 0x2.U
......@@ -118,6 +119,12 @@ trait HasCSRConst {
IRQ_SEIP, IRQ_SSIP, IRQ_STIP,
IRQ_UEIP, IRQ_USIP, IRQ_UTIP
)
def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = {
val readOnly = addr(11,10) === "b11".U
val lowestAccessPrivilegeLevel = addr(9,8)
mode >= lowestAccessPrivilegeLevel && !(wen && readOnly)
}
}
trait HasExceptionNO {
......@@ -137,18 +144,18 @@ trait HasExceptionNO {
def storePageFault = 15
val ExcPriority = Seq(
breakPoint, // TODO: different BP has different priority
instrPageFault,
instrAccessFault,
illegalInstr,
instrAddrMisaligned,
ecallM, ecallS, ecallU,
storeAddrMisaligned,
loadAddrMisaligned,
storePageFault,
loadPageFault,
storeAccessFault,
loadAccessFault
breakPoint, // TODO: different BP has different priority
instrPageFault,
instrAccessFault,
illegalInstr,
instrAddrMisaligned,
ecallM, ecallS, ecallU,
storePageFault,
loadPageFault,
storeAccessFault,
loadAccessFault,
storeAddrMisaligned,
loadAddrMisaligned
)
}
......@@ -201,13 +208,15 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
class MstatusStruct extends Bundle {
val sd = Output(UInt(1.W))
val pad1 = Output(UInt((XLEN-37).W))
val sxl = Output(UInt(2.W))
val uxl = Output(UInt(2.W))
val pad0 = Output(UInt(9.W))
val pad1 = if (XLEN == 64) Output(UInt(27.W)) else null
val sxl = if (XLEN == 64) Output(UInt(2.W)) else null
val uxl = if (XLEN == 64) Output(UInt(2.W)) else null
val pad0 = if (XLEN == 64) Output(UInt(9.W)) else Output(UInt(8.W))
val tsr = Output(UInt(1.W))
val tw = Output(UInt(1.W))
val tvm = Output(UInt(1.W)) // TODO: add excp check
val tvm = Output(UInt(1.W))
val mxr = Output(UInt(1.W))
val sum = Output(UInt(1.W))
val mprv = Output(UInt(1.W))
......@@ -244,17 +253,17 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
val mie = RegInit(0.U(XLEN.W))
val mipWire = WireInit(0.U.asTypeOf(new Interrupt))
val mipReg = RegInit(0.U.asTypeOf(new Interrupt).asUInt)
val mipFixMask = "h777".U
val mipFixMask = GenMask(9) | GenMask(5) | GenMask(1)
val mip = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt)
def getMisaMxl(mxl: Int): UInt = (mxl.U << (XLEN-2)).asUInt()
def getMisaExt(ext: Char): UInt = (1.U << (ext.toInt - 'a'.toInt)).asUInt()
def getMisaMxl(mxl: Int): UInt = {mxl.U << (XLEN-2)}
def getMisaExt(ext: Char): UInt = {1.U << (ext.toInt - 'a'.toInt)}
var extList = List('a', 's', 'i', 'u')
if(HasMExtension){ extList = extList :+ 'm'}
if(HasCExtension){ extList = extList :+ 'c'}
if(HasFPU){ extList = extList ++ List('f', 'd')}
val misaInitVal = getMisaMxl(2) | extList.foldLeft(0.U)((sum, i) => sum | getMisaExt(i)) //"h8000000000141105".U
val misa = RegInit(UInt(XLEN.W), misaInitVal)
val misaInitVal = getMisaMxl(2) | extList.foldLeft(0.U)((sum, i) => sum | getMisaExt(i)) //"h8000000000141105".U
val misa = RegInit(UInt(XLEN.W), misaInitVal)
// MXL = 2 | 0 | EXT = b 00 0000 0100 0001 0001 0000 0101
// (XLEN-1, XLEN-2) | |(25, 0) ZY XWVU TSRQ PONM LKJI HGFE DCBA
......@@ -272,24 +281,31 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
// | pad0 |
// | tsr |
// | tw |
// | tvm | // TODO: add excp check 3.1.6.4
// | tvm |
// | mxr |
// | sum |
// | mprv |
// | xs | 00 |
// | fs |
// | fs | 00 |
// | mpp | 00 |
// | hpp | 00 |
// | spp | 0 |
// | pie | 0000 |
// | pie | 0000 | pie.h is used as UBE
// | ie | 0000 | uie hardlinked to 0, as N ext is not implemented
val mstatusStruct = mstatus.asTypeOf(new MstatusStruct)
def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
val mstatusNew = Cat(mstatusOld.fs === "b11".U, mstatus(XLEN-2, 0))
val mstatusNew = Cat(mstatusOld.xs === "b11".U || mstatusOld.fs === "b11".U, mstatus(XLEN-2, 0))
mstatusNew
}
val mstatusMask = ~ZeroExt((
GenMask(XLEN-2, 38) | GenMask(31, 23) | GenMask(10, 9) | GenMask(2) |
GenMask(37) | // MBE
GenMask(36) | // SBE
GenMask(6) // UBE
), 64)
val medeleg = RegInit(UInt(XLEN.W), 0.U)
val mideleg = RegInit(UInt(XLEN.W), 0.U)
val mscratch = RegInit(UInt(XLEN.W), 0.U)
......@@ -319,9 +335,16 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
// val sie = RegInit(0.U(XLEN.W))
val sieMask = "h222".U & mideleg
val sipMask = "h222".U & mideleg
<<<<<<< HEAD
// val satp = RegInit(0.U(XLEN.W))
val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U) // only use for tlb naive debug
val satpMask = "hf0000fffffffffff".U // disable asid
=======
val satp = RegInit(0.U(XLEN.W))
// val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U) // only use for tlb naive debug
val satpMask = "h80000fffffffffff".U // disable asid, mode can only be 8 / 0
// val satp = RegInit(UInt(XLEN.W), 0.U)
>>>>>>> master
val sepc = RegInit(UInt(XLEN.W), 0.U)
val scause = RegInit(UInt(XLEN.W), 0.U)
val stval = Reg(UInt(XLEN.W))
......@@ -451,9 +474,9 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
// Machine Trap Setup
// MaskedRegMap(Mstatus, mstatus, "hffffffffffffffee".U, (x=>{printf("mstatus write: %x time: %d\n", x, GTimer()); x})),
MaskedRegMap(Mstatus, mstatus, "hffffffffffffffff".U, mstatusUpdateSideEffect),
MaskedRegMap(Mstatus, mstatus, mstatusMask, mstatusUpdateSideEffect, mstatusMask),
MaskedRegMap(Misa, misa), // now MXL, EXT is not changeable
MaskedRegMap(Medeleg, medeleg, "hbbff".U),
MaskedRegMap(Medeleg, medeleg, "hf3ff".U),
MaskedRegMap(Mideleg, mideleg, "h222".U),
MaskedRegMap(Mie, mie),
MaskedRegMap(Mtvec, mtvec),
......@@ -493,14 +516,15 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
))
// satp wen check
val satpLegalMode = (wdata.asTypeOf(new SatpStruct).mode===0.U) || (wdata.asTypeOf(new SatpStruct).mode===8.U)
val wen = valid && func =/= CSROpType.jmp && Mux(addr===Satp.U, satpLegalMode, true.B)
// TODO: problem: is wen under mode check?
// if satp.mode is illegal, will not write
// Debug(){when(wen){printf("[CSR] addr %x wdata %x func %x rdata %x\n", addr, wdata, func, rdata)}}
MaskedRegMap.generate(mapping, addr, rdata, wen, wdata)
val satpLegalMode = (wdata.asTypeOf(new SatpStruct).mode===0.U) || (wdata.asTypeOf(new SatpStruct).mode===8.U)
// general CSR wen check
val wen = valid && func =/= CSROpType.jmp && (addr=/=Satp.U || satpLegalMode)
val permitted = csrAccessPermissionCheck(addr, false.B, priviledgeMode)
// Writeable check is ingored.
// Currently, write to illegal csr addr will be ignored
MaskedRegMap.generate(mapping, addr, rdata, wen && permitted, wdata)
io.out.bits := rdata
val isIllegalAddr = MaskedRegMap.isIllegalAddr(mapping, addr)
// Fix Mip/Sip write
val fixMapping = Map(
......@@ -523,7 +547,7 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
io.fpu_csr.frm := fcsr.asTypeOf(new FcsrStruct).frm
// CSR inst decode
val ret = Wire(Bool())
val isEbreak = addr === privEbreak && func === CSROpType.jmp
val isEcall = addr === privEcall && func === CSROpType.jmp
val isMret = addr === privMret && func === CSROpType.jmp
val isSret = addr === privSret && func === CSROpType.jmp
......@@ -532,8 +556,13 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
XSDebug(wen, "csr write: pc %x addr %x rdata %x wdata %x func %x\n", io.cfIn.pc, addr, rdata, wdata, func)
XSDebug(wen, "pc %x mstatus %x mideleg %x medeleg %x mode %x\n", io.cfIn.pc, mstatus, mideleg , medeleg, priviledgeMode)
// Illegal priviledged operation list
val illegalSModeSret = valid && isSret && priviledgeMode === ModeS && mstatusStruct.tsr.asBool
// MMU Permission Check
// Illegal priviledged instruction check
val isIllegalAddr = MaskedRegMap.isIllegalAddr(mapping, addr)
val isIllegalAccess = !permitted
val isIllegalPrivOp = illegalSModeSret
// def MMUPermissionCheck(ptev: Bool, pteu: Bool): Bool = ptev && !(priviledgeMode === ModeU && !pteu) && !(priviledgeMode === ModeS && pteu && mstatusStruct.sum.asBool)
// def MMUPermissionCheckLoad(ptev: Bool, pteu: Bool): Bool = ptev && !(priviledgeMode === ModeU && !pteu) && !(priviledgeMode === ModeS && pteu && mstatusStruct.sum.asBool) && (pter || (mstatusStruct.mxr && ptex))
......@@ -565,11 +594,15 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
tlbBundle.priv.dmode := Mux(mstatusStruct.mprv.asBool, mstatusStruct.mpp, priviledgeMode)
val hasInstrPageFault = io.exception.bits.cf.exceptionVec(instrPageFault) && io.exception.valid
val hasLoadPageFault = false.B // FIXME: add ld-pf/st-pf
val hasStorePageFault = false.B
val hasStoreAddrMisaligned = io.exception.bits.cf.exceptionVec(storeAddrMisaligned)
val hasLoadAddrMisaligned = io.exception.bits.cf.exceptionVec(loadAddrMisaligned)
val hasLoadPageFault = io.exception.bits.cf.exceptionVec(loadPageFault) && io.exception.valid
val hasStorePageFault = io.exception.bits.cf.exceptionVec(storePageFault) && io.exception.valid
val hasStoreAddrMisaligned = io.exception.bits.cf.exceptionVec(storeAddrMisaligned) && io.exception.valid
val hasLoadAddrMisaligned = io.exception.bits.cf.exceptionVec(loadAddrMisaligned) && io.exception.valid
// mtval write logic
val memExceptionAddr = WireInit(0.U(VAddrBits.W))
ExcitingUtils.addSource(io.exception.bits.lsroqIdx, "EXECPTION_LSROQIDX")
ExcitingUtils.addSink(memExceptionAddr, "EXECPTION_VADDR")
when(hasInstrPageFault || hasLoadPageFault || hasStorePageFault){
val tval = Mux(
hasInstrPageFault,
......@@ -578,8 +611,7 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
SignExt(io.exception.bits.cf.pc + 2.U, XLEN),
SignExt(io.exception.bits.cf.pc, XLEN)
),
// SignExt(io.dmemMMU.addr, XLEN)
"hffffffff".U // FIXME: add ld/st pf
SignExt(memExceptionAddr, XLEN)
)
when(priviledgeMode === ModeM){
mtval := tval
......@@ -588,11 +620,9 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
}
}
val lsuAddr = WireInit(0.U(64.W))
BoringUtils.addSink(lsuAddr, "LSUADDR")
when(hasLoadAddrMisaligned || hasStoreAddrMisaligned)
{
mtval := SignExt(lsuAddr, XLEN)
mtval := SignExt(memExceptionAddr, XLEN)
}
// Exception and Intr
......@@ -622,11 +652,14 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
// exceptions
val csrExceptionVec = Wire(Vec(16, Bool()))
csrExceptionVec.map(_ := false.B)
csrExceptionVec(breakPoint) := io.in.valid && isEbreak
csrExceptionVec(ecallM) := priviledgeMode === ModeM && io.in.valid && isEcall
csrExceptionVec(ecallS) := priviledgeMode === ModeS && io.in.valid && isEcall
csrExceptionVec(ecallU) := priviledgeMode === ModeU && io.in.valid && isEcall
// csrExceptionVec(instrPageFault) := hasInstrPageFault
csrExceptionVec(illegalInstr) := isIllegalAddr && wen // Trigger an illegal instr exception when unimplemented csr is being read/written // TODO: if csrrw under wrong priv mode will cause illegal instr now ?
// Trigger an illegal instr exception when:
// * unimplemented csr is being read/written
// * csr access is illegal
csrExceptionVec(illegalInstr) := (isIllegalAddr || isIllegalAccess) && wen
csrExceptionVec(loadPageFault) := hasLoadPageFault
csrExceptionVec(storePageFault) := hasStorePageFault
val iduExceptionVec = io.cfIn.exceptionVec
......@@ -644,7 +677,7 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
val retTarget = Wire(UInt(VAddrBits.W))
val trapTarget = Wire(UInt(VAddrBits.W))
ExcitingUtils.addSource(trapTarget, "trapTarget")
val resetSatp = addr === Satp.U && satpLegalMode && wen // write to satp will cause the pipeline be flushed
val resetSatp = addr === Satp.U && wen // write to satp will cause the pipeline be flushed
io.redirect := DontCare
io.redirectValid := (valid && func === CSROpType.jmp && !isEcall) || resetSatp
//TODO: use pred pc instead pc+4
......@@ -655,23 +688,13 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
XSDebug(raiseExceptionIntr, "int/exc: pc %x int (%d):%x exc: (%d):%x\n",io.exception.bits.cf.pc, intrNO, io.exception.bits.cf.intrVec.asUInt, exceptionNO, raiseExceptionVec.asUInt)
XSDebug(raiseExceptionIntr, "pc %x mstatus %x mideleg %x medeleg %x mode %x\n", io.exception.bits.cf.pc, mstatus, mideleg, medeleg, priviledgeMode)
XSDebug(io.redirectValid, "redirect to %x\n", io.redirect.target)
XSDebug(valid && isMret, "Mret to %x!\n[CSR] int/exc: pc %x int (%d):%x exc: (%d):%x\n",retTarget, io.cfIn.pc, intrNO, io.cfIn.intrVec.asUInt, exceptionNO, raiseExceptionVec.asUInt)
XSDebug(valid && isMret, "[MST] pc %x mstatus %x mideleg %x medeleg %x mode %x\n", io.cfIn.pc, mstatus, mideleg , medeleg, priviledgeMode)
XSDebug(valid && isSret, "Sret to %x!\n[CSR] int/exc: pc %x int (%d):%x exc: (%d):%x\n",retTarget, io.cfIn.pc, intrNO, io.cfIn.intrVec.asUInt, exceptionNO, raiseExceptionVec.asUInt)
XSDebug(valid && isSret, "pc %x mstatus %x mideleg %x medeleg %x mode %x\n", io.cfIn.pc, mstatus, mideleg , medeleg, priviledgeMode)
XSDebug(io.redirectValid, "Redirect %x raiseExcepIntr:%d valid:%d instrValid:%x \n", io.redirect.target, raiseExceptionIntr, valid, io.instrValid)
// Branch control
val deleg = Mux(raiseIntr, mideleg , medeleg)
// val delegS = ((deleg & (1 << (causeNO & 0xf))) != 0) && (priviledgeMode < ModeM);
val delegS = (deleg(causeNO(3,0))) && (priviledgeMode < ModeM)
val tvalWen = !(hasInstrPageFault || hasLoadPageFault || hasStorePageFault || hasLoadAddrMisaligned || hasStoreAddrMisaligned) || raiseIntr // in noop-riscv64, no exception will come together with PF
val tvalWen = !(hasInstrPageFault || hasLoadPageFault || hasStorePageFault || hasLoadAddrMisaligned || hasStoreAddrMisaligned) || raiseIntr // TODO: need check
ret := isMret || isSret || isUret
trapTarget := Mux(delegS, stvec, mtvec)(VAddrBits-1, 0)
retTarget := DontCare
// val illegalEret = TODO
......@@ -679,26 +702,26 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
when (valid && isMret) {
val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
// mstatusNew.mpp.m := ModeU //TODO: add mode U
mstatusNew.ie.m := mstatusOld.pie.m
priviledgeMode := mstatusOld.mpp
mstatusNew.pie.m := true.B
mstatusNew.mpp := ModeU
mstatusNew.mprv := 0.U
mstatus := mstatusNew.asUInt
// lr := false.B
retTarget := mepc(VAddrBits-1, 0)
}
when (valid && isSret) {
when (valid && isSret && !illegalSModeSret) {
val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
// mstatusNew.mpp.m := ModeU //TODO: add mode U
mstatusNew.ie.s := mstatusOld.pie.s
priviledgeMode := Cat(0.U(1.W), mstatusOld.spp)
mstatusNew.pie.s := true.B
mstatusNew.spp := ModeU
mstatus := mstatusNew.asUInt
// lr := false.B
mstatusNew.mprv := 0.U
// lr := false.B
retTarget := sepc(VAddrBits-1, 0)
}
......@@ -724,8 +747,7 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
mstatusNew.pie.s := mstatusOld.ie.s
mstatusNew.ie.s := false.B
priviledgeMode := ModeS
when(tvalWen){stval := 0.U} // TODO: should not use =/=
// printf("[*] mstatusNew.spp %x\n", mstatusNew.spp)
when(tvalWen){stval := 0.U}
// trapTarget := stvec(VAddrBits-1. 0)
}.otherwise {
mcause := causeNO
......@@ -734,15 +756,9 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
mstatusNew.pie.m := mstatusOld.ie.m
mstatusNew.ie.m := false.B
priviledgeMode := ModeM
when(tvalWen){mtval := 0.U} // TODO: should not use =/=
when(tvalWen){mtval := 0.U}
// trapTarget := mtvec(VAddrBits-1. 0)
}
// mstatusNew.pie.m := LookupTree(priviledgeMode, List(
// ModeM -> mstatusOld.ie.m,
// ModeH -> mstatusOld.ie.h, //ERROR
// ModeS -> mstatusOld.ie.s,
// ModeU -> mstatusOld.ie.u
// ))
mstatus := mstatusNew.asUInt
}
......
src/main/scala/xiangshan/mem/Lsroq.scala
浏览文件 @ fd2e07ef
......@@ -8,6 +8,7 @@ import xiangshan.cache._
import xiangshan.cache.{DCacheLoadIO, TlbRequestIO, MemoryOpConstants}
class LsRoqEntry extends XSBundle {
val vaddr = UInt(VAddrBits.W) // TODO: need opt
val paddr = UInt(PAddrBits.W)
val op = UInt(6.W)
val mask = UInt(8.W)
......@@ -139,6 +140,7 @@ class Lsroq extends XSModule {
writebacked(io.loadIn(i).bits.uop.lsroqIdx) := !io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio
// allocated(io.loadIn(i).bits.uop.lsroqIdx) := io.loadIn(i).bits.miss // if hit, lsroq entry can be recycled
data(io.loadIn(i).bits.uop.lsroqIdx).paddr := io.loadIn(i).bits.paddr
data(io.loadIn(i).bits.uop.lsroqIdx).vaddr := io.loadIn(i).bits.vaddr
data(io.loadIn(i).bits.uop.lsroqIdx).mask := io.loadIn(i).bits.mask
data(io.loadIn(i).bits.uop.lsroqIdx).data := io.loadIn(i).bits.data // for mmio / misc / debug
data(io.loadIn(i).bits.uop.lsroqIdx).mmio := io.loadIn(i).bits.mmio
......@@ -156,6 +158,7 @@ class Lsroq extends XSModule {
when(io.storeIn(i).fire()) {
valid(io.storeIn(i).bits.uop.lsroqIdx) := !io.storeIn(i).bits.mmio
data(io.storeIn(i).bits.uop.lsroqIdx).paddr := io.storeIn(i).bits.paddr
data(io.storeIn(i).bits.uop.lsroqIdx).vaddr := io.storeIn(i).bits.vaddr
data(io.storeIn(i).bits.uop.lsroqIdx).mask := io.storeIn(i).bits.mask
data(io.storeIn(i).bits.uop.lsroqIdx).data := io.storeIn(i).bits.data
data(io.storeIn(i).bits.uop.lsroqIdx).mmio := io.storeIn(i).bits.mmio
......@@ -636,6 +639,12 @@ class Lsroq extends XSModule {
XSDebug("uncache resp: data %x\n", io.dcache.resp.bits.data)
}
// Read vaddr for mem exception
val mexcLsroqIdx = WireInit(0.U(LsroqIdxWidth.W))
val memExceptionAddr = WireInit(data(mexcLsroqIdx(InnerLsroqIdxWidth - 1, 0)).vaddr)
ExcitingUtils.addSink(mexcLsroqIdx, "EXECPTION_LSROQIDX")
ExcitingUtils.addSource(memExceptionAddr, "EXECPTION_VADDR")
// misprediction recovery / exception redirect
// invalidate lsroq term using robIdx
val needCancel = Wire(Vec(LsroqSize, Bool()))
......
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