* FtqToICache add bypass write signal and use bypass signal

* IFU: ignore ICache access bundle

* ICacheMainPipe: expand meta/data access output to 4 identical vector
output, each output is connected to a copied register trigger by FTQ
requests

* IPrefetch/ReplacePipe: expand meta/data access outpu to 4 indentical
vector output, and each output is triggered by the same signal group

* add ICachPartWayArray to wrap a part-way module

* SRAM array array_0 array_1: width × 1/4 and depth stay unchanged

* separate ifu req and icache req for timing optimization

* both ifu ftq_req_ready and icache ftq_req_ready depend on each other

* ifu and icache has pc_mem register

[WIP]ICacheMainPipe: add copied registers

[WIP]ftq: read ftq_pc_mem one cycle ahead, reqs to be copied

[WIP] FTQ:  delete outside bypass

* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq

* ctrl: add data modules for pc and jalr_target

This commit adds two data modules for pc and jalr_target respectively.
They are the same as data modules in frontend. Should benefit timing.

* jump: reduce pc and jalr_target read latency

* ftq: add predecode redirect update target interface, valid only on ifuRedirect

* ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles
Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>

and remove all bypass for ftq_pc_mem

* without s2_valid, invalid pmp_af will cause wait_state turn into
wait_pmp_except and incorrect read data

- Move tag and idx compare to s1 in secondary miss

- Delay 1 cycle when PMP report an access fault and ICache miss

using RegNext causes a memory fetch req incorrectly perceived as a mmio
req

and improve parameterizaton of fromMicroBTBEntry

This reverts commit 99529e48.

This reverts commit 33b74280.

- Move tag and idx compare to s1 in secondary miss

- Delay 1 cycle when PMP report an access fault and ICache miss

using RegNext causes a memory fetch req incorrectly perceived as a mmio
req

* add one cycle stall to ftb miss update, and
* add one cycle delay to all other predictors

* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray)
req.ready

* IFU <bug-fix>: deal with itlb miss for resend

* IFU <bug fix>: enable crossPageFault for resend-pf
Co-authored-by: NDeltaZero <lacrosseelis@gmail.com>

* freelist & refcounter: implement arch states

* walk: restore and walk again when redirecting

* ROB: optimize invalidation of `valid`

* config: minimalconfig use non-inclusive L3 cache

* config: make simulation config dependent on FPGAPlatform

* axi4,mem: fix typo for pending_write_resp_id

* axi4,mem: fix has_write_resp condition

Usage:

When make emu, please use EMU_TRACE=1, EMU_TRACE=vcd or EMU_TRACE=VCD
to dump waveform of vcd format, and use EMU_TRACE=fst or EMU_TRACE=FST
to dump waveform of fst format.

When use xiangshan.py, please add --trace to dump waveform of vcd format,
and add --trace-fst to dump waveform of fst format.

Now we update data field (fwd data, uop) in load queue when load_s2
is valid. It will help to on lq wen fanout problem.

State flags will be treated differently. They are still updated
accurately according to loadIn.valid
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* ldu: optimize dcache hitvec wiring

In previous design, hitvec is generated in load s1, then send to dcache
and lsu (rs) side separately. As dcache and lsu (rs side) is far in real
chip, it caused severe wiring problem.

Now we generate 2 hitvec in parallel:

* hitvec 1 is generated near dcache.
To generate that signal, paddr from dtlb is sent to dcache in load_s1
to geerate hitvec. The hitvec is then sent to dcache to generate
data array read_way_en.

* hitvec 2 is generated near lsu and rs in load_s2, tag read result
from dcache, as well as coh_state, is sent to lsu in load_s1,
then it is used to calcuate hitvec in load_s2.  hitvec 2 is used
to generate hit/miss signal used by lsu.

It should fix the wiring problem caused by hitvec

* ldu: opt loadViolationQuery.resp.ready timing

An extra release addr register is added near lsu to speed up the
generation of loadViolationQuery.resp.ready

* l1tlb: replace NormalPage data module and add duplicate resp result

data module:
add BankedSyncDataMoudleWithDup data module:
divided the data array into banks and read as Async, bypass write data.
RegNext the data result * #banks. choose from the chosen data.

duplicate:
duplicate the chosen data and return to outside(tlb).
tlb return (ppn+perm) * #DUP to outside (for load unit only)

TODO: load unit use different tlb resp result to different module.
one for lsq, one for dcache.

* l1tlb: Fix wrong vidx_bypass logic after using duplicate data module

We use BankedSyncDataMoudleWithDup instead of SyncDataModuleTemplate,
whose write ports are not Vec.
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: NZhangZifei <1773908404@qq.com>
Co-authored-by: Ngood-circle <fenghaoyuan19@mails.ucas.ac.cn>

* AtomicsUnit: refactor FSM in AtomicsUnit

* send tlb req and sbuffer flush req at the same time
* remove s_cache_resp_latch state
* change `data_valid` logic: do not send dcache req until `data_valid`
is true

* Atomicsunit: add `s_cache_resp_latch` state back

* Update Artifact Evaluation badges to README.md