- 03 11月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 02 11月, 2020 3 次提交
- 01 11月, 2020 6 次提交
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
Log and waveform are controlled by cpu clock cycles instead of simulated cycles. When loading from snapshot and assert stops the simulation, we cannot know the accurate cpu cycle. To determine the actual cpu clock, we print cycleCnt when loading from snapshot.
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由 Yinan Xu 提交于
--threads 1 can delay assert to the end of each cycle and produce the entire log
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
have not connected the performance counters to CSR
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- 31 10月, 2020 1 次提交
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由 ljw 提交于
emu: asynchronous reset ram
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- 30 10月, 2020 1 次提交
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由 Yinan Xu 提交于
We need to asynchronous reset the system when reset is true. In verilator model, it's done by always resetting the external devices when reset is true. After the reset signal is released, we call init once for external devices to make sure they are correctly reset.
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- 29 10月, 2020 3 次提交
- 28 10月, 2020 7 次提交
- 27 10月, 2020 10 次提交
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由 Yinan Xu 提交于
MissQueue: for read hit, remember to set new_coh in decide_next_state
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由 Yinan Xu 提交于
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由 allen 提交于
L2 support outer probe
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 William Wang 提交于
optimize dispatch queue: support dequeue when store writes back
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由 Allen 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
Case: vvvdvvvddddd ^ ^ If the leftmost instruction is a store and it writebacks, these instructions won't be replayed. However, we cannot move headPtr to the left hand side of the dispatchPtr since there're still instructions that have not been dispatched to issue queues. In this case, we only remove the instructions before dispatchPtr. Moving headPtr in case of store writeback only affects performance, since instructions leave dispatch queue when they commit.
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- 26 10月, 2020 3 次提交
- 25 10月, 2020 5 次提交
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由 Yinan Xu 提交于
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由 William Wang 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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