add enable IO for prefetcher and move L2 prefetcher to SoC

bug dcache deadlock

perf: remove emu perf framework in CSR, use XSPerf instead

Opt timing at ftq commit & Ubtb merge data meta

L1d timing

csr: pass hartId by IO to dedup CSRs for different XSCores

RS: timing optimization for signal ctrl&data's in.valid and numExist

Refactor backend

    s2: select out the amo word
    s3: amo computation and meta/data/lr/sc update.

    timing worse.

path.