- 01 1月, 2022 1 次提交
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由 Luo Jia 提交于
XiangShan has registered an marchid of 25: https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md . This value should be returned from CSR `marchid`.
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- 30 12月, 2021 2 次提交
- 29 12月, 2021 5 次提交
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由 Jay 提交于
* Add Prefetch and Parity enable register for ICache * Add ICache parity enable control for pipe
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由 Jay 提交于
* IFU: fix mmio RVC bug * IFU: add resend address check for mmio When a mmio fetch an RVI instruction which cross 64 bits, IFU must send paddr + 2.U to fetch the higher 16 bits. But the paddr + 2.U is not checked by TLB or PMP. This may cause some unexpected fetch stuck problem.
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由 Lemover 提交于
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由 Yinan Xu 提交于
This commit adds blocking logic for instructions when they enter dispatch queues. If previous instructions have exceptions, any following instructions should be enter dispatch queue. Consider the following case. If uop(0) has an exception and is a load. If uop(1) does not have an exception and is a load as well. Then the allocation logic in dispatch queue will allocate an entry for both uop(0) and uop(1). However, uop(0) will not set enq.valid and leave the entry in dispatch queue empty. uop(1) will be allocated in dpq. In dispatch queue, pointers are updated according to the real number of instruction enqueue, which is one. While the second is actually allocated. This causes errors.
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由 wakafa 提交于
* bump huancun * Fix probe BtoB Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
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- 28 12月, 2021 1 次提交
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由 William Wang 提交于
* dcache: add source info in L1CacheErrorInfo * ICache: fix valid signal and add source/opType * dcache: fix bug in ecc error * mem,csr: send full L1CacheErrorInfo to CSR * icache: provide cache error info for CSR * dcache: force resp hit if tag ecc error happens * mem: reorg l1 cache error report path Now dcache tag error will force trigger a hit * dcache: fix readline ecc check error * dcache: mainpipe will not be influenced by tag error * dcache: fix data ecc check error * dcache: if coh state is Nothing, do not raise error Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn> Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>
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- 27 12月, 2021 3 次提交
- 26 12月, 2021 3 次提交
- 25 12月, 2021 1 次提交
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由 William Wang 提交于
If s2_data_invalid and s2_ldld_violation happens together, enter s2_ldld_violation workflow. Note: ld-ld violation or forward failure will let an normal load inst replay from fetch. If TLB hit and ld-ld violation / forward failure happens, we write back that inst immediately. Meanwhile, such insts will not be replayed from rs.
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- 24 12月, 2021 2 次提交
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由 Yinan Xu 提交于
Exception address is used serveral cycles after flush. We delay it by more cycles to ensure its flush safety.
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由 William Wang 提交于
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- 23 12月, 2021 1 次提交
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由 Jay 提交于
* IPrefetch: fix prefetchPtr stop problem * This problem happens because prefetchPtr still exits when close IPrefetch * Fix PMP req port still be occupied even when ICache miss * Shut down IPrefetch * IPrefetch: fix Hint not set PreferCache bit * bump HuanCun
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- 22 12月, 2021 2 次提交
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由 William Wang 提交于
* mem: optimize missq reject to lq timing DCache replay request is quite slow to generate, as it need to compare load address with address in all valid miss queue entries. Now we delay the usage of replay request from data cache. Now replay request will not influence normal execution flow until load_s3 (1 cycle after load_s2, load result writeback to RS). Note1: It is worth mentioning that "select refilling inst for load writeback" will be disabled if dcacheRequireReplay in the last cycle. Note2: ld-ld violation or forward failure will let an normal load inst replay from fetch. If TLB hit and ld-ld violation / forward failure happens, we write back that inst immediately. Meanwhile, such insts will not be replayed from rs. * dcache: compare probe block addr instead of full addr
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由 William Wang 提交于
* difftest: bump difftest to support --no-diff test * ci: add cacheoptest test (--no-diff)
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- 21 12月, 2021 7 次提交
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由 William Wang 提交于
* dcache: use sram to build ecc array * MainPipe: latch s1_encTag to last until s1_fire Authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
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由 Yinan Xu 提交于
This commit adds an LsqEnqCtrl module to add one more clock cycle between dispatch and load/store queue. LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter. They are used to determine whether load/store queue can accept new instructions. After that, instructions are sent to load/store queue. This module decouples queue allocation and real enqueue. Besides, uop storage in load/store queue are optimized. In dispatch, only robIdx is required. Other information is naturally conveyed in the pipeline and can be stored later in load/store queue if needed. For example, exception vector, trigger, ftqIdx, pdest, etc are unnecessary before the instruction leaves the load/store pipeline.
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由 William Wang 提交于
This commit removed PriorityEncoder in sbuffer enq path. It should improve sbuffer enqueue timing.
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由 Lemover 提交于
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由 wakafa 提交于
* pma: allow r/w priv for l3-cache op mmio space * bump huancun * bump huancun * bump huancun
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由 Jay 提交于
* Add Naive Instruction Prefetch * Add instruction prefetch module in ICache * send Hint to L2 (prefetched data stores in L2) * Ftq: add prefetchPtr and prefetch interface * Fix IPrefetch PMP Port preempting problem * Fix merge conflict
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由 Li Qianruo 提交于
Refactor Trigger
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- 20 12月, 2021 7 次提交
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由 Chuanqi Zhang 提交于
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由 Jay 提交于
* ICache: raise access fault when L2 send corrupt * ICache: add ECC error connection * chores: add comments and code clean-up * ICache: raise AF when Meta/Data Parity wrong * Update Frontend.scala
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由 Li Qianruo 提交于
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由 William Wang 提交于
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由 Li Qianruo 提交于
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由 William Wang 提交于
* dcache: let ecc error and l2 corrupt raise load af If CSR.smblockctl.cache_error_enable is disabled, ecc error and l2 corrupt will not raise any exception. * mem: enable cache error by default * mem: support store ecc check, add ecc error csr Support store / atom ecc check (early version) Add ecc error csr to distingush ecc error and other access fault Timing opt and unit tests to be added.
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由 Jay 提交于
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- 18 12月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 17 12月, 2021 3 次提交
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由 Lemover 提交于
* memblock: regnext ptw's resp * pmp: timing optimization from tlb.sram.ppn to pmp, add static pmp check long latency: tlb's sram may be slow to gen ppn, ppn to pmp may be long latency. Solution: add static pmp check. Fatal problem: pmp grain is smalled than TLB pages(4KB, 2MB, 1GB) Solution: increase pmp'grain to 4K, for 4K entries, pre-check pmp and store the result into tlb storage. For super pages, still dynamic check that translation and check. * pmp: change pmp grain to 4KB, change pma relative init config * bump ready-to-run, update nemu so for pmp grain * bump ready-to-run, update nemu so for pmp grain again update pmp unit test. The old test assumes that pmp grain is less than 512bit.
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由 Yinan Xu 提交于
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由 Jiawei Lin 提交于
* Change L3 to 6MB * Bump huancun
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- 16 12月, 2021 1 次提交
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由 Yinan Xu 提交于
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