IPrefetch: add prefetch address merge and counter (#1404)

* fix performance counter in ICacheMainpipe

* IPrefetch: add prefetch address merge and counter

src/main/scala/top/Configs.scala

@@ -94,7 +94,7 @@ class MinimalConfig(n: Int = 1) extends Config(
           nMissEntries = 2,
           nReleaseEntries = 2,
           nProbeEntries = 2,
-          nPrefetchEntries = 4,
+          nPrefetchEntries = 2,
           hasPrefetch = false
         ),
         dcacheParametersOpt = Some(DCacheParameters(

src/main/scala/xiangshan/Parameters.scala

@@ -217,8 +217,8 @@ case class XSCoreParameters
     nMissEntries = 2,
     nReleaseEntries = 2,
     nProbeEntries = 2,
-    nPrefetchEntries = 4,
-    hasPrefetch = false,
+    nPrefetchEntries = 2,
+    hasPrefetch = true,
   ),
   dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters(
     tagECC = Some("secded"),

src/main/scala/xiangshan/frontend/IFU.scala

@@ -695,6 +695,9 @@ class NewIFU(implicit p: Parameters) extends XSModule
   XSPerfAccumulate("hit_0_miss_1",    f3_perf_info.hit_0_miss_1  && io.toIbuffer.fire()  )
   XSPerfAccumulate("miss_0_hit_1",    f3_perf_info.miss_0_hit_1   && io.toIbuffer.fire() )
   XSPerfAccumulate("miss_0_miss_1",   f3_perf_info.miss_0_miss_1 && io.toIbuffer.fire() )
+  XSPerfAccumulate("hit_0_except_1",   f3_perf_info.hit_0_except_1 && io.toIbuffer.fire() )
+  XSPerfAccumulate("miss_0_except_1",   f3_perf_info.miss_0_except_1 && io.toIbuffer.fire() )
+  XSPerfAccumulate("except_0",   f3_perf_info.except_0 && io.toIbuffer.fire() )
   XSPerfAccumulate("cross_line_block", io.toIbuffer.fire() && f3_situation(0) )
   XSPerfAccumulate("fall_through_is_cacheline_end", io.toIbuffer.fire() && f3_situation(1) )
 }

src/main/scala/xiangshan/frontend/icache/ICache.scala

@@ -495,6 +495,10 @@ class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParame
   mainPipe.io.pmp(0).resp <> io.pmp(0).resp
   prefetchPipe.io.pmp.resp <> io.pmp(0).resp
 
+  prefetchPipe.io.prefetchEnable := mainPipe.io.prefetchEnable
+  prefetchPipe.io.prefetchDisable := mainPipe.io.prefetchDisable
+
+
   io.pmp(1) <> mainPipe.io.pmp(1)
 
   when(mainPipe.io.pmp(0).req.valid && prefetchPipe.io.pmp.req.valid)

src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala

@@ -76,6 +76,9 @@ class ICachePerfInfo(implicit p: Parameters) extends ICacheBundle{
   val hit_0_miss_1   = Bool()
   val miss_0_hit_1   = Bool()
   val miss_0_miss_1  = Bool()
+  val hit_0_except_1 = Bool()
+  val miss_0_except_1 = Bool()
+  val except_0       = Bool()
   val bank_hit       = Vec(2,Bool())
   val hit            = Bool()
 }
@@ -93,6 +96,8 @@ class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle {
   val respStall   = Input(Bool())
   val perfInfo = Output(new ICachePerfInfo)
 
+  val prefetchEnable = Output(Bool())
+  val prefetchDisable = Output(Bool())
   val csr_parity_enable = Input(Bool())
 
 }
@@ -113,8 +118,10 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
   val s0_ready, s1_ready, s2_ready = WireInit(false.B)
   val s0_fire,  s1_fire , s2_fire  = WireInit(false.B)
 
-  val missSwitchBit = RegInit(false.B)  
+  val missSwitchBit = RegInit(false.B)
 
+  io.prefetchEnable := false.B
+  io.prefetchDisable := false.B
   /** replacement status register */
   val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W))))
   val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) )
@@ -562,10 +569,13 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
 
   when(toMSHR.map(_.valid).reduce(_||_)){
     missSwitchBit := true.B
+    io.prefetchEnable := true.B
   }.elsewhen(missSwitchBit && s2_fetch_finish){
     missSwitchBit := false.B
+    io.prefetchDisable := true.B
   }
 
+
   val miss_all_fix       =  wait_state === wait_finish
   s2_fetch_finish        := ((s2_valid && s2_fixed_hit) || miss_all_fix || hit_0_except_1_latch || except_0_latch || s2_mmio)
   
@@ -610,15 +620,18 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
     }
   }
 
-  io.perfInfo.only_0_hit    := only_0_miss_latch
+  io.perfInfo.only_0_hit    := only_0_hit_latch
   io.perfInfo.only_0_miss   := only_0_miss_latch
   io.perfInfo.hit_0_hit_1   := hit_0_hit_1_latch
   io.perfInfo.hit_0_miss_1  := hit_0_miss_1_latch
   io.perfInfo.miss_0_hit_1  := miss_0_hit_1_latch
   io.perfInfo.miss_0_miss_1 := miss_0_miss_1_latch
+  io.perfInfo.hit_0_except_1 := hit_0_except_1_latch
+  io.perfInfo.miss_0_except_1 := miss_0_except_1_latch
+  io.perfInfo.except_0      := except_0_latch
   io.perfInfo.bank_hit(0)   := only_0_miss_latch  || hit_0_hit_1_latch || hit_0_miss_1_latch || hit_0_except_1_latch
   io.perfInfo.bank_hit(1)   := miss_0_hit_1_latch || hit_0_hit_1_latch 
-  io.perfInfo.hit           := hit_0_hit_1_latch
+  io.perfInfo.hit           := hit_0_hit_1_latch || only_0_hit_latch || hit_0_except_1_latch || except_0_latch
 
   /** <PERF> fetch bubble generated by icache miss*/
 

src/main/scala/xiangshan/frontend/icache/IPrefetch.scala

@@ -51,12 +51,34 @@ class IPredfetchIO(implicit p: Parameters) extends IPrefetchBundle {
   val toIMeta         = Decoupled(new ICacheReadBundle)
   val fromIMeta       = Input(new ICacheMetaRespBundle)
   val toMissUnit     = new IPrefetchToMissUnit
+
+  val prefetchEnable = Input(Bool())
+  val prefetchDisable = Input(Bool())
 }
 
 class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
 {
   val io = IO(new IPredfetchIO)
 
+  val enableBit = RegInit(false.B)
+  val maxPrefetchCoutner = RegInit(0.U(log2Ceil(nPrefetchEntries + 1).W))
+
+  val reachMaxSize = maxPrefetchCoutner === nPrefetchEntries.U
+
+  when(io.prefetchEnable){
+    enableBit := true.B
+  }.elsewhen((enableBit && io.prefetchDisable) || (enableBit && reachMaxSize)){
+    enableBit := false.B
+  }
+
+  class PrefetchDir(implicit  p: Parameters) extends IPrefetchBundle
+  {
+    val valid = Bool()
+    val paddr = UInt(PAddrBits.W)
+  }
+
+  val prefetch_dir = RegInit(VecInit(Seq.fill(nPrefetchEntries)(0.U.asTypeOf(new PrefetchDir))))
+
   val fromFtq = io.fromFtq
   val (toITLB,  fromITLB) = (io.iTLBInter.req, io.iTLBInter.resp)
   val (toIMeta, fromIMeta) = (io.toIMeta, io.fromIMeta.metaData(0))
@@ -70,7 +92,7 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
   /** Prefetch Stage 0: req from Ftq */
   val p0_valid  =   fromFtq.req.valid
   val p0_vaddr  =   addrAlign(fromFtq.req.bits.target, blockBytes, PAddrBits)
-  p0_fire   :=   p0_valid && p1_ready && toITLB.fire() && !fromITLB.bits.miss && toIMeta.ready
+  p0_fire   :=   p0_valid && p1_ready && toITLB.fire() && !fromITLB.bits.miss && toIMeta.ready && enableBit
 
   toIMeta.valid     := p0_valid
   toIMeta.bits.vSetIdx(0) := get_idx(p0_vaddr)
@@ -90,7 +112,7 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
 
   fromITLB.ready := true.B
 
-  fromFtq.req.ready :=  p1_ready && GTimer() > 500.U
+  fromFtq.req.ready :=  (!enableBit || (enableBit && p0_fire)) && GTimer() > 500.U
 
   /** Prefetch Stage 1: cache probe filter */
   val p1_valid =  generatePipeControl(lastFire = p0_fire, thisFire = p1_fire || p1_discard, thisFlush = false.B, lastFlush = false.B)
@@ -124,7 +146,7 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
   val p1_req_accept   = p1_valid && tlb_resp_valid && p1_miss
 
   p1_ready    :=   p1_fire || p1_req_cancle || !p1_valid
-  p1_fire     :=   p1_valid && p1_req_accept && p2_ready
+  p1_fire     :=   p1_valid && p1_req_accept && p2_ready && enableBit
   p1_discard  :=   p1_valid && p1_req_cancle
 
   /** Prefetch Stage 2: filtered req PIQ enqueue */
@@ -150,14 +172,29 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
   p2_discard := p2_valid && ((p2_exception && p2_pmp_fire) || !io.pmp.req.ready)
 
   /** Prefetch Stage 2: filtered req PIQ enqueue */
-  val p3_valid =  generatePipeControl(lastFire = p2_fire, thisFire = p3_fire, thisFlush = false.B, lastFlush = false.B)
+  val p3_valid =  generatePipeControl(lastFire = p2_fire, thisFire = p3_fire || p3_discard, thisFlush = false.B, lastFlush = false.B)
+
+  val p3_paddr = RegEnable(next = p2_paddr,  enable = p2_fire)
 
-  val p3_paddr = RegEnable(next = tlb_resp_paddr,  enable = p2_fire)
+  val p3_hit_dir = VecInit((0 until nPrefetchEntries).map(i => prefetch_dir(i).valid && prefetch_dir(i).paddr === p3_paddr )).reduce(_||_)
 
-  toMissUnit.enqReq.valid             := p3_valid
+  p3_discard := p3_hit_dir
+
+  toMissUnit.enqReq.valid             := p3_valid && enableBit && !p3_discard
   toMissUnit.enqReq.bits.paddr        := p3_paddr
 
-  p3_ready := toMissUnit.enqReq.ready
+  when(reachMaxSize){
+    maxPrefetchCoutner := 0.U
+
+    prefetch_dir.foreach(_.valid := false.B)
+  }.elsewhen(toMissUnit.enqReq.fire()){
+    maxPrefetchCoutner := maxPrefetchCoutner + 1.U
+
+    prefetch_dir(maxPrefetchCoutner).valid := true.B
+    prefetch_dir(maxPrefetchCoutner).paddr := p3_paddr
+  }
+
+  p3_ready := toMissUnit.enqReq.ready || !enableBit
   p3_fire  := toMissUnit.enqReq.fire()
 
 }
@@ -220,13 +257,6 @@ class IPrefetchEntry(edge: TLEdgeOut, id: Int)(implicit p: Parameters) extends I
   io.mem_hint.bits.user.lift(PreferCacheKey).foreach(_ := true.B)
 
 
-  XSPerfAccumulate(
-    "PrefetchEntryPenalty" + Integer.toString(id, 10),
-    BoolStopWatch(
-      start = io.req.fire(),
-      stop = io.mem_hint_ack.fire(),
-      startHighPriority = true)
-  )
   XSPerfAccumulate("PrefetchEntryReq" + Integer.toString(id, 10), io.req.fire())
 
 }
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