1. taken mask should consider corresponding valid bit
2. FetchWidth is in 4 bytes

1. previously we flush ftq status at stage2Redirect, but use
   stage3Redirect to flush ifu, when stage3Redirect comes with
   pdWb, ifuWbPtr would be falsely increased
2. toBpuUpdate.valid should only assign when do_commit

* Use FakeBPU can pass bubble-sort

* copy whole sram instead of dividing into banks.
* use RegEnable to hold meta_valid bit instead of RegNext

the state should be kept in IFU to control the f2_lastHalf register

* Invalid first instuction behind half-RVI

* Using separated selection instead of f2_hit Mux.

* reason: didn't flush wait_state when backend redirect

*ICache: The address is not aligned with the cache line
*IFU: fix instruciton valids width bug

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

* CSR: add csr access check for mstatus.tvm

tvm: trap virtual Memory.
when tvm is set, r/w the satp in S-mode will raise illegal-instr

* Fence: add tvm check that may disallow sfence

when tvm is set and at s-mode, sfence.vma will raise illegal-instr

* change the number of function units in MinimalConfig
* remove some hard-wired values

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

This commit adds an non-parameterized scheduler containing all reservation stations.
Now IntegerBlock, FloatBlock, MemBlock contain only function units.
The Schduler connects dispatch with all function units.
Parameterization to be added later.