difftest: Remove diff_rat and its related ports, when both env.EnableDifftest and env.AlwaysBasicDiff are false.

1. fix some bugs
2. add VfWbFuBusyTable
3. add WBPortConflictFlag

Backend: Add pipeline level between Scheduler and DataPath for MemScheduler and VfScheduler, and replace PipelineConnect with NewPipelineConnect.

1. The decoding information of the vset instruction is wrong.
2. Function "connectNonPipedCtrlSingal" should only be used in non-piped fu not in VSET.

Merge newest modification of master

Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* LoadQueueReplay: fix worst case, all oldest instructions are allocated to the same bank,
and the number of instructions is greater than the number of stages in load unit.
* Remove bank conflict block
* Increase priority for data replay

The deadlock scenario is as follows:

The LoadQueueReplay entry will not be released immediately after the instruction
is replayed from LoadQueueReplay. For example, after instruction a is replayed from
LoadQueueReplay, entry 1 is still valid. If instruction a still needs to be replayed,
Entry 1 will be updated again, otherwise entry 1 can be released.

If only the time of the first enqueue is used to select replay instructions (age matrix),
when there are too many instructions (in LoadQueueReplay) to be replay, some
instructions may not be selected.

Using the pointer ldWbPtr of the oldest instruction, when the saved lqIdx of the
instruction is equal to ldWbPtr and can be replayed, LoadQueueReplay will give
priority to the instruction instead of using the selection result of the age matrix.
To select older instructions, LoadQueueReplay will calculate pointers such as
ldWbPtr, ldWbPtr+1, ldWbPtr+2, ldWbPtr+3..., and if the lqIdx of the instruction
is in these results, it will be selected first.

When the pointer is compared, there will be an n-bit long mask, and LoadQueueReplay
will be from 0 to n-1. When i th bit is valid, select i th instruction.

The stride of the pointer comparison is larger than the number of pipeline stages
of the load unit, and the selected instruction still needs to be replayed after the
first replay (for example, the data is not ready). Worse, in the bit of the mask
generated by pointer comparison, the instructions (lqIdx is ldWbPtr+1, ldWbPtr+2, ...)
after the oldest instruction (lqIdx is equal to ldWbPtr) are in the lower bit and the
oldest instruction is in the higher bit. It cannot select the oldest instruction.

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitStrict when compare SSID

* fix store data wakeup logic
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* The input of VIMac data module should be exchanged when opcode is vmadd or vnmsub, since source data are not exchanged in data module.

* Vector source data should be localed at high bits of vimacs.vs1|2, when widen=1 and vuopIdx is a odd number
* The odd uop of widen insts should use high part of vs1 and vs2.
* The eew of widen insts should be double of sew.

* Width of vlMapVdIdx should be 4-bit, because vl can equal to VLEN. In this case, vlMapVdIdx is 8.