WbFuBusyTable: refactor WbFubusyTable

1. fix some bugs
2. add VfWbFuBusyTable
3. add WBPortConflictFlag

src/main/scala/xiangshan/backend/Backend.scala

@@ -6,7 +6,7 @@ import chisel3.util._
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utility.{PipelineConnect, ZeroExt}
 import xiangshan._
-import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput, FuBusyTableWriteBundle}
+import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput}
 import xiangshan.backend.ctrlblock.CtrlBlock
 import xiangshan.backend.datapath.WbConfig._
 import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath}
@@ -66,33 +66,45 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
   private val vfExuBlock = wrapper.vfExuBlock.get.module
   private val wbDataPath = Module(new WbDataPath(params))
 
-  private val (intRespWrite, vfRespWrite, memRespWrite) = (intScheduler.io.wbFuBusyTable.fuBusyTableWrite,
-    vfScheduler.io.wbFuBusyTable.fuBusyTableWrite,
-    memScheduler.io.wbFuBusyTable.fuBusyTableWrite)
-  private val (intRespRead, vfRespRead, memRespRead) = (intScheduler.io.wbFuBusyTable.fuBusyTableRead,
-    vfScheduler.io.wbFuBusyTable.fuBusyTableRead,
-    memScheduler.io.wbFuBusyTable.fuBusyTableRead)
-  private val allRespWrite = (intRespWrite ++ vfRespWrite ++ memRespWrite).flatten
-  private val allRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten
+  private val (intRespWrite, vfRespWrite, memRespWrite) = (intScheduler.io.toWbFuBusyTable.intFuBusyTableWrite,
+    vfScheduler.io.toWbFuBusyTable.intFuBusyTableWrite,
+    memScheduler.io.toWbFuBusyTable.intFuBusyTableWrite)
+  private val (intRespRead, vfRespRead, memRespRead) = (intScheduler.io.fromWbFuBusyTable.fuBusyTableRead,
+    vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead,
+    memScheduler.io.fromWbFuBusyTable.fuBusyTableRead)
+  private val intAllRespWrite = (intRespWrite ++ vfRespWrite ++ memRespWrite).flatten
+  private val intAllRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten.map(_.intWbBusyTable)
+  private val intAllWbConflictFlag = dataPath.io.wbConfictRead.flatten.flatten.map(_.intConflict)
+
+  private val (vfIntRespWrite, vfVfRespWrite, vfMemRespWrite) = (intScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite,
+    vfScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite,
+    memScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite)
+
+  private val vfAllRespWrite = (vfIntRespWrite ++ vfVfRespWrite ++ vfMemRespWrite).flatten
+  private val vfAllRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten.map(_.vfWbBusyTable)
+  private val vfAllWbConflictFlag = dataPath.io.wbConfictRead.flatten.flatten.map(_.vfConflict)
+
   wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf)
   private val allExuParams = params.allExuParams
-  private val respWriteWithParams = allRespWrite.zip(allExuParams)
-  println(s"[respWriteWithParams] is ${respWriteWithParams}")
-  respWriteWithParams.foreach{ case(l,r) =>
+  private val intRespWriteWithParams = intAllRespWrite.zip(allExuParams)
+  println(s"[intRespWriteWithParams] is ${intRespWriteWithParams}")
+  intRespWriteWithParams.foreach{ case(l,r) =>
     println(s"FuBusyTableWriteBundle is ${l}, ExeUnitParams is ${r}")
   }
-//  require(false)
+  private val vfRespWriteWithParams = vfAllRespWrite.zip(allExuParams)
 
-  private val intWBFuGroup = params.getIntWBExeGroup.map{case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs))}
-  private val intLatencyCertains = intWBFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))}
+  private val intWBAllFuGroup = params.getIntWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs)) }
+  private val intWBFuGroup = params.getIntWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs).filter(_.writeIntRf)) }
+  private val intLatencyCertains = intWBAllFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))}
   private val intWBFuLatencyMap = intLatencyCertains.map{case (k, latencyCertain) =>
     if (latencyCertain) Some(intWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get)))
     else None
   }.toSeq
   private val intWBFuLatencyValMax = intWBFuLatencyMap.map(latencyMap=> latencyMap.map(x => x.map(_._2).max))
 
-  private val vfWBFuGroup = params.getVfWBExeGroup.map{case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs))}
-  private val vfLatencyCertains = vfWBFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))}
+  private val vfWBAllFuGroup = params.getVfWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs)) }
+  private val vfWBFuGroup = params.getVfWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs).filter(x => x.writeFpRf || x.writeVecRf)) }
+  private val vfLatencyCertains = vfWBAllFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))}
   val vfWBFuLatencyMap = vfLatencyCertains.map { case (k, latencyCertain) =>
     if (latencyCertain) Some(vfWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get)))
     else None
@@ -102,87 +114,180 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
   private val intWBFuBusyTable = intWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None }
   println(s"[intWBFuBusyTable] is ${intWBFuBusyTable.map(x => x) }")
   private val vfWBFuBusyTable = vfWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None }
+  println(s"[vfWBFuBusyTable] is ${vfWBFuBusyTable.map(x => x) }")
+
+  private val intWBPortConflictFlag = intWBFuLatencyValMax.map { case y => if (y.getOrElse(0) > 0) Some(Reg(Bool())) else None }
+  private val vfWBPortConflictFlag = vfWBFuLatencyValMax.map { case y => if (y.getOrElse(0) > 0) Some(Reg(Bool())) else None }
+
+  intWBPortConflictFlag.foreach(x => if(x.isDefined) dontTouch((x.get)))
+  vfWBPortConflictFlag.foreach(x => if(x.isDefined) dontTouch((x.get)))
+
 
   intWBFuBusyTable.map(x => x.map(dontTouch(_)))
-  dontTouch(intScheduler.io.wbFuBusyTable)
-  dontTouch(vfScheduler.io.wbFuBusyTable)
-  dontTouch(memScheduler.io.wbFuBusyTable)
+  vfWBFuBusyTable.map(x => x.map(dontTouch(_)))
 
+
+  private val intWBFuBusyTableWithPort = intWBFuBusyTable.zip(intWBFuGroup.map(_._1))
+  private val intWBPortConflictFlagWithPort = intWBPortConflictFlag.zip(intWBFuGroup.map(_._1))
   // intWBFuBusyTable write
-  for (i <- 0 until intWBFuGroup.size) {
-    if (intWBFuBusyTable(i).nonEmpty){
-      val deqIsLatencyNumMask = respWriteWithParams.zipWithIndex.map{ case((r, p), idx) =>
-        val resps = p.schdType match {
-          case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp)
-          case MemScheduler() => Seq(r.deqResp, r.og1Resp)
-          case VfScheduler() => Seq(r.deqResp, r.og1Resp)
-          case _ => null
-        }
-        val matchI = (p.wbPortConfigs.collectFirst{ case x: IntWB => x }.getOrElse(-1)) == i
-        if(matchI){
-          Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess,
-            Cat((0 until intWBFuLatencyValMax(i).getOrElse(0)).map { case num =>
-            val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num+1).map(_.fuType)
-            val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num
+  intWBFuBusyTableWithPort.zip(intWBPortConflictFlag).zip(intWBFuLatencyValMax).foreach {
+    case (((busyTable, wbPort), wbPortConflictFlag), maxLatency) =>
+      if (busyTable.nonEmpty) {
+      val maskWidth = maxLatency.getOrElse(0)
+      val defaultMask = ((1 << maskWidth) - 1).U
+      val deqWbFuBusyTableValue = intRespWriteWithParams.zipWithIndex.filter { case ((r, p), idx) =>
+        (p.wbPortConfigs.collectFirst{ case x: IntWB => x.port }.getOrElse(-1)) == wbPort
+      }.map{case ((r, p), idx) =>
+        val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp)
+        Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess,
+          VecInit((0 until maxLatency.getOrElse(0) + 1).map { case latency =>
+          val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == latency).map(_.fuType)
+          val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num
             isLatencyNum
-            }),
-            0.U)
-        } else 0.U
-      }.reduce(_|_)
-      val og0IsLatencyNumMask = WireInit(-1.S.asTypeOf(deqIsLatencyNumMask))
-      og0IsLatencyNumMask := respWriteWithParams.zipWithIndex.map { case ((r, p), idx) =>
-        val resps = p.schdType match {
-          case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp)
-          case MemScheduler() => Seq(r.deqResp, r.og1Resp)
-          case VfScheduler() => Seq(r.deqResp, r.og1Resp)
-          case _ => null
-        }
-        val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == i
+          }).asUInt,
+          0.U)
+      }
+//        deqWbFuBusyTableValue.foreach(x => dontTouch(x))
+      val deqIsLatencyNumMask = (deqWbFuBusyTableValue.reduce(_ | _) >> 1).asUInt
+      wbPortConflictFlag.get := deqWbFuBusyTableValue.reduce(_ & _).orR
+
+      val og0IsLatencyNumMask = WireInit(defaultMask)
+      og0IsLatencyNumMask := intRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) =>
+        val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp)
+        val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort
         if (matchI) {
-          Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.issueSuccess,
-            ~(Cat(Cat((0 until intWBFuLatencyValMax(i).getOrElse(0)).map { case num =>
-              val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType)
+          Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.rfArbitFail,
+            (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num =>
+              val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType)
               val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(1).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num
               isLatencyNum
-            }), 0.U(1.W))),
-            -1.S.asTypeOf(deqIsLatencyNumMask)).asTypeOf(deqIsLatencyNumMask)
-        } else -1.S.asTypeOf(deqIsLatencyNumMask)
+            }).asUInt, 0.U(1.W)))).asUInt,
+            defaultMask)
+        } else defaultMask
       }.reduce(_&_)
-      val og1IsLatencyNumMask = WireInit(-1.S.asTypeOf(deqIsLatencyNumMask))
-      og1IsLatencyNumMask := respWriteWithParams.zipWithIndex.map { case ((r, p), idx) =>
-        val resps = p.schdType match {
-          case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp)
-          case MemScheduler() => Seq(r.deqResp, r.og1Resp)
-          case VfScheduler() => Seq(r.deqResp, r.og1Resp)
-          case _ => null
-        }
-        val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == i
+      val og1IsLatencyNumMask = WireInit(defaultMask)
+      og1IsLatencyNumMask := intRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) =>
+        val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp)
+        val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort
         if (matchI && resps.length==3) {
-          Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.issueSuccess,
-            ~(Cat(Cat((0 until intWBFuLatencyValMax(i).getOrElse(0)).map { case num =>
-              val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType)
+          Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.fuBusy,
+            (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num =>
+              val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType)
               val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(2).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num
               isLatencyNum
-            }), 0.U(1.W))),
-            -1.S.asTypeOf(deqIsLatencyNumMask)).asTypeOf(deqIsLatencyNumMask)
-        } else -1.S.asTypeOf(deqIsLatencyNumMask)
+            }).asUInt, 0.U(2.W)))).asUInt,
+            defaultMask)
+        } else defaultMask
       }.reduce(_ & _)
       dontTouch(deqIsLatencyNumMask)
       dontTouch(og0IsLatencyNumMask)
       dontTouch(og1IsLatencyNumMask)
-      intWBFuBusyTable(i).get := ((intWBFuBusyTable(i).get << 1.U).asUInt() | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt() & og1IsLatencyNumMask.asUInt()
+      busyTable.get := ((busyTable.get >> 1.U).asUInt() | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt() & og1IsLatencyNumMask.asUInt()
     }
   }
   // intWBFuBusyTable read
-  for(i <- 0 until allRespRead.size){
-    allRespRead(i) := intWBFuBusyTable.zipWithIndex.map{ case (ele, idx) =>
-      val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == idx
-      if(ele.nonEmpty && matchI){
-        ele.get.asTypeOf(allRespRead(i))
-      }else{
-        0.U.asTypeOf(allRespRead(i))
+  for(i <- 0 until intAllRespRead.size){
+    if(intAllRespRead(i).isDefined){
+      intAllRespRead(i).get := intWBFuBusyTableWithPort.map { case (busyTable, wbPort) =>
+        val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort
+        if (busyTable.nonEmpty && matchI) {
+          busyTable.get.asTypeOf(intAllRespRead(i).get)
+        } else {
+          0.U.asTypeOf(intAllRespRead(i).get)
+        }
+      }.reduce(_ | _)
+    }
+
+    if (intAllWbConflictFlag(i).isDefined) {
+      intAllWbConflictFlag(i).get := intWBPortConflictFlagWithPort.map { case (conflictFlag, wbPort) =>
+        val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort
+        if (conflictFlag.nonEmpty && matchI) {
+          conflictFlag.get
+        } else false.B
+      }.reduce(_ | _)
+    }
+  }
+
+  private val vfWBFuBusyTableWithPort = vfWBFuBusyTable.zip(vfWBFuGroup.map(_._1))
+  private val vfWBPortConflictFlagWithPort = vfWBPortConflictFlag.zip(vfWBFuGroup.map(_._1))
+  // vfWBFuBusyTable write
+  vfWBFuBusyTableWithPort.zip(vfWBPortConflictFlag).zip(vfWBFuLatencyValMax).foreach{
+    case(((busyTable, wbPort), wbPortConflictFlag), maxLatency) =>
+      if(busyTable.nonEmpty){
+        val maskWidth = maxLatency.getOrElse(0)
+        val defaultMask = ((1 << maskWidth) - 1).U
+        val deqWbFuBusyTableValue = vfRespWriteWithParams.zipWithIndex.filter { case ((_, p), _) =>
+          (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort
+        }.map { case ((r, p), _) =>
+          val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp)
+          Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess,
+            VecInit((0 until maxLatency.getOrElse(0) + 1).map { case latency =>
+              val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == latency).map(_.fuType)
+              val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num
+              isLatencyNum
+            }).asUInt,
+            0.U)
+        }
+        val deqIsLatencyNumMask = (deqWbFuBusyTableValue.reduce(_ | _) >> 1).asUInt
+        wbPortConflictFlag.get := deqWbFuBusyTableValue.reduce(_ & _).orR
+
+        val og0IsLatencyNumMask = WireInit(defaultMask)
+        og0IsLatencyNumMask := vfRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) =>
+          val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp)
+          val matchI = (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort
+          if (matchI) {
+            Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.rfArbitFail,
+              (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num =>
+                val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType)
+                val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(1).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num
+                isLatencyNum
+              }).asUInt, 0.U(1.W)))).asUInt,
+              defaultMask)
+          } else defaultMask
+        }.reduce(_ & _)
+        val og1IsLatencyNumMask = WireInit(defaultMask)
+        og1IsLatencyNumMask := vfRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) =>
+          val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp)
+
+          val matchI = (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort
+          if (matchI && resps.length == 3) {
+            Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.fuBusy,
+              (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num =>
+                val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType)
+                val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(2).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num
+                isLatencyNum
+              }).asUInt, 0.U(2.W)))).asUInt,
+              defaultMask)
+          } else defaultMask
+        }.reduce(_ & _)
+        dontTouch(deqIsLatencyNumMask)
+        dontTouch(og0IsLatencyNumMask)
+        dontTouch(og1IsLatencyNumMask)
+        busyTable.get := ((busyTable.get >> 1.U).asUInt | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt & og1IsLatencyNumMask.asUInt
       }
-    }.reduce(_|_)
+  }
+
+  // vfWBFuBusyTable read
+  for (i <- 0 until vfAllRespRead.size) {
+    if(vfAllRespRead(i).isDefined){
+      vfAllRespRead(i).get := vfWBFuBusyTableWithPort.map { case (busyTable, wbPort) =>
+        val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort
+        if (busyTable.nonEmpty && matchI) {
+          busyTable.get.asTypeOf(vfAllRespRead(i).get)
+        } else {
+          0.U.asTypeOf(vfAllRespRead(i).get)
+        }
+      }.reduce(_ | _)
+    }
+
+    if(vfAllWbConflictFlag(i).isDefined){
+      vfAllWbConflictFlag(i).get := vfWBPortConflictFlagWithPort.map { case (conflictFlag, wbPort) =>
+        val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort
+        if (conflictFlag.nonEmpty && matchI) {
+          conflictFlag.get
+        } else false.B
+      }.reduce(_ | _)
+    }
   }
 
   ctrlBlock.io.fromTop.hartId := io.fromTop.hartId

src/main/scala/xiangshan/backend/Bundles.scala

@@ -328,12 +328,34 @@ object Bundles {
     val fuType = FuType()
   }
 
-  class FuBusyTableWriteBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
+  class WbFuBusyTableWriteBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
     val deqResp = Valid(new fuBusyRespBundle)
     val og0Resp = Valid(new fuBusyRespBundle)
     val og1Resp = Valid(new fuBusyRespBundle)
   }
 
+  class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle {
+    val intWbBusyTable = params.intLatencyValMax match {
+      case Some(latency) => Some(UInt((latency + 1).W))
+      case None => None
+    }
+    val vfWbBusyTable = params.vfLatencyValMax match {
+      case Some(latency) => Some(UInt((latency + 1).W))
+      case None => None
+    }
+  }
+
+  class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle {
+    val intConflict = params.intLatencyValMax match {
+      case Some(latency) => Some(Bool())
+      case None => None
+    }
+    val vfConflict = params.vfLatencyValMax match {
+      case Some(latency) => Some(Bool())
+      case None => None
+    }
+  }
+
   // DataPath --[ExuInput]--> Exu
   class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle {
     val fuType        = FuType()

src/main/scala/xiangshan/backend/datapath/DataPath.scala

@@ -170,6 +170,8 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
   private val intBlocksSeq = intBlocks.flatten
   private val vfBlocks = fromIQ.map { case iq => Wire(Vec(iq.size, Bool())) }
   private val vfBlocksSeq = vfBlocks.flatten
+  private val intWbConflictReads = io.wbConfictRead.flatten.flatten.map(_.intConflict)
+  private val vfWbConflictReads = io.wbConfictRead.flatten.flatten.map(_.vfConflict)
 
   val intWbBusyInSize = issuePortsIn.map(issuePortIn => issuePortIn.bits.getIntWbBusyBundle.size).scan(0)(_ + _)
   val intReadPortInSize: IndexedSeq[Int] = issuePortsIn.map(issuePortIn => issuePortIn.bits.getIntRfReadBundle.size).scan(0)(_ + _)
@@ -184,14 +186,15 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
           sink.bits := DontCare
           sink.valid := issuePortIn.valid && source
       }
-      if (rw > lw) {
-        intNotBlocksSeqW(idx) := arbiterInW.zip(wbBusyIn).map {
+       val notBlockFlag = if (rw > lw) {
+        val arbiterRes = arbiterInW.zip(wbBusyIn).map {
           case (sink, source) => sink.ready
         }.reduce(_ & _)
-      }
-      else {
-        intNotBlocksSeqW(idx) := true.B
-      }
+        if (intWbConflictReads(idx).isDefined) {
+          Mux(intWbConflictReads(idx).get, arbiterRes, true.B)
+        } else arbiterRes
+      } else true.B
+      intNotBlocksSeqW(idx) := notBlockFlag
       val readPortIn = issuePortIn.bits.getIntRfReadBundle
       val l = intReadPortInSize(idx)
       val r = intReadPortInSize(idx + 1)
@@ -199,7 +202,7 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
       arbiterIn.zip(readPortIn).foreach{
         case(sink, source) =>
           sink.bits.addr := source.addr
-          sink.valid := issuePortIn.valid && SrcType.isXp(source.srcType) && intNotBlocksSeqW(idx)
+          sink.valid := issuePortIn.valid && SrcType.isXp(source.srcType)
       }
       if(r > l){
         intBlocksSeq(idx) := !arbiterIn.zip(readPortIn).map {
@@ -228,14 +231,16 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
           sink.bits := DontCare
           sink.valid := issuePortIn.valid && source
       }
-      if (rw > lw) {
-        vfNotBlocksSeqW(idx) := arbiterInW.zip(wbBusyIn).map {
+      val notBlockFlag = if (rw > lw){
+        val arbiterRes = arbiterInW.zip(wbBusyIn).map {
           case (sink, source) => sink.ready
         }.reduce(_ & _)
-      }
-      else {
-        vfNotBlocksSeqW(idx) := true.B
-      }
+        if(vfWbConflictReads(idx).isDefined) {
+          Mux(vfWbConflictReads(idx).get, arbiterRes, true.B)
+        }else arbiterRes
+      }else true.B
+      vfNotBlocksSeqW(idx) := notBlockFlag
+
       val readPortIn = issuePortIn.bits.getVfRfReadBundle
       val l = vfReadPortInSize(idx)
       val r = vfReadPortInSize(idx + 1)
@@ -243,7 +248,7 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
       arbiterIn.zip(readPortIn).foreach {
         case (sink, source) =>
           sink.bits.addr := source.addr
-          sink.valid := issuePortIn.valid && SrcType.isVfp(source.srcType) && vfNotBlocksSeqW(idx)
+          sink.valid := issuePortIn.valid && SrcType.isVfp(source.srcType)
       }
       if (r > l) {
         vfBlocksSeq(idx) := !arbiterIn.zip(readPortIn).map {
@@ -412,7 +417,7 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
       }.otherwise {
         s1_valid := false.B
       }
-
+      dontTouch(block)
       s0.ready := (s1_ready || !s1_valid) && !block
       // IQ(s0) --[Ctrl]--> s1Reg ---------- end
 
@@ -554,6 +559,8 @@ class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBund
   // Todo: check if this can be removed
   val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth)
 
+  val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle())))))
+
   val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] =
     Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle)))
 

src/main/scala/xiangshan/backend/datapath/RdConfig.scala

@@ -6,8 +6,8 @@ object RdConfig {
     val priority: Int
   }
 
-  case class IntRD(port: Int, priority: Int) extends RdConfig()
+  case class IntRD(port: Int = -1, priority: Int = Int.MaxValue) extends RdConfig()
 
-  case class VfRD(port: Int, priority: Int) extends RdConfig()
+  case class VfRD(port: Int = -1, priority: Int = Int.MaxValue) extends RdConfig()
 }
 

src/main/scala/xiangshan/backend/datapath/WbConfig.scala

@@ -39,6 +39,15 @@ object WbConfig {
     override def numPreg: Int = 160
   }
 
+  case class VecWB(
+    port: Int = -1,
+    priority: Int = Int.MaxValue,
+  ) extends PregWB {
+    def dataCfg: DataConfig = VecData()
+
+    override def numPreg: Int = 160
+  }
+
   case class CtrlWB(
     port: Int = -1,
   ) extends WbConfig {

src/main/scala/xiangshan/backend/exu/ExeUnit.scala

@@ -8,7 +8,7 @@ import utility.DelayN
 import utils._
 import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput}
 import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput}
-import xiangshan.{Redirect, XSBundle, XSModule}
+import xiangshan.{HasXSParameter, Redirect, XSBundle, XSModule}
 
 class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle {
   val flush = Flipped(ValidIO(new Redirect()))
@@ -27,7 +27,7 @@ class ExeUnitImp(
   override val wrapper: ExeUnit
 )(implicit
   p: Parameters, exuParams: ExeUnitParams
-) extends LazyModuleImp(wrapper) {
+) extends LazyModuleImp(wrapper) with HasXSParameter{
   private val fuCfgs = exuParams.fuConfigs
 
   val io = IO(new ExeUnitIO(exuParams))
@@ -49,10 +49,26 @@ class ExeUnitImp(
   }.elsewhen(io.in.fire) {
     busy := true.B
   }
-  if(exuParams.latencyValMax.nonEmpty){
+  val intWbPort = exuParams.getIntWBPort
+  val intFlag = if(intWbPort.isDefined) backendParams.allExuParams.map(exuParam => (exuParam.getIntWBPort, exuParam.latencyCertain))
+    .filter(_._1.isDefined)
+    .filter(_._1.get.port == intWbPort.get.port)
+    .map(_._2)
+    .reduce(_ | _)
+  else true
+
+  val vfWbPort = exuParams.getVfWBPort
+  val vfFlag = if (vfWbPort.isDefined) backendParams.allExuParams.map(exuParam => (exuParam.getVfWBPort, exuParam.latencyCertain))
+    .filter(_._1.isDefined)
+    .filter(_._1.get.port == vfWbPort.get.port)
+    .map(_._2)
+    .reduce(_ | _)
+  else true
+
+  if(intFlag && vfFlag){
     busy := false.B
   }
-
+  dontTouch(io.out.ready)
   // rob flush --> funcUnits
   funcUnits.zipWithIndex.foreach { case (fu, i) =>
     fu.io.flush <> io.flush
@@ -65,9 +81,9 @@ class ExeUnitImp(
   val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond))
 
   // ExeUnit.in <---> Dispatcher.in
-  in1ToN.io.in.valid := io.in.fire()
+  in1ToN.io.in.valid := io.in.valid && !busy
   in1ToN.io.in.bits := io.in.bits
-  io.in.ready := !busy
+  io.in.ready := !busy && in1ToN.io.in.ready
 
   // Dispatcher.out <---> FunctionUnits
   in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach {
@@ -153,7 +169,7 @@ class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Boo
   XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu")
 
   io.out.zipWithIndex.foreach { case (out, i) =>
-    out.valid := acceptVec(i) && io.in.valid && out.ready
+    out.valid := acceptVec(i) && io.in.valid
     out.bits := io.in.bits
   }
 

src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala

@@ -3,10 +3,11 @@ package xiangshan.backend.exu
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
+import xiangshan.HasXSParameter
 import xiangshan.backend.Bundles.{ExuInput, ExuOutput}
 import xiangshan.backend.datapath.DataConfig.DataConfig
 import xiangshan.backend.datapath.RdConfig._
-import xiangshan.backend.datapath.WbConfig.{VfWB, IntWB, WbConfig}
+import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB, WbConfig}
 import xiangshan.backend.fu.{FuConfig, FuType}
 import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler}
 
@@ -49,9 +50,21 @@ case class ExeUnitParams(
   val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _)
   val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0
 
-  protected val latencyCertain = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_&&_)
-  val fuLatencyMap = if (latencyCertain) Some(fuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None
-  val latencyValMax = fuLatencyMap.map(x => x.map(_._2).max)
+  val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf)
+  val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf)
+
+  val latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_&&_)
+  val intLatencyCertain = if (writeIntFuConfigs.nonEmpty) writeIntFuConfigs.map(x => x.latency.latencyVal.nonEmpty).fold(true)(_ && _) else false
+  val vfLatencyCertain = if (writeVfFuConfigs.nonEmpty) writeVfFuConfigs.map(x => x.latency.latencyVal.nonEmpty).fold(true)(_ && _) else false
+
+  val fuLatencyMap: Option[Seq[(Int, Int)]] = if (latencyCertain) Some(fuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None
+  val latencyValMax: Option[Int] = fuLatencyMap.map(x => x.map(_._2).max)
+
+  val intFuLatencyMap = if (intLatencyCertain) Some(writeIntFuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None
+  val intLatencyValMax = intFuLatencyMap.map(x => x.map(_._2).max)
+
+  val vfFuLatencyMap = if (vfLatencyCertain) Some(writeVfFuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None
+  val vfLatencyValMax = vfFuLatencyMap.map(x => x.map(_._2).max)
 
   def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _)
 

src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.issue
 import chipsalliance.rocketchip.config.Parameters
 import chisel3.util._
 import chisel3._
-import xiangshan.backend.Bundles.{ExuInput, ExuOutput, IssueQueueIssueBundle, OGRespBundle, FuBusyTableWriteBundle}
+import xiangshan.backend.Bundles.{ExuInput, ExuOutput, IssueQueueIssueBundle, OGRespBundle, WbConflictBundle, WbFuBusyTableReadBundle, WbFuBusyTableWriteBundle}
 import xiangshan.backend.datapath.WbConfig.WbConfig
 import xiangshan.backend.exu.ExeUnitParams
 import xiangshan.backend.fu.{FuConfig, FuType}
@@ -177,14 +177,23 @@ case class IssueBlockParams(
     MixedVec(exuBlockParams.map(_ => new OGRespBundle))
   }
 
-  def genFuBusyTableWriteBundle(implicit p: Parameters) = {
+  def genWbFuBusyTableWriteBundle(implicit p: Parameters) = {
     implicit val issueBlockParams = this
-    MixedVec(exuBlockParams.map(_ => new FuBusyTableWriteBundle))
+    MixedVec(exuBlockParams.map(_ => new WbFuBusyTableWriteBundle()))
   }
 
-  def genFuBusyTableReadBundle(implicit p: Parameters) = {
+  def genWbFuBusyTableReadBundle()(implicit p: Parameters) = {
     implicit val issueBlockParams = this
-    MixedVec(exuBlockParams.map(x => UInt(x.latencyValMax.getOrElse(0).W)))
+    MixedVec(exuBlockParams.map{ x =>
+      new WbFuBusyTableReadBundle(x)
+    })
+  }
+
+  def genWbConflictBundle()(implicit p: Parameters) = {
+    implicit val issueBlockParams = this
+    MixedVec(exuBlockParams.map { x =>
+      new WbConflictBundle(x)
+    })
   }
 
   def getIQName = {

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -40,7 +40,7 @@ class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends X
   val deqResp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
   val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
   val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
-  val wbBusyRead = Input(params.genFuBusyTableReadBundle)
+  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
   val wakeup = Vec(params.numWakeupFromWB, Flipped(ValidIO(new IssueQueueWakeUpBundle(params.pregBits))))
   val status = Output(new IssueQueueStatusBundle(params.numEnq))
   val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
@@ -57,6 +57,8 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
   require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
   val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
   val fuLatencyMaps :  Seq[Option[Seq[(Int, Int)]]]  = params.exuBlockParams.map(x => x.fuLatencyMap)
+  val intFuLatencyMaps: Seq[Option[Seq[(Int, Int)]]]  = params.exuBlockParams.map(x => x.intFuLatencyMap)
+  val vfFuLatencyMaps : Seq[Option[Seq[(Int, Int)]]]  = params.exuBlockParams.map(x => x.vfFuLatencyMap)
   val latencyValMaxs: Seq[Option[Int]] = params.exuBlockParams.map(x => x.latencyValMax)
   val allDeqFuCfgs: Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
   val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
@@ -74,13 +76,12 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
   val fuBusyTable = latencyValMaxs.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None }
 
   // Wires
-  val resps = params.schdType match {
-    case IntScheduler() => Seq(io.deqResp, io.og0Resp, io.og1Resp)
-    case MemScheduler() => Seq(io.deqResp, io.og1Resp)
-    case VfScheduler() => Seq(io.deqResp, io.og1Resp)
-    case _ => null
-  }
+  val resps = Seq(io.deqResp, io.og0Resp, io.og1Resp)
+
+  val intWbBusyTableRead = io.wbBusyTableRead.map(_.intWbBusyTable)
+  val vfWbBusyTableRead = io.wbBusyTableRead.map(_.vfWbBusyTable)
   val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
+  val wbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
   val s0_enqValidVec = io.enq.map(_.valid)
   val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
   val s0_enqSelOHVec = Wire(Vec(params.numEnq, UInt(params.numEntries.W)))
@@ -230,7 +231,7 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
   subDeqPolicies.zipWithIndex.map { case (dpOption: Option[DeqPolicy], i) =>
     if (dpOption.nonEmpty) {
       val dp = dpOption.get
-      dp.io.request             := canIssueVec.asUInt & VecInit(deqCanAcceptVec(i)).asUInt & (~fuBusyTableMask(i)).asUInt()
+      dp.io.request             := canIssueVec.asUInt & VecInit(deqCanAcceptVec(i)).asUInt & (~fuBusyTableMask(i)).asUInt & (~wbBusyTableMask(i)).asUInt
       subDeqSelValidVec(i).get  := dp.io.deqSelOHVec.map(oh => oh.valid)
       subDeqSelOHVec(i).get     := dp.io.deqSelOHVec.map(oh => oh.bits)
     }
@@ -260,7 +261,7 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
         0.U
       ) // |  when N cycle is 2 latency, N+1 cycle could not 1 latency
       val isLNumVecOg0 = WireInit(~(0.U.asTypeOf(isLatencyNumVec)))
-      isLNumVecOg0 := Mux(resps(1)(i).valid && (resps(1)(i).bits.respType === RSFeedbackType.rfArbitFail || resps(1)(i).bits.respType === RSFeedbackType.fuBusy),
+      isLNumVecOg0 := Mux(resps(1)(i).valid && resps(1)(i).bits.respType === RSFeedbackType.rfArbitFail,
         ~(Cat(Cat((0 until latencyValMaxs(i).get).map { case num =>
           val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == num+1).map(_._1) // futype with latency equal to num+1
           val isLatencyNum = Cat(latencyNumFuType.map(futype => fuTypeRegVec(OHToUInt(io.og0Resp(i).bits.addrOH)) === futype.U)).asUInt().orR() // The latency of the deq inst is Num
@@ -270,54 +271,80 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
         // & ~
       )
       val isLNumVecOg1 = WireInit(~(0.U.asTypeOf(isLatencyNumVec)))
-      if(resps.length == 3){
-        isLNumVecOg1 := Mux(resps(2)(i).valid && resps(2)(i).bits.respType === RSFeedbackType.fuBusy,
-          ~(Cat(Cat((0 until latencyValMaxs(i).get).map { case num =>
-            val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == num+1).map(_._1) // futype with latency equal to num+1
-            val isLatencyNum = Cat(latencyNumFuType.map(futype => fuTypeRegVec(OHToUInt(io.og1Resp(i).bits.addrOH)) === futype.U)).asUInt().orR() // The latency of the deq inst is Num
-            isLatencyNum
-          }), 0.U(2.W))),
-          ~(0.U.asTypeOf(isLatencyNumVec))
-        )
-        // & ~
-      }
+      isLNumVecOg1 := Mux(resps(2)(i).valid && resps(2)(i).bits.respType === RSFeedbackType.fuBusy,
+        ~(Cat(Cat((0 until latencyValMaxs(i).get).map { case num =>
+          val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == num+1).map(_._1) // futype with latency equal to num+1
+          val isLatencyNum = Cat(latencyNumFuType.map(futype => fuTypeRegVec(OHToUInt(io.og1Resp(i).bits.addrOH)) === futype.U)).asUInt().orR() // The latency of the deq inst is Num
+          isLatencyNum
+        }), 0.U(2.W))),
+        ~(0.U.asTypeOf(isLatencyNumVec))
+      )
+      // & ~
+
 
       fuBusyTable(i).get := ((fuBusyTable(i).get << 1.U).asUInt() | isLatencyNumVec) & isLNumVecOg0.asUInt() & isLNumVecOg1.asUInt()
     }
   }
-  // fuBusyTable read
+
   for (i <- 0 until params.numDeq){
+    // fuBusyTable read
     if(fuBusyTable(i).nonEmpty){
       val isReadLatencyNumVec2 = fuBusyTable(i).get.asBools().reverse.zipWithIndex.map { case (en, idx) =>
         val isLatencyNumVec = WireInit(0.U(params.numEntries.W))
         when(en) {
           isLatencyNumVec := VecInit(fuTypeRegVec.map { case futype =>
             val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == idx).map(_._1)
-            val isLatencyNum = Cat(latencyNumFuType.map(_.U === futype)).asUInt().orR()
+            val isLatencyNum = Cat(latencyNumFuType.map(_.U === futype)).asUInt.orR
             isLatencyNum
-          }).asUInt()
+          }).asUInt
         }
         isLatencyNumVec
       }
-      val isWBReadLatencyNumVec2 = io.wbBusyRead(i).asBools().reverse.zipWithIndex.map { case (en, idx) =>
+      if ( latencyValMaxs(i).get > 1 ){
+        fuBusyTableMask(i) := isReadLatencyNumVec2.reduce(_ | _)
+      }else{
+        fuBusyTableMask(i) := isReadLatencyNumVec2.head
+      }
+    } else {
+      fuBusyTableMask(i) := 0.U(params.numEntries.W)
+    }
+
+    // intWbFuBusyTable read
+    val intWbBusyTableMask = if (intWbBusyTableRead(i).isDefined) {
+      intWbBusyTableRead(i).get.asBools.zipWithIndex.map { case (en, idx) =>
         val isLatencyNumVec = WireInit(0.U(params.numEntries.W))
         when(en) {
           isLatencyNumVec := VecInit(fuTypeRegVec.map { case futype =>
-            val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == idx).map(_._1)
+            val latencyNumFuType = intFuLatencyMaps(i).get.filter(_._2 == idx).map(_._1)
+            val isLatencyNum = Cat(latencyNumFuType.map(_.U === futype)).asUInt.orR
+            isLatencyNum
+          }).asUInt
+        }
+        isLatencyNumVec
+      }
+    }.fold(0.U)(_ | _)
+    else{
+      0.U(params.numEntries.W)
+    }
+    // vfWbFuBusyTable read
+    val vfWbBusyTableMask = if (vfWbBusyTableRead(i).isDefined) {
+      vfWbBusyTableRead(i).get.asBools.zipWithIndex.map { case (en, idx) =>
+        val isLatencyNumVec = WireInit(0.U(params.numEntries.W))
+        when(en) {
+          isLatencyNumVec := VecInit(fuTypeRegVec.map { case futype =>
+            val latencyNumFuType = vfFuLatencyMaps(i).get.filter(_._2 == idx).map(_._1)
             val isLatencyNum = Cat(latencyNumFuType.map(_.U === futype)).asUInt().orR()
             isLatencyNum
           }).asUInt()
         }
         isLatencyNumVec
       }
-      if ( latencyValMaxs(i).get > 1 ){
-        fuBusyTableMask(i) := isReadLatencyNumVec2.reduce(_ | _) | isWBReadLatencyNumVec2.reduce(_ | _)
-      }else{
-        fuBusyTableMask(i) := isReadLatencyNumVec2.head | isWBReadLatencyNumVec2.head
-      }
-    } else {
-      fuBusyTableMask(i) := 0.U(params.numEntries.W)
+    }.fold(0.U)(_ | _)
+    else{
+      0.U(params.numEntries.W)
     }
+
+    wbBusyTableMask(i) := intWbBusyTableMask | vfWbBusyTableMask
   }
 
   io.deq.zipWithIndex.foreach { case (deq, i) =>

src/main/scala/xiangshan/backend/issue/Scheduler.scala

@@ -41,9 +41,12 @@ class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSB
   val fromTop = new Bundle {
     val hartId = Input(UInt(8.W))
   }
-  val wbFuBusyTable = new Bundle{
-    val fuBusyTableWrite = MixedVec(params.issueBlockParams.map(x => x.genFuBusyTableWriteBundle))
-    val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genFuBusyTableReadBundle)))
+  val fromWbFuBusyTable = new Bundle{
+    val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle)))
+  }
+  val toWbFuBusyTable = new Bundle{
+    val intFuBusyTableWrite = MixedVec(params.issueBlockParams.map(x => x.genWbFuBusyTableWriteBundle))
+    val vfFuBusyTableWrite = MixedVec(params.issueBlockParams.map(x => x.genWbFuBusyTableWriteBundle))
   }
   val fromCtrlBlock = new Bundle {
     val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W)))
@@ -163,6 +166,7 @@ class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBl
   extends SchedulerImpBase(wrapper)
     with HasXSParameter
 {
+//  dontTouch(io.vfWbFuBusyTable)
   println(s"[SchedulerArithImp] " +
     s"has intBusyTable: ${intBusyTable.nonEmpty}, " +
     s"has vfBusyTable: ${vfBusyTable.nonEmpty}")
@@ -179,10 +183,15 @@ class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBl
       deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B)
       deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType
 
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).deqResp.bits.respType := RSFeedbackType.issueSuccess
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B)
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.respType := RSFeedbackType.issueSuccess
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B)
+
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).deqResp.bits.respType := RSFeedbackType.issueSuccess
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B)
     }
     iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) =>
       og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid
@@ -192,10 +201,15 @@ class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBl
       og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen
       og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType
 
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen
+
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen
     }
     iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) =>
       og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid
@@ -205,12 +219,18 @@ class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBl
       og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen
       og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType
 
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen
+
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType
+      io.toWbFuBusyTable.vfFuBusyTableWrite(i)(j).og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen
     }
-    iq.io.wbBusyRead := io.wbFuBusyTable.fuBusyTableRead(i)
+
+    iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i)
   }
 
   val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map {
@@ -248,10 +268,10 @@ class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBloc
       deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B)
       deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType
 
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).deqResp.bits.respType := RSFeedbackType.issueSuccess
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B)
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.fuType := iq.io.deq(j).bits.common.fuType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.respType := RSFeedbackType.issueSuccess
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).deqResp.bits.rfWen := iq.io.deq(j).bits.common.rfWen.getOrElse(false.B)
     }
     iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) =>
       og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid
@@ -261,10 +281,10 @@ class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBloc
       og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen
       og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType
 
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.fuType := io.fromDataPath(i)(j).og0resp.bits.fuType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og0Resp.bits.rfWen := io.fromDataPath(i)(j).og0resp.bits.rfWen
     }
     iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) =>
       og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid
@@ -274,12 +294,12 @@ class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBloc
       og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen
       og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType
 
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType
-      io.wbFuBusyTable.fuBusyTableWrite(i)(j).og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.fuType := io.fromDataPath(i)(j).og1resp.bits.fuType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType
+      io.toWbFuBusyTable.intFuBusyTableWrite(i)(j).og1Resp.bits.rfWen := io.fromDataPath(i)(j).og1resp.bits.rfWen
     }
-    iq.io.wbBusyRead := io.wbFuBusyTable.fuBusyTableRead(i)
+    iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i)
   }
 
   memAddrIQs.zipWithIndex.foreach { case (iq, i) =>

src/main/scala/xiangshan/backend/issue/StatusArray.scala

@@ -169,12 +169,7 @@ class StatusArray()(implicit p: Parameters, params: IssueBlockParams) extends XS
     }
   }
 
-  val resps = params.schdType match {
-    case IntScheduler() => io.deqResp ++ io.og0Resp ++ io.og1Resp
-    case MemScheduler() => io.deqResp ++ io.og1Resp
-    case VfScheduler()  => io.deqResp ++ io.og1Resp
-    case _ => null
-  }
+  val resps = io.deqResp ++ io.og0Resp ++ io.og1Resp
 
   deqRespVec.zipWithIndex.foreach { case (deqResp, i) =>
     val deqRespValidVec = VecInit(resps.map(x => x.valid && x.bits.addrOH(i)))