Fix ftq bug

build.sc: bump chisel to 3.4.2

fix bug in SDHelper and change default dram latency to 90 cycles

emu: fix --max-cycles and --max-instr

Fix l1plus double hit problem and random replace bug

It used to be changed only when hit

Instead of using io.req.bits as a index to search in valid array, we use
s1_addr register to keep the valid read from valid register array.

roq,exceptionGen: enq_valid should not set when io.flush is valid

roq: block commits when exception.roqIdx === deqPtrVec.last

utils,log: fix PerfDebug conditions

soc: set the number of external interrupts to 150 and dontTouch it

RS: add param srcLen which decides the src data len stored in rs