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提交 ce14a4f1 编写于 作者: W wangkaifan
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Merge branch 'dual-dev' into dual-dev-clean

上级 5a713461 c8e4eb89
展开全部 隐藏空白更改
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Showing with 1324 addition and 1095 deletion
build.sc
浏览文件 @ ce14a4f1
......@@ -29,7 +29,7 @@ trait CommonModule extends ScalaModule {
}
val chisel = Agg(
ivy"edu.berkeley.cs::chisel3:3.4.1"
ivy"edu.berkeley.cs::chisel3:3.4.2"
)
object `api-config-chipsalliance` extends CommonModule {
......
src/main/scala/device/AXI4DummySD.scala
浏览文件 @ ce14a4f1
......@@ -32,23 +32,22 @@ class SDHelper extends BlackBox with HasBlackBoxInline {
setInline("SDHelper.v",
s"""
|import "DPI-C" function void sd_setaddr(input int addr);
|import "DPI-C" function int sd_read(input bit ren);
|import "DPI-C" function void sd_read(output int data);
|
|module SDHelper (
| input clk,
| input setAddr,
| input [31:0] addr,
| input ren,
| output [31:0] data
| output reg [31:0] data
|);
|
| always @(posedge clk) begin
| if (setAddr) begin
| sd_setaddr(addr);
| end
| always @(negedge clk) begin
| if (ren) sd_read(data);
| end
| always@(posedge clk) begin
| if (setAddr) sd_setaddr(addr);
| end
|
| assign data = sd_read(ren);
|
|endmodule
""".stripMargin)
......
src/main/scala/system/SoC.scala
浏览文件 @ ce14a4f1
......@@ -158,7 +158,7 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
lazy val module = new LazyModuleImp(this){
val io = IO(new Bundle{
val extIntrs = Input(Vec(NrExtIntr, Bool()))
val extIntrs = Input(UInt(NrExtIntr.W))
// val meip = Input(Vec(NumCores, Bool()))
val ila = if(env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
})
......@@ -170,7 +170,7 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
val trapIO1 = IO(new xiangshan.TrapIO())
val trapIO = Seq(trapIO0, trapIO1)
plic.module.io.extra.get.intrVec <> RegNext(RegNext(Cat(io.extIntrs)))
plic.module.io.extra.get.intrVec <> RegNext(RegNext(io.extIntrs))
for (i <- 0 until NumCores) {
xs_core(i).module.io.externalInterrupt.mtip := clint.module.io.mtip(i)
......@@ -189,8 +189,9 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
trapIO1 <> xs_core(1).module.trapIO
}
// do not let dma AXI signals optimized out
chisel3.dontTouch(dma.out.head._1)
chisel3.dontTouch(extDev.out.head._1)
dontTouch(dma.out.head._1)
dontTouch(extDev.out.head._1)
dontTouch(io.extIntrs)
}
}
src/main/scala/utils/LogUtils.scala
浏览文件 @ ce14a4f1
......@@ -107,7 +107,7 @@ object XSPerf {
val counter = RegInit(0.U(64.W))
val next_counter = WireInit(0.U(64.W))
val logTimestamp = WireInit(0.U(64.W))
val enableDebug = Parameters.get.envParameters.EnableDebug
val enableDebug = Parameters.get.envParameters.EnablePerfDebug
next_counter := counter + perfCnt
counter := next_counter
......
src/main/scala/utils/Replacement.scala
浏览文件 @ ce14a4f1
......@@ -47,7 +47,7 @@ object ReplacementPolicy {
class RandomReplacement(n_ways: Int) extends ReplacementPolicy {
private val replace = Wire(Bool())
replace := false.B
replace := true.B
def nBits = 16
def perSet = false
private val lfsr = LFSR(nBits, replace)
......
src/main/scala/xiangshan/Bundle.scala
浏览文件 @ ce14a4f1
......@@ -360,6 +360,11 @@ class CSRSpecialIO extends XSBundle {
val interrupt = Output(Bool())
}
class ExceptionInfo extends XSBundle {
val uop = new MicroOp
val isInterrupt = Bool()
}
class RoqCommitInfo extends XSBundle {
val ldest = UInt(5.W)
val rfWen = Bool()
......
src/main/scala/xiangshan/XSCore.scala
浏览文件 @ ce14a4f1
......@@ -50,6 +50,7 @@ case class XSCoreParameters
EnableLB: Boolean = false,
EnableLoop: Boolean = false,
EnableSC: Boolean = false,
EnbaleTlbDebug: Boolean = false,
EnableJal: Boolean = false,
EnableUBTB: Boolean = true,
HistoryLength: Int = 64,
......@@ -102,12 +103,12 @@ case class XSCoreParameters
RefillSize: Int = 512,
TlbEntrySize: Int = 32,
TlbSPEntrySize: Int = 4,
TlbL2EntrySize: Int = 256, // or 512
TlbL2SPEntrySize: Int = 16,
PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
PtwSPEntrySize: Int = 16,
PtwL1EntrySize: Int = 16,
PtwL2EntrySize: Int = 256,
PtwL2EntrySize: Int = 2048,//(256 * 8)
NumPerfCounters: Int = 16,
NrExtIntr: Int = 1
NrExtIntr: Int = 150
)
trait HasXSParameter {
......@@ -140,6 +141,7 @@ trait HasXSParameter {
val EnableLB = core.EnableLB
val EnableLoop = core.EnableLoop
val EnableSC = core.EnableSC
val EnbaleTlbDebug = core.EnbaleTlbDebug
val HistoryLength = core.HistoryLength
val BtbSize = core.BtbSize
// val BtbWays = 4
......@@ -181,8 +183,8 @@ trait HasXSParameter {
val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth
val TlbEntrySize = core.TlbEntrySize
val TlbSPEntrySize = core.TlbSPEntrySize
val TlbL2EntrySize = core.TlbL2EntrySize
val TlbL2SPEntrySize = core.TlbL2SPEntrySize
val PtwL3EntrySize = core.PtwL3EntrySize
val PtwSPEntrySize = core.PtwSPEntrySize
val PtwL1EntrySize = core.PtwL1EntrySize
val PtwL2EntrySize = core.PtwL2EntrySize
val NumPerfCounters = core.NumPerfCounters
......@@ -414,7 +416,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
frontend.io.backend <> ctrlBlock.io.frontend
frontend.io.sfence <> integerBlock.io.fenceio.sfence
frontend.io.tlbCsr := integerBlock.io.csrio.tlb
frontend.io.tlbCsr <> integerBlock.io.csrio.tlb
frontend.io.icacheMemAcq <> l1pluscache.io.req
l1pluscache.io.resp <> frontend.io.icacheMemGrant
......@@ -471,7 +473,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo
integerBlock.io.fenceio.sfence <> memBlock.io.sfence
integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
memBlock.io.tlbCsr := RegNext(integerBlock.io.csrio.tlb)
memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb
floatBlock.io.frm <> integerBlock.io.csrio.frm
......
src/main/scala/xiangshan/backend/CtrlBlock.scala
浏览文件 @ ce14a4f1
......@@ -11,7 +11,7 @@ import xiangshan.backend.exu._
import xiangshan.backend.exu.Exu.exuConfigs
import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq}
import xiangshan.backend.regfile.RfReadPort
import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr, RoqExceptionInfo}
import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr}
import xiangshan.mem.LsqEnqIO
class CtrlToIntBlockIO extends XSBundle {
......@@ -180,7 +180,7 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
val roqio = new Bundle {
// to int block
val toCSR = new RoqCSRIO
val exception = ValidIO(new RoqExceptionInfo)
val exception = ValidIO(new ExceptionInfo)
// to mem block
val lsq = new RoqLsqIO
}
......
src/main/scala/xiangshan/backend/FloatBlock.scala
浏览文件 @ ce14a4f1
......@@ -60,7 +60,8 @@ class FloatBlock
def needData(a: ExuConfig, b: ExuConfig): Boolean =
(a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf)
val readPortIndex = RegNext(io.fromCtrlBlock.readPortIndex)
// val readPortIndex = RegNext(io.fromCtrlBlock.readPortIndex)
val readPortIndex = Seq(0, 1, 2, 3, 2, 3)
val reservedStations = exeUnits.map(_.config).zipWithIndex.map({ case (cfg, i) =>
var certainLatency = -1
if (cfg.hasCertainLatency) {
......@@ -82,7 +83,7 @@ class FloatBlock
s"delay:${certainLatency}"
)
val rs = Module(new ReservationStation(cfg, fastPortsCnt, slowPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = false))
val rs = Module(new ReservationStation(cfg, XLEN + 1, fastPortsCnt, slowPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = false))
rs.io.redirect <> redirect // TODO: remove it
rs.io.flush <> flush // TODO: remove it
......
src/main/scala/xiangshan/backend/IntegerBlock.scala
浏览文件 @ ce14a4f1
......@@ -8,7 +8,6 @@ import xiangshan.backend.exu._
import xiangshan.backend.fu.FenceToSbuffer
import xiangshan.backend.issue.{ReservationStation}
import xiangshan.backend.regfile.Regfile
import xiangshan.backend.roq.RoqExceptionInfo
class WakeUpBundle(numFast: Int, numSlow: Int) extends XSBundle {
val fastUops = Vec(numFast, Flipped(ValidIO(new MicroOp)))
......@@ -76,7 +75,7 @@ class IntegerBlock
val fflags = Flipped(Valid(UInt(5.W))) // from roq
val dirty_fs = Input(Bool()) // from roq
val frm = Output(UInt(3.W)) // to float
val exception = Flipped(ValidIO(new RoqExceptionInfo))
val exception = Flipped(ValidIO(new ExceptionInfo))
val trapTarget = Output(UInt(VAddrBits.W)) // to roq
val isXRet = Output(Bool())
val interrupt = Output(Bool()) // to roq
......@@ -141,7 +140,8 @@ class IntegerBlock
def needData(a: ExuConfig, b: ExuConfig): Boolean =
(a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf)
val readPortIndex = RegNext(io.fromCtrlBlock.readPortIndex)
// val readPortIndex = RegNext(io.fromCtrlBlock.readPortIndex)
val readPortIndex = Seq(1, 2, 3, 0, 1, 2, 3)
val reservationStations = exeUnits.map(_.config).zipWithIndex.map({ case (cfg, i) =>
var certainLatency = -1
if (cfg.hasCertainLatency) {
......@@ -162,7 +162,7 @@ class IntegerBlock
println(s"${i}: exu:${cfg.name} wakeupCnt: ${wakeupCnt} slowPorts: ${extraListenPortsCnt} delay:${certainLatency} feedback:${feedback}")
val rs = Module(new ReservationStation(cfg, wakeupCnt, extraListenPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = feedback))
val rs = Module(new ReservationStation(cfg, XLEN + 1, wakeupCnt, extraListenPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = feedback))
rs.io.redirect <> redirect
rs.io.flush <> flush // TODO: remove it
......
src/main/scala/xiangshan/backend/MemBlock.scala
浏览文件 @ ce14a4f1
......@@ -158,7 +158,7 @@ class MemBlockImp
println(s"${i}: exu:${cfg.name} wakeupCnt: ${wakeupCnt} slowPorts: ${slowPortsCnt} delay:${certainLatency} feedback:${feedback}")
val rs = Module(new ReservationStation(cfg, wakeupCnt, slowPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = feedback))
val rs = Module(new ReservationStation(cfg, XLEN + 1, wakeupCnt, slowPortsCnt, fixedDelay = certainLatency, fastWakeup = certainLatency >= 0, feedback = feedback))
rs.io.redirect <> redirect // TODO: remove it
rs.io.flush <> io.fromCtrlBlock.flush // TODO: remove it
......
src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
浏览文件 @ ce14a4f1
......@@ -21,76 +21,89 @@ class Dispatch2Fp extends XSModule {
/**
* Part 1: generate indexes for reservation stations
*/
val fmacIndexGen = Module(new IndexMapping(dpParams.FpDqDeqWidth, exuParameters.FmacCnt, true))
// val fmacIndexGen = Module(new IndexMapping(dpParams.FpDqDeqWidth, exuParameters.FmacCnt, true))
val fmacCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.fmacCanAccept(deq.bits.ctrl.fuType)))
val fmacPriority = PriorityGen((0 until exuParameters.FmacCnt).map(i => io.numExist(i)))
fmacIndexGen.io.validBits := fmacCanAccept
fmacIndexGen.io.priority := fmacPriority
val (fmacPriority, fmacIndex) = PriorityGen((0 until exuParameters.FmacCnt).map(i => io.numExist(i)))
// fmacIndexGen.io.validBits := fmacCanAccept
// fmacIndexGen.io.priority := fmacPriority
val fmiscIndexGen = Module(new IndexMapping(dpParams.FpDqDeqWidth, exuParameters.FmiscCnt, true))
val fmiscCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.fmiscCanAccept(deq.bits.ctrl.fuType)))
val fmiscPriority = PriorityGen((0 until exuParameters.FmiscCnt).map(i => io.numExist(i+exuParameters.FmacCnt)))
val (fmiscPriority, _) = PriorityGen((0 until exuParameters.FmiscCnt).map(i => io.numExist(i+exuParameters.FmacCnt)))
fmiscIndexGen.io.validBits := fmiscCanAccept
fmiscIndexGen.io.priority := fmiscPriority
val allIndexGen = Seq(fmacIndexGen, fmiscIndexGen)
val validVec = allIndexGen.map(_.io.mapping.map(_.valid)).reduceLeft(_ ++ _)
val indexVec = allIndexGen.map(_.io.mapping.map(_.bits)).reduceLeft(_ ++ _)
for (i <- validVec.indices) {
// val allIndexGen = Seq(fmacIndexGen, fmiscIndexGen)
// val validVec = allIndexGen.map(_.io.mapping.map(_.valid)).reduceLeft(_ ++ _)
// val indexVec = allIndexGen.map(_.io.mapping.map(_.bits)).reduceLeft(_ ++ _)
// for (i <- validVec.indices) {
// XSDebug(p"mapping $i: valid ${validVec(i)} index ${indexVec(i)}\n")
}
// }
/**
* Part 2: assign regfile read ports
*/
val fpStaticIndex = Seq(0, 1, 2, 3)
val fpDynamicIndex = Seq(4, 5)
val fpStaticMappedValid = fpStaticIndex.map(i => validVec(i))
val fpDynamicMappedValid = fpDynamicIndex.map(i => validVec(i))
val (fpReadPortSrc, fpDynamicExuSrc) = RegfileReadPortGen(fpStaticMappedValid, fpDynamicMappedValid)
val fpStaticMapped = fpStaticIndex.map(i => indexVec(i))
val fpDynamicMapped = fpDynamicIndex.map(i => indexVec(i))
for (i <- fpStaticIndex.indices) {
val index = WireInit(VecInit(fpStaticMapped(i) +: fpDynamicMapped))
io.readRf(3*i ) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc1
io.readRf(3*i+1) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc2
io.readRf(3*i+2) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc3
}
val readPortIndex = Wire(Vec(exuParameters.FpExuCnt, UInt(2.W)))
fpStaticIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := i.U})
fpDynamicIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := fpDynamicExuSrc(i)})
// val fpStaticIndex = Seq(0, 1, 2, 3)
// val fpDynamicIndex = Seq(4, 5)
// val fpStaticMappedValid = fpStaticIndex.map(i => validVec(i))
// val fpDynamicMappedValid = fpDynamicIndex.map(i => validVec(i))
// val (fpReadPortSrc, fpDynamicExuSrc) = RegfileReadPortGen(fpStaticMappedValid, fpDynamicMappedValid)
// val fpStaticMapped = fpStaticIndex.map(i => indexVec(i))
// val fpDynamicMapped = fpDynamicIndex.map(i => indexVec(i))
// for (i <- fpStaticIndex.indices) {
// val index = WireInit(VecInit(fpStaticMapped(i) +: fpDynamicMapped))
// io.readRf(3*i ) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc1
// io.readRf(3*i+1) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc2
// io.readRf(3*i+2) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc3
// }
// val readPortIndex = Wire(Vec(exuParameters.FpExuCnt, UInt(2.W)))
// fpStaticIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := i.U})
// fpDynamicIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := fpDynamicExuSrc(i)})
for (i <- 0 until dpParams.IntDqDeqWidth) {
io.readState(3*i ).req := io.fromDq(i).bits.psrc1
io.readState(3*i+1).req := io.fromDq(i).bits.psrc2
io.readState(3*i+2).req := io.fromDq(i).bits.psrc3
}
io.readRf(0) := io.enqIQCtrl(0).bits.psrc1
io.readRf(1) := io.enqIQCtrl(0).bits.psrc2
io.readRf(2) := io.enqIQCtrl(0).bits.psrc3
io.readRf(3) := io.enqIQCtrl(1).bits.psrc1
io.readRf(4) := io.enqIQCtrl(1).bits.psrc2
io.readRf(5) := io.enqIQCtrl(1).bits.psrc3
io.readRf(6) := Mux(io.enqIQCtrl(2).valid, io.enqIQCtrl(2).bits.psrc1, io.enqIQCtrl(4).bits.psrc1)
io.readRf(7) := Mux(io.enqIQCtrl(2).valid, io.enqIQCtrl(2).bits.psrc2, io.enqIQCtrl(4).bits.psrc2)
io.readRf(8) := Mux(io.enqIQCtrl(2).valid, io.enqIQCtrl(2).bits.psrc3, io.enqIQCtrl(4).bits.psrc3)
io.readRf(9) := Mux(io.enqIQCtrl(3).valid, io.enqIQCtrl(3).bits.psrc1, io.enqIQCtrl(5).bits.psrc1)
io.readRf(10) := Mux(io.enqIQCtrl(3).valid, io.enqIQCtrl(3).bits.psrc2, io.enqIQCtrl(5).bits.psrc2)
io.readRf(11) := Mux(io.enqIQCtrl(3).valid, io.enqIQCtrl(3).bits.psrc3, io.enqIQCtrl(5).bits.psrc3)
/**
* Part 3: dispatch to reservation stations
*/
val fmacReady = Cat(io.enqIQCtrl.take(exuParameters.FmacCnt).map(_.ready)).andR
// val fmacReady = Cat(io.enqIQCtrl.take(exuParameters.FmacCnt).map(_.ready)).andR
val fmiscReady = Cat(io.enqIQCtrl.drop(exuParameters.FmacCnt).map(_.ready)).andR
for (i <- 0 until exuParameters.FpExuCnt) {
val enq = io.enqIQCtrl(i)
val deqIndex = if (i < exuParameters.FmacCnt) fmacPriority(i) else fmiscIndexGen.io.mapping(i-exuParameters.FmacCnt).bits
if (i < exuParameters.FmacCnt) {
enq.valid := fmacIndexGen.io.mapping(i).valid && fmacReady
enq.valid := fmacCanAccept(fmacPriority(i))//fmacIndexGen.io.mapping(i).valid && fmacReady
}
else {
enq.valid := fmiscIndexGen.io.mapping(i - exuParameters.FmacCnt).valid && fmiscReady
enq.valid := fmiscIndexGen.io.mapping(i - exuParameters.FmacCnt).valid && fmiscReady && !io.enqIQCtrl(2).valid && !io.enqIQCtrl(3).valid
}
enq.bits := io.fromDq(indexVec(i)).bits
enq.bits := io.fromDq(deqIndex).bits
val src1Ready = VecInit((0 until 4).map(i => io.readState(i * 3).resp))
val src2Ready = VecInit((0 until 4).map(i => io.readState(i * 3 + 1).resp))
val src3Ready = VecInit((0 until 4).map(i => io.readState(i * 3 + 2).resp))
enq.bits.src1State := src1Ready(indexVec(i))
enq.bits.src2State := src2Ready(indexVec(i))
enq.bits.src3State := src3Ready(indexVec(i))
enq.bits.src1State := src1Ready(deqIndex)
enq.bits.src2State := src2Ready(deqIndex)
enq.bits.src3State := src3Ready(deqIndex)
XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
p"srcState(${enq.bits.src1State} ${enq.bits.src2State} ${enq.bits.src3State}) " +
p"enters reservation station $i from ${indexVec(i)}\n")
p"enters reservation station $i from ${deqIndex}\n")
}
/**
......@@ -98,9 +111,10 @@ class Dispatch2Fp extends XSModule {
*/
val fmisc2CanOut = !(fmiscCanAccept(0) && fmiscCanAccept(1))
val fmisc3CanOut = !(fmiscCanAccept(0) && fmiscCanAccept(1) || fmiscCanAccept(0) && fmiscCanAccept(2) || fmiscCanAccept(1) && fmiscCanAccept(2))
val fmacReadyVec = VecInit(io.enqIQCtrl.take(4).map(_.ready))
for (i <- 0 until dpParams.FpDqDeqWidth) {
io.fromDq(i).ready := fmacCanAccept(i) && fmacReady ||
fmiscCanAccept(i) && (if (i <= 1) true.B else if (i == 2) fmisc2CanOut else fmisc3CanOut) && fmiscReady
io.fromDq(i).ready := fmacCanAccept(i) && fmacReadyVec(fmacIndex(i)) ||
fmiscCanAccept(i) && (if (i <= 1) true.B else if (i == 2) fmisc2CanOut else fmisc3CanOut) && fmiscReady && !io.enqIQCtrl(2).valid && !io.enqIQCtrl(3).valid
XSInfo(io.fromDq(i).fire(),
p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Fp dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
......@@ -112,7 +126,8 @@ class Dispatch2Fp extends XSModule {
/**
* Part 5: send read port index of register file to reservation station
*/
io.readPortIndex := readPortIndex
// io.readPortIndex := readPortIndex
io.readPortIndex := DontCare
// val readPortIndexReg = Reg(Vec(exuParameters.FpExuCnt, UInt(log2Ceil(NRFpReadPorts - exuParameters.StuCnt).W)))
// val uopReg = Reg(Vec(exuParameters.FpExuCnt, new MicroOp))
// val dataValidRegDebug = Reg(Vec(exuParameters.FpExuCnt, Bool()))
......
src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
浏览文件 @ ce14a4f1
......@@ -32,73 +32,82 @@ class Dispatch2Int extends XSModule {
val jmpIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, jmpCnt, false))
val mduIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, mduCnt, true))
val aluIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, aluCnt, true))
// val aluIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, aluCnt, true))
val mduPriority = PriorityGen(io.numExist.slice(jmpCnt, jmpCnt + mduCnt))
val aluPriority = PriorityGen(io.numExist.drop(jmpCnt + mduCnt))
val (mduPriority, mduIndex) = PriorityGen(io.numExist.slice(jmpCnt, jmpCnt + mduCnt))
val (aluPriority, aluIndex) = PriorityGen(io.numExist.drop(jmpCnt + mduCnt))
jmpIndexGen.io.validBits := jmpCanAccept
mduIndexGen.io.validBits := mduCanAccept
aluIndexGen.io.validBits := aluCanAccept
// aluIndexGen.io.validBits := aluCanAccept
jmpIndexGen.io.priority := DontCare
mduIndexGen.io.priority := mduPriority
aluIndexGen.io.priority := aluPriority
// aluIndexGen.io.priority := aluPriority
val allIndexGen = Seq(jmpIndexGen, mduIndexGen, aluIndexGen)
val validVec = allIndexGen.flatMap(_.io.mapping.map(_.valid))
val indexVec = allIndexGen.flatMap(_.io.mapping.map(_.bits))
// val allIndexGen = Seq(jmpIndexGen, mduIndexGen, aluIndexGen)
// val validVec = allIndexGen.flatMap(_.io.mapping.map(_.valid))
// val indexVec = allIndexGen.flatMap(_.io.mapping.map(_.bits))
/**
* Part 2: assign regfile read ports
*/
val intStaticIndex = Seq(3, 4, 5, 6)
val intDynamicIndex = Seq(0, 1, 2)
val intStaticMappedValid = intStaticIndex.map(i => validVec(i))
val intDynamicMappedValid = intDynamicIndex.map(i => validVec(i))
val (intReadPortSrc, intDynamicExuSrc) = RegfileReadPortGen(intStaticMappedValid, intDynamicMappedValid)
val intStaticMapped = intStaticIndex.map(i => indexVec(i))
val intDynamicMapped = intDynamicIndex.map(i => indexVec(i))
for (i <- intStaticIndex.indices) {
val index = WireInit(VecInit(intStaticMapped(i) +: intDynamicMapped))
io.readRf(2*i ) := io.fromDq(index(intReadPortSrc(i))).bits.psrc1
io.readRf(2*i+1) := io.fromDq(index(intReadPortSrc(i))).bits.psrc2
}
val readPortIndex = Wire(Vec(exuParameters.IntExuCnt, UInt(2.W)))
intStaticIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := i.U})
intDynamicIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := intDynamicExuSrc(i)})
// val intStaticIndex = Seq(3, 4, 5, 6)
// val intDynamicIndex = Seq(0, 1, 2)
// val intStaticMappedValid = intStaticIndex.map(i => validVec(i))
// val intDynamicMappedValid = intDynamicIndex.map(i => validVec(i))
// val (intReadPortSrc, intDynamicExuSrc) = RegfileReadPortGen(intStaticMappedValid, intDynamicMappedValid)
// val intStaticMapped = intStaticIndex.map(i => indexVec(i))
// val intDynamicMapped = intDynamicIndex.map(i => indexVec(i))
// for (i <- intStaticIndex.indices) {
// val index = WireInit(VecInit(intStaticMapped(i) +: intDynamicMapped))
// io.readRf(2*i ) := io.fromDq(index(intReadPortSrc(i))).bits.psrc1
// io.readRf(2*i+1) := io.fromDq(index(intReadPortSrc(i))).bits.psrc2
// }
// val readPortIndex = Wire(Vec(exuParameters.IntExuCnt, UInt(2.W)))
// intStaticIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := i.U})
// intDynamicIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := intDynamicExuSrc(i)})
io.readRf(0) := io.enqIQCtrl(3).bits.psrc1
io.readRf(1) := io.enqIQCtrl(3).bits.psrc2
io.readRf(2) := Mux(io.enqIQCtrl(4).valid, io.enqIQCtrl(4).bits.psrc1, io.enqIQCtrl(0).bits.psrc1)
io.readRf(3) := io.enqIQCtrl(4).bits.psrc2
io.readRf(4) := Mux(io.enqIQCtrl(5).valid, io.enqIQCtrl(5).bits.psrc1, io.enqIQCtrl(1).bits.psrc1)
io.readRf(5) := Mux(io.enqIQCtrl(5).valid, io.enqIQCtrl(5).bits.psrc2, io.enqIQCtrl(1).bits.psrc2)
io.readRf(6) := Mux(io.enqIQCtrl(6).valid, io.enqIQCtrl(6).bits.psrc1, io.enqIQCtrl(2).bits.psrc1)
io.readRf(7) := Mux(io.enqIQCtrl(6).valid, io.enqIQCtrl(6).bits.psrc2, io.enqIQCtrl(2).bits.psrc2)
for (i <- 0 until dpParams.IntDqDeqWidth) {
io.readState(2*i ).req := io.fromDq(i).bits.psrc1
io.readState(2*i+1).req := io.fromDq(i).bits.psrc2
}
val src1Ready = VecInit((0 until 4).map(i => io.readState(i * 2).resp))
val src2Ready = VecInit((0 until 4).map(i => io.readState(i * 2 + 1).resp))
/**
* Part 3: dispatch to reservation stations
*/
val jmpReady = io.enqIQCtrl(0).ready
val mduReady = Cat(io.enqIQCtrl.slice(jmpCnt, jmpCnt + mduCnt).map(_.ready)).andR
val aluReady = Cat(io.enqIQCtrl.drop(jmpCnt + mduCnt).map(_.ready)).andR
// val aluReady = Cat(io.enqIQCtrl.drop(jmpCnt + mduCnt).map(_.ready)).andR
for (i <- 0 until exuParameters.IntExuCnt) {
val enq = io.enqIQCtrl(i)
val deqIndex = if (i < jmpCnt) jmpIndexGen.io.mapping(0).bits else if (i < jmpCnt + mduCnt) mduIndexGen.io.mapping(i - jmpCnt).bits else aluPriority(i - (jmpCnt + mduCnt))
if (i < jmpCnt) {
enq.valid := jmpIndexGen.io.mapping(i).valid// && jmpReady
enq.valid := jmpIndexGen.io.mapping(i).valid && !io.enqIQCtrl(4).valid
}
else if (i < jmpCnt + mduCnt) {
enq.valid := mduIndexGen.io.mapping(i - jmpCnt).valid && mduReady
enq.valid := mduIndexGen.io.mapping(i - jmpCnt).valid && mduReady && !io.enqIQCtrl(5).valid && !io.enqIQCtrl(6).valid
}
else { // alu
enq.valid := aluIndexGen.io.mapping(i - (jmpCnt + mduCnt)).valid && aluReady
enq.valid := aluCanAccept(aluPriority(i - (jmpCnt + mduCnt))) //aluIndexGen.io.mapping(i - (jmpCnt + mduCnt)).valid //&& aluReady
}
enq.bits := io.fromDq(indexVec(i)).bits
val src1Ready = VecInit((0 until 4).map(i => io.readState(i * 2).resp))
val src2Ready = VecInit((0 until 4).map(i => io.readState(i * 2 + 1).resp))
enq.bits.src1State := src1Ready(indexVec(i))
enq.bits.src2State := src2Ready(indexVec(i))
enq.bits := io.fromDq(deqIndex).bits
enq.bits.src1State := src1Ready(deqIndex)
enq.bits.src2State := src2Ready(deqIndex)
enq.bits.src3State := DontCare
XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
p"srcState(${enq.bits.src1State} ${enq.bits.src2State}) " +
p"enters reservation station $i from ${indexVec(i)}\n")
p"enters reservation station $i from ${deqIndex}\n")
}
/**
......@@ -106,10 +115,11 @@ class Dispatch2Int extends XSModule {
*/
val mdu2CanOut = !(mduCanAccept(0) && mduCanAccept(1))
val mdu3CanOut = !(mduCanAccept(0) && mduCanAccept(1) || mduCanAccept(0) && mduCanAccept(2) || mduCanAccept(1) && mduCanAccept(2))
val aluReadyVec = VecInit(io.enqIQCtrl.drop(jmpCnt + mduCnt).map(_.ready))
for (i <- 0 until dpParams.IntDqDeqWidth) {
io.fromDq(i).ready := jmpCanAccept(i) && (if (i == 0) true.B else !Cat(jmpCanAccept.take(i)).orR) && jmpReady ||
aluCanAccept(i) && aluReady ||
mduCanAccept(i) && (if (i <= 1) true.B else if (i == 2) mdu2CanOut else mdu3CanOut) && mduReady
io.fromDq(i).ready := jmpCanAccept(i) && (if (i == 0) true.B else !Cat(jmpCanAccept.take(i)).orR) && jmpReady && !io.enqIQCtrl(4).valid ||
aluCanAccept(i) && aluReadyVec(aluIndex(i)) ||
mduCanAccept(i) && (if (i <= 1) true.B else if (i == 2) mdu2CanOut else mdu3CanOut) && mduReady && !io.enqIQCtrl(5).valid && !io.enqIQCtrl(6).valid
XSInfo(io.fromDq(i).fire(),
p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Int dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
......@@ -121,7 +131,8 @@ class Dispatch2Int extends XSModule {
/**
* Part 5: send read port index of register file to reservation station
*/
io.readPortIndex := readPortIndex
// io.readPortIndex := readPortIndex
io.readPortIndex := DontCare
// val readPortIndexReg = Reg(Vec(exuParameters.IntExuCnt, UInt(log2Ceil(NRIntReadPorts).W)))
// val uopReg = Reg(Vec(exuParameters.IntExuCnt, new MicroOp))
// val dataValidRegDebug = Reg(Vec(exuParameters.IntExuCnt, Bool()))
......
src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala
浏览文件 @ ce14a4f1
......@@ -24,13 +24,13 @@ class Dispatch2Ls extends XSModule {
*/
val loadIndexGen = Module(new IndexMapping(dpParams.LsDqDeqWidth, exuParameters.LduCnt, true))
val loadCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.loadCanAccept(deq.bits.ctrl.fuType)))
val loadPriority = PriorityGen((0 until exuParameters.LduCnt).map(i => io.numExist(i)))
val (loadPriority, _) = PriorityGen((0 until exuParameters.LduCnt).map(i => io.numExist(i)))
loadIndexGen.io.validBits := loadCanAccept
loadIndexGen.io.priority := loadPriority
val storeIndexGen = Module(new IndexMapping(dpParams.LsDqDeqWidth, exuParameters.StuCnt, true))
val storeCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.storeCanAccept(deq.bits.ctrl.fuType)))
val storePriority = PriorityGen((0 until exuParameters.StuCnt).map(i => io.numExist(i+exuParameters.LduCnt)))
val (storePriority, _) = PriorityGen((0 until exuParameters.StuCnt).map(i => io.numExist(i+exuParameters.LduCnt)))
storeIndexGen.io.validBits := storeCanAccept
storeIndexGen.io.priority := storePriority
......
src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala
浏览文件 @ ce14a4f1
......@@ -76,7 +76,7 @@ object PriorityGen {
}))
priority(sortedIndex(i)) := i.U
}
priority
(priority, sortedIndex)
}
}
......
src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala
浏览文件 @ ce14a4f1
......@@ -7,7 +7,6 @@ import xiangshan._
import xiangshan.backend.exu.Exu.jumpExeUnitCfg
import xiangshan.backend.fu.fpu.IntToFP
import xiangshan.backend.fu.{CSR, Fence, FenceToSbuffer, FunctionUnit, Jump}
import xiangshan.backend.roq.RoqExceptionInfo
class JumpExeUnit extends Exu(jumpExeUnitCfg)
{
......@@ -15,7 +14,7 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
val fflags = Flipped(ValidIO(UInt(5.W)))
val dirty_fs = Input(Bool())
val frm = Output(UInt(3.W))
val exception = Flipped(ValidIO(new RoqExceptionInfo))
val exception = Flipped(ValidIO(new ExceptionInfo))
val trapTarget = Output(UInt(VAddrBits.W))
val isXRet = Output(Bool())
val interrupt = Output(Bool())
......
src/main/scala/xiangshan/backend/ftq/Ftq.scala
浏览文件 @ ce14a4f1
......@@ -281,7 +281,9 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper {
s := s_invalid
}
})
commitStateQueue(next.value).foreach(_ := s_invalid)
when(next.value =/= headPtr.value){ // if next.value === headPtr.value, ftq is full
commitStateQueue(next.value).foreach(_ := s_invalid)
}
}
XSPerf("ftqEntries", validEntries)
......
src/main/scala/xiangshan/backend/fu/Alu.scala
浏览文件 @ ce14a4f1
......@@ -2,10 +2,91 @@ package xiangshan.backend.fu
import chisel3._
import chisel3.util._
import utils.{LookupTree, LookupTreeDefault, ParallelMux, SignExt, XSDebug, ZeroExt}
import utils.{LookupTree, ParallelMux, SignExt, ZeroExt}
import xiangshan._
import xiangshan.backend.ALUOpType
class AddModule extends XSModule {
val io = IO(new Bundle() {
val src1, src2 = Input(UInt(XLEN.W))
val out = Output(UInt((XLEN+1).W))
})
io.out := io.src1 +& io.src2
}
class SubModule extends XSModule {
val io = IO(new Bundle() {
val src1, src2 = Input(UInt(XLEN.W))
val out = Output(UInt((XLEN+1).W))
})
io.out := (io.src1 +& (~io.src2).asUInt()) + 1.U
}
class LeftShiftModule extends XSModule {
val io = IO(new Bundle() {
val shamt = Input(UInt(6.W))
val sllSrc = Input(UInt(XLEN.W))
val sll = Output(UInt(XLEN.W))
})
io.sll := (io.sllSrc << io.shamt)(XLEN - 1, 0)
}
class RightShiftModule extends XSModule {
val io = IO(new Bundle() {
val shamt = Input(UInt(6.W))
val srlSrc, sraSrc = Input(UInt(XLEN.W))
val srl, sra = Output(UInt(XLEN.W))
})
io.srl := io.srlSrc >> io.shamt
io.sra := (io.sraSrc.asSInt() >> io.shamt).asUInt()
}
class ShiftModule extends XSModule {
val io = IO(new Bundle() {
val shamt = Input(UInt(6.W))
val shsrc1 = Input(UInt(XLEN.W))
val sll, srl, sra = Output(UInt(XLEN.W))
})
io.sll := (io.shsrc1 << io.shamt)(XLEN-1, 0)
io.srl := io.shsrc1 >> io.shamt
io.sra := (io.shsrc1.asSInt >> io.shamt).asUInt
}
class MiscResultSelect extends XSModule {
val io = IO(new Bundle() {
val func = Input(UInt())
val sll, slt, sltu, xor, srl, or, and, sra = Input(UInt(XLEN.W))
val miscRes = Output(UInt(XLEN.W))
})
io.miscRes := ParallelMux(List(
ALUOpType.and -> io.and,
ALUOpType.or -> io.or,
ALUOpType.xor -> io.xor,
ALUOpType.slt -> ZeroExt(io.slt, XLEN),
ALUOpType.sltu -> ZeroExt(io.sltu, XLEN),
ALUOpType.srl -> io.srl,
ALUOpType.sll -> io.sll,
ALUOpType.sra -> io.sra
).map(x => (x._1 === io.func(3, 0), x._2)))
}
class AluResSel extends XSModule {
val io = IO(new Bundle() {
val func = Input(UInt())
val isSub = Input(Bool())
val addRes, subRes, miscRes = Input(UInt(XLEN.W))
val aluRes = Output(UInt(XLEN.W))
})
val isAddSub = ALUOpType.isAddSub(io.func)
val res = Mux(ALUOpType.isAddSub(io.func),
Mux(io.isSub, io.subRes, io.addRes),
io.miscRes
)
val h32 = Mux(ALUOpType.isWordOp(io.func), Fill(32, res(31)), res(63, 32))
io.aluRes := Cat(h32, res(31, 0))
}
class Alu extends FunctionUnit with HasRedirectOut {
val (src1, src2, func, pc, uop) = (
......@@ -16,40 +97,63 @@ class Alu extends FunctionUnit with HasRedirectOut {
io.in.bits.uop
)
val offset = src2
val valid = io.in.valid
val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw)
val addRes = src1 +& src2
val subRes = (src1 +& (~src2).asUInt()) + 1.U
val addModule = Module(new AddModule)
addModule.io.src1 := src1
addModule.io.src2 := src2
val subModule = Module(new SubModule)
subModule.io.src1 := src1
subModule.io.src2 := src2
val addRes = addModule.io.out
val subRes = subModule.io.out
val xorRes = src1 ^ src2
val sltu = !subRes(XLEN)
val slt = xorRes(XLEN-1) ^ sltu
val shsrc1 = LookupTreeDefault(func, src1, List(
ALUOpType.srlw -> ZeroExt(src1(31,0), 64),
ALUOpType.sraw -> SignExt(src1(31,0), 64)
))
val shamt = Mux(ALUOpType.isWordOp(func), src2(4, 0), src2(5, 0))
val miscRes = ParallelMux(List(
ALUOpType.sll -> (shsrc1 << shamt)(XLEN-1, 0),
ALUOpType.slt -> ZeroExt(slt, XLEN),
ALUOpType.sltu -> ZeroExt(sltu, XLEN),
ALUOpType.xor -> xorRes,
ALUOpType.srl -> (shsrc1 >> shamt),
ALUOpType.or -> (src1 | src2),
ALUOpType.and -> (src1 & src2),
ALUOpType.sra -> (shsrc1.asSInt >> shamt).asUInt
).map(x => (x._1 === func(3, 0), x._2)))
val res = Mux(ALUOpType.isAddSub(func),
Mux(isAdderSub, subRes, addRes),
miscRes
val isW = ALUOpType.isWordOp(func)
val shamt = Cat(!isW && src2(5), src2(4, 0))
val leftShiftModule = Module(new LeftShiftModule)
leftShiftModule.io.sllSrc := src1
leftShiftModule.io.shamt := shamt
val rightShiftModule = Module(new RightShiftModule)
rightShiftModule.io.shamt := shamt
rightShiftModule.io.srlSrc := Cat(
Mux(isW, 0.U(32.W), src1(63, 32)),
src1(31, 0)
)
rightShiftModule.io.sraSrc := Cat(
Mux(isW, Fill(32, src1(31)), src1(63, 32)),
src1(31, 0)
)
val aluRes = Mux(ALUOpType.isWordOp(func), SignExt(res(31,0), 64), res)
val sll = leftShiftModule.io.sll
val srl = rightShiftModule.io.srl
val sra = rightShiftModule.io.sra
val miscResSel = Module(new MiscResultSelect)
miscResSel.io.func := func(3, 0)
miscResSel.io.sll := sll
miscResSel.io.slt := ZeroExt(slt, XLEN)
miscResSel.io.sltu := ZeroExt(sltu, XLEN)
miscResSel.io.xor := xorRes
miscResSel.io.srl := srl
miscResSel.io.or := (src1 | src2)
miscResSel.io.and := (src1 & src2)
miscResSel.io.sra := sra
val miscRes = miscResSel.io.miscRes
val aluResSel = Module(new AluResSel)
aluResSel.io.func := func
aluResSel.io.isSub := isAdderSub
aluResSel.io.addRes := addRes
aluResSel.io.subRes := subRes
aluResSel.io.miscRes := miscRes
val aluRes = aluResSel.io.aluRes
val branchOpTable = List(
ALUOpType.getBranchType(ALUOpType.beq) -> !xorRes.orR,
......@@ -58,14 +162,9 @@ class Alu extends FunctionUnit with HasRedirectOut {
)
val isBranch = ALUOpType.isBranch(func)
val isRVC = uop.cf.pd.isRVC
val taken = LookupTree(ALUOpType.getBranchType(func), branchOpTable) ^ ALUOpType.isBranchInvert(func)
val target = (pc + offset)(VAddrBits-1,0)
val snpc = Mux(isRVC, pc + 2.U, pc + 4.U)
redirectOutValid := io.out.valid && isBranch
// Only brTag, level, roqIdx are needed
// other infos are stored in brq
redirectOut := DontCare
redirectOut.level := RedirectLevel.flushAfter
redirectOut.roqIdx := uop.roqIdx
......
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @ ce14a4f1
......@@ -7,7 +7,6 @@ import utils._
import xiangshan._
import xiangshan.backend._
import xiangshan.backend.fu.util._
import xiangshan.backend.roq.RoqExceptionInfo
object hartId extends (() => Int) {
var x = 0
......@@ -132,7 +131,7 @@ class CSR extends FunctionUnit with HasCSRConst
// to FPU
val fpu = Flipped(new FpuCsrIO)
// from rob
val exception = Flipped(ValidIO(new RoqExceptionInfo))
val exception = Flipped(ValidIO(new ExceptionInfo))
// to ROB
val isXRet = Output(Bool())
val trapTarget = Output(UInt(VAddrBits.W))
......@@ -323,7 +322,7 @@ class CSR extends FunctionUnit with HasCSRConst
// val sie = RegInit(0.U(XLEN.W))
val sieMask = "h222".U & mideleg
val sipMask = "h222".U & mideleg
val satp = RegInit(0.U(XLEN.W))
val satp = if(EnbaleTlbDebug) RegInit(UInt(XLEN.W), "h8000000000087fbe".U) else RegInit(0.U(XLEN.W))
// val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U) // only use for tlb naive debug
val satpMask = "h80000fffffffffff".U // disable asid, mode can only be 8 / 0
val sepc = RegInit(UInt(XLEN.W), 0.U)
......@@ -747,14 +746,19 @@ class CSR extends FunctionUnit with HasCSRConst
val delegS = deleg(causeNO(3,0)) && (priviledgeMode < ModeM)
val tvalWen = !(hasInstrPageFault || hasLoadPageFault || hasStorePageFault || hasLoadAddrMisaligned || hasStoreAddrMisaligned) || raiseIntr // TODO: need check
val isXRet = io.in.valid && func === CSROpType.jmp && !isEcall
// ctrl block use these 2 cycles later
// 0 1 2
// XRet
// wb -> commit
// -> flush -> frontend redirect
csrio.isXRet := RegNext(RegNext(isXRet))
csrio.trapTarget := Mux(RegNext(RegNext(isXRet)),
RegNext(RegNext(retTarget)),
// ctrl block will use theses later for flush
val isXRetFlag = RegInit(false.B)
val retTargetReg = Reg(retTarget.cloneType)
when (io.flushIn) {
isXRetFlag := false.B
}.elsewhen (isXRet) {
isXRetFlag := true.B
retTargetReg := retTarget
}
csrio.isXRet := isXRetFlag
csrio.trapTarget := Mux(isXRetFlag,
retTargetReg,
Mux(delegS, stvec, mtvec)(VAddrBits-1, 0)
)
......
src/main/scala/xiangshan/backend/fu/Jump.scala
浏览文件 @ ce14a4f1
......@@ -27,7 +27,7 @@ class Jump extends FunctionUnit with HasRedirectOut {
val isJalr = JumpOpType.jumpOpisJalr(func)
val isAuipc = JumpOpType.jumpOpisAuipc(func)
val offset = SignExt(Mux1H(Seq(
val offset = SignExt(ParallelMux(Seq(
isJalr -> ImmUnion.I.toImm32(immMin),
isAuipc -> ImmUnion.U.toImm32(immMin),
!(isJalr || isAuipc) -> ImmUnion.J.toImm32(immMin)
......
src/main/scala/xiangshan/backend/issue/ReservationStation.scala
浏览文件 @ ce14a4f1
......@@ -82,6 +82,7 @@ class SingleSrcCAM[T <: Data](val gen: T, val set: Int, val readWidth: Int, rfZe
class ReservationStation
(
val exuCfg: ExuConfig,
srcLen: Int,
fastPortsCnt: Int,
slowPortsCnt: Int,
fixedDelay: Int,
......@@ -98,13 +99,13 @@ class ReservationStation
val numExist = Output(UInt(iqIdxWidth.W))
val fromDispatch = Flipped(DecoupledIO(new MicroOp))
val deq = DecoupledIO(new ExuInput)
val srcRegValue = Input(Vec(srcNum, UInt((XLEN + 1).W)))
val srcRegValue = Input(Vec(srcNum, UInt(srcLen.W)))
val jumpPc = if(exuCfg == Exu.jumpExeUnitCfg) Input(UInt(VAddrBits.W)) else null
val jalr_target = if(exuCfg == Exu.jumpExeUnitCfg) Input(UInt(VAddrBits.W)) else null
val fastUopOut = ValidIO(new MicroOp)
val fastUopsIn = Vec(fastPortsCnt, Flipped(ValidIO(new MicroOp)))
val fastDatas = Vec(fastPortsCnt, Input(UInt((XLEN+1).W)))
val fastDatas = Vec(fastPortsCnt, Input(UInt(srcLen.W)))
val slowPorts = Vec(slowPortsCnt, Flipped(ValidIO(new ExuOutput)))
val redirect = Flipped(ValidIO(new Redirect))
......@@ -113,9 +114,9 @@ class ReservationStation
val rsIdx = if (feedback) Output(UInt(log2Up(IssQueSize).W)) else null
})
val select = Module(new ReservationStationSelect(exuCfg, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
val ctrl = Module(new ReservationStationCtrl(exuCfg, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
val data = Module(new ReservationStationData(exuCfg, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
val select = Module(new ReservationStationSelect(exuCfg, srcLen, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
val ctrl = Module(new ReservationStationCtrl(exuCfg, srcLen, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
val data = Module(new ReservationStationData(exuCfg, srcLen, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
select.io.redirect := io.redirect
select.io.flush := io.flush
......@@ -178,6 +179,7 @@ class ReservationStation
class ReservationStationSelect
(
val exuCfg: ExuConfig,
srcLen: Int,
fastPortsCnt: Int,
slowPortsCnt: Int,
fixedDelay: Int,
......@@ -366,6 +368,7 @@ class ReservationStationSelect
class ReservationStationCtrl
(
val exuCfg: ExuConfig,
srcLen: Int,
fastPortsCnt: Int,
slowPortsCnt: Int,
fixedDelay: Int,
......@@ -489,7 +492,7 @@ class ReservationStationCtrl
val asynIdxUop = (0 until iqSize).map(i => asynUop(io.indexVec(i)) )
val readyIdxVec = (0 until iqSize).map(i => io.validVec(i) && Cat(srcQueue(io.indexVec(i))).andR )
val fastAsynUop = ParallelPriorityMux(readyIdxVec zip asynIdxUop)
val fastRoqIdx = ParallelPriorityMux(readyIdxVec zip roqIdx)
val fastRoqIdx = ParallelPriorityMux(readyIdxVec zip (0 until iqSize).map(i => roqIdx(io.indexVec(i))))
val fastSentUop = Wire(new MicroOp)
fastSentUop := DontCare
fastSentUop.pdest := fastAsynUop.pdest
......@@ -622,6 +625,7 @@ class RSDataSingleSrc(srcLen: Int, numEntries: Int, numListen: Int) extends XSMo
class ReservationStationData
(
val exuCfg: ExuConfig,
srcLen: Int,
fastPortsCnt: Int,
slowPortsCnt: Int,
fixedDelay: Int,
......@@ -635,7 +639,7 @@ class ReservationStationData
require(nonBlocked==fastWakeup)
val io = IO(new XSBundle {
val srcRegValue = Vec(srcNum, Input(UInt((XLEN + 1).W)))
val srcRegValue = Vec(srcNum, Input(UInt(srcLen.W)))
val jumpPc = if(exuCfg == Exu.jumpExeUnitCfg) Input(UInt(VAddrBits.W)) else null
val jalr_target = if(exuCfg == Exu.jumpExeUnitCfg) Input(UInt(VAddrBits.W)) else null
val in = Input(new Bundle {
......@@ -647,11 +651,11 @@ class ReservationStationData
val listen = new Bundle {
val wen = Input(Vec(srcNum, Vec(iqSize, Vec(fastPortsCnt + slowPortsCnt, Bool()))))
val wdata = Input(Vec(fastPortsCnt + slowPortsCnt, UInt((XLEN + 1).W)))
val wdata = Input(Vec(fastPortsCnt + slowPortsCnt, UInt(srcLen.W)))
}
val sel = Input(UInt(iqIdxWidth.W))
val out = Output(Vec(srcNum, UInt((XLEN + 1).W)))
val out = Output(Vec(srcNum, UInt(srcLen.W)))
val pc = if(exuCfg == Exu.jumpExeUnitCfg) Output(UInt(VAddrBits.W)) else null
})
......@@ -660,7 +664,7 @@ class ReservationStationData
// Data : single read, multi write
// ------------------------
val data = (0 until srcNum).map{i =>
val d = Module(new RSDataSingleSrc(XLEN + 1, iqSize, fastPortsCnt + slowPortsCnt))
val d = Module(new RSDataSingleSrc(srcLen, iqSize, fastPortsCnt + slowPortsCnt))
d.suggestName(s"${this.name}_data${i}")
d.io
}
......
src/main/scala/xiangshan/cache/icache.scala → src/main/scala/xiangshan/cache/ICache.scala
浏览文件 @ ce14a4f1
......@@ -456,7 +456,7 @@ class ICache extends ICacheModule
idx=refillReq.refill_idx,
waymask=refillReq.refill_waymask)
s3_ready := ((io.resp.ready && s3_hit || !s3_valid) && !blocking) || (blocking && ((icacheMissQueue.io.resp.fire()) || io.mmio_grant.fire()))
s3_ready := ((io.resp.fire() || !s3_valid) && !blocking) || (blocking && ((icacheMissQueue.io.resp.fire()) || io.mmio_grant.fire()))
when(icacheFlush){ validArray := 0.U }
......
src/main/scala/xiangshan/cache/icacheMissQueue.scala → src/main/scala/xiangshan/cache/ICacheMissQueue.scala
浏览文件 @ ce14a4f1
......@@ -135,7 +135,7 @@ class IcacheMissEntry extends ICacheMissQueueModule
//TODO: Maybe this sate is noe necessary so we don't need respDataReg
is(s_write_back){
when((io.refill.fire() && io.meta_write.fire()) || needFlush || io.flush){
when((io.refill.fire() && io.meta_write.fire()) || needFlush){
state := s_wait_resp
}
}
......@@ -150,10 +150,10 @@ class IcacheMissEntry extends ICacheMissQueueModule
//refill write and meta write
//WARNING: Maybe could not finish refill in 1 cycle
io.meta_write.valid := (state === s_write_back) && !needFlush && !io.flush
io.meta_write.valid := (state === s_write_back) && !needFlush
io.meta_write.bits.apply(tag=req_tag, setIdx=req_idx, waymask=req_waymask)
io.refill.valid := (state === s_write_back) && !needFlush && !io.flush
io.refill.valid := (state === s_write_back) && !needFlush
io.refill.bits.apply(data=respDataReg.asUInt,
setIdx=req_idx,
waymask=req_waymask)
......
src/main/scala/xiangshan/cache/L1plusCache.scala
浏览文件 @ ce14a4f1
......@@ -88,7 +88,8 @@ object L1plusCacheMetadata {
}
class L1plusCacheMetaReadReq extends L1plusCacheBundle {
val idx = UInt(idxBits.W)
val tagIdx = UInt(idxBits.W)
val validIdx = UInt(idxBits.W)
val way_en = UInt(nWays.W)
val tag = UInt(tagBits.W)
}
......@@ -202,7 +203,7 @@ class L1plusCacheMetadataArray extends L1plusCacheModule {
val resp = Output(Vec(nWays, new L1plusCacheMetadata))
val flush = Input(Bool())
})
val waddr = io.write.bits.idx
val waddr = io.write.bits.tagIdx
val wvalid = io.write.bits.data.valid
val wtag = io.write.bits.data.tag.asUInt
val wmask = Mux((nWays == 1).B, (-1).asSInt, io.write.bits.way_en.asSInt).asBools
......@@ -237,12 +238,12 @@ class L1plusCacheMetadataArray extends L1plusCacheModule {
// tag read
tag_array.io.r.req.valid := io.read.fire()
tag_array.io.r.req.bits.apply(setIdx=io.read.bits.idx)
tag_array.io.r.req.bits.apply(setIdx=io.read.bits.tagIdx)
val rtags = tag_array.io.r.resp.data.map(rdata =>
cacheParams.tagCode.decode(rdata).corrected)
for (i <- 0 until nWays) {
io.resp(i).valid := valid_array(RegNext(io.read.bits.idx))(i)
io.resp(i).valid := valid_array(io.read.bits.validIdx)(i)
io.resp(i).tag := rtags(i)
}
......@@ -253,15 +254,15 @@ class L1plusCacheMetadataArray extends L1plusCacheModule {
def dumpRead() = {
when (io.read.fire()) {
XSDebug("MetaArray Read: idx: %d way_en: %x tag: %x\n",
io.read.bits.idx, io.read.bits.way_en, io.read.bits.tag)
XSDebug("MetaArray Read: idx: (t:%d v:%d) way_en: %x tag: %x\n",
io.read.bits.tagIdx, io.read.bits.validIdx, io.read.bits.way_en, io.read.bits.tag)
}
}
def dumpWrite() = {
when (io.write.fire()) {
XSDebug("MetaArray Write: idx: %d way_en: %x tag: %x new_tag: %x new_valid: %x\n",
io.write.bits.idx, io.write.bits.way_en, io.write.bits.tag, io.write.bits.data.tag, io.write.bits.data.valid)
io.write.bits.tagIdx, io.write.bits.way_en, io.write.bits.tag, io.write.bits.data.tag, io.write.bits.data.valid)
}
}
......@@ -475,7 +476,7 @@ class L1plusCachePipe extends L1plusCacheModule
val data_read = io.data_read.bits
// Tag read for new requests
meta_read.idx := get_idx(io.req.bits.addr)
meta_read.tagIdx := get_idx(io.req.bits.addr)
meta_read.way_en := ~0.U(nWays.W)
meta_read.tag := DontCare
// Data read for new requests
......@@ -502,6 +503,9 @@ class L1plusCachePipe extends L1plusCacheModule
}
s1_valid := s1_valid_reg
meta_read.validIdx := get_idx(s1_addr)
dump_pipeline_reqs("L1plusCachePipe s1", s1_valid, s1_req)
val meta_resp = io.meta_resp
......@@ -726,7 +730,8 @@ class L1plusCacheMissEntry(edge: TLEdgeOut) extends L1plusCacheModule
// meta write
when (state === s_meta_write_req) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.tagIdx := req_idx
io.meta_write.bits.validIdx := req_idx
io.meta_write.bits.data.valid := true.B
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
......@@ -828,7 +833,7 @@ class L1plusCacheMissQueue(edge: TLEdgeOut) extends L1plusCacheModule with HasTL
// print meta_write
XSDebug(io.meta_write.fire(), "meta_write idx %x way_en: %x old_tag: %x new_valid: %d new_tag: %x\n",
io.meta_write.bits.idx, io.meta_write.bits.way_en, io.meta_write.bits.tag,
io.meta_write.bits.tagIdx, io.meta_write.bits.way_en, io.meta_write.bits.tag,
io.meta_write.bits.data.valid, io.meta_write.bits.data.tag)
// print tilelink messages
......
src/main/scala/xiangshan/cache/PTW.scala 0 → 100644
浏览文件 @ ce14a4f1
此差异已折叠。
src/main/scala/xiangshan/cache/tlb.scala → src/main/scala/xiangshan/cache/TLB.scala
浏览文件 @ ce14a4f1
......@@ -38,6 +38,17 @@ trait HasTlbConst extends HasXSParameter {
val v = Bool()
}
}
def replaceWrapper(v: UInt, lruIdx: UInt): UInt = {
val width = v.getWidth
val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U)))
val full = Cat(v).andR
Mux(full, lruIdx, emptyIdx)
}
def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = {
replaceWrapper(VecInit(v).asUInt, lruIdx)
}
}
abstract class TlbBundle extends XSBundle with HasTlbConst
......@@ -275,7 +286,8 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val ifecth = if (isDtlb) false.B else true.B
val mode = if (isDtlb) priv.dmode else priv.imode
// val vmEnable = satp.mode === 8.U // && (mode < ModeM) // FIXME: fix me when boot xv6/linux...
val vmEnable = satp.mode === 8.U && (mode < ModeM)
val vmEnable = if(EnbaleTlbDebug) (satp.mode === 8.U)
else (satp.mode === 8.U && (mode < ModeM))
val reqAddr = req.map(_.bits.vaddr.asTypeOf(vaBundle))
val cmd = req.map(_.bits.cmd)
......@@ -297,36 +309,38 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
/**
* PTW refill
*/
val refill = ptw.resp.fire()
def randReplace(v: UInt) = {
val width = v.getWidth
val randIdx = LFSR64()(log2Up(width)-1, 0)
val priorIdx = PriorityEncoder(~(v))
val full = Cat(v).andR
Mux(full, randIdx, priorIdx)
}
val refill = ptw.resp.fire() && !sfence.valid
val normalReplacer = if (isDtlb) Some("random") else Some("plru")
val superReplacer = if (isDtlb) Some("random") else Some("plru")
val nReplace = ReplacementPolicy.fromString(normalReplacer, TlbEntrySize)
val sReplace = ReplacementPolicy.fromString(superReplacer, TlbSPEntrySize)
val nRefillIdx = replaceWrapper(nv, nReplace.way)
val sRefillIdx = replaceWrapper(sv, sReplace.way)
when (refill) {
val resp = ptw.resp.bits
when (resp.entry.level === 2.U) {
val refillIdx = randReplace(nv.asUInt)
when (resp.entry.level.getOrElse(0.U) === 2.U) {
val refillIdx = nRefillIdx
refillIdx.suggestName(s"NormalRefillIdx")
nv(refillIdx) := true.B
nentry(refillIdx).apply(
vpn = resp.entry.tag,
ppn = resp.entry.ppn,
level = resp.entry.level,
perm = VecInit(resp.entry.perm).asUInt,
level = resp.entry.level.getOrElse(0.U),
perm = VecInit(resp.entry.perm.getOrElse(0.U)).asUInt,
pf = resp.pf
)
XSDebug(p"Refill normal: idx:${refillIdx} entry:${resp.entry} pf:${resp.pf}\n")
}.otherwise {
val refillIdx = randReplace(sv.asUInt)
val refillIdx = sRefillIdx
refillIdx.suggestName(s"SuperRefillIdx")
sv(refillIdx) := true.B
sentry(refillIdx).apply(
vpn = resp.entry.tag,
ppn = resp.entry.ppn,
level = resp.entry.level,
perm = VecInit(resp.entry.perm).asUInt,
level = resp.entry.level.getOrElse(0.U),
perm = VecInit(resp.entry.perm.getOrElse(0.U)).asUInt,
pf = resp.pf
)
XSDebug(p"Refill superpage: idx:${refillIdx} entry:${resp.entry} pf:${resp.pf}\n")
......@@ -336,11 +350,12 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
/**
* L1 TLB read
*/
// val tlb_read_mask = Mux(refill, ((1<<(TlbEntrySize+TlbSPEntrySize))-1).U, 0.U((TlbEntrySize+TlbSPEntrySize).W))
val nRefillMask = Mux(refill, UIntToOH(nRefillIdx)(TlbEntrySize-1, 0), 0.U).asBools
val sRefillMask = Mux(refill, UIntToOH(sRefillIdx)(TlbSPEntrySize-1, 0), 0.U).asBools
def TLBNormalRead(i: Int) = {
val entryHitVec = (
if (isDtlb)
VecInit(entry.map{ e => ~refill && e.hit(reqAddr(i).vpn/*, satp.asid*/)})
VecInit(entry.zip(nRefillMask ++ sRefillMask).map{ case (e,m) => ~m && e.hit(reqAddr(i).vpn)})
else
VecInit(entry.map(_.hit(reqAddr(i).vpn/*, satp.asid*/)))
)
......@@ -349,17 +364,38 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val cmdReg = if (isDtlb) RegNext(cmd(i)) else cmd(i)
val validReg = if (isDtlb) RegNext(valid(i)) else valid(i)
val entryHitVecReg = if (isDtlb) RegNext(entryHitVec) else entryHitVec
entryHitVecReg.suggestName(s"entryHitVecReg_${i}")
val hitVec = (v zip entryHitVecReg).map{ case (a,b) => a&b }
val pfHitVec = (pf zip entryHitVecReg).map{ case (a,b) => a&b }
val hitVec = VecInit((v zip entryHitVecReg).map{ case (a,b) => a&b })
val pfHitVec = VecInit((pf zip entryHitVecReg).map{ case (a,b) => a&b })
val pfArray = ParallelOR(pfHitVec).asBool && validReg && vmEnable
val hit = ParallelOR(hitVec).asBool && validReg && vmEnable && ~pfArray
val miss = !hit && validReg && vmEnable && ~pfArray
val hitppn = ParallelMux(hitVec zip entry.map(_.ppn(reqAddrReg.vpn)))
val hitPerm = ParallelMux(hitVec zip entry.map(_.data.perm))
hitVec.suggestName(s"hitVec_${i}")
pfHitVec.suggestName(s"pfHitVec_${i}")
hit.suggestName(s"hit_${i}")
miss.suggestName(s"miss_${i}")
hitppn.suggestName(s"hitppn_${i}")
hitPerm.suggestName(s"hitPerm_${i}")
if (!isDtlb) { // NOTE: only support one access
val hitVecUInt = hitVec.asUInt
XSDebug(hitVecUInt.orR, p"HitVecUInt:${Hexadecimal(hitVecUInt)}\n")
when (Cat(hitVecUInt(TlbEntrySize-1, 0)).orR && validReg && vmEnable) {
nReplace.access(OHToUInt(hitVecUInt(TlbEntrySize-1, 0)))
XSDebug(p"Normal Page Access: ${Hexadecimal(OHToUInt(hitVecUInt(TlbEntrySize-1, 0)))}\n")
}
when (Cat(hitVecUInt(TlbEntrySize + TlbSPEntrySize - 1, TlbEntrySize)).orR && validReg && vmEnable) {
sReplace.access(OHToUInt(hitVecUInt(TlbEntrySize + TlbSPEntrySize - 1, TlbEntrySize)))
XSDebug(p"Super Page Access: ${Hexadecimal(OHToUInt(hitVecUInt(TlbEntrySize + TlbSPEntrySize - 1, TlbEntrySize)))}\n")
}
}
XSDebug(valid(i), p"(${i.U}) entryHit:${Hexadecimal(entryHitVec.asUInt)}\n")
XSDebug(validReg, p"(${i.U}) entryHitReg:${Hexadecimal(entryHitVecReg.asUInt)} hitVec:${Hexadecimal(VecInit(hitVec).asUInt)} pfHitVec:${Hexadecimal(VecInit(pfHitVec).asUInt)} pfArray:${Hexadecimal(pfArray.asUInt)} hit:${hit} miss:${miss} hitppn:${Hexadecimal(hitppn)} hitPerm:${hitPerm}\n")
XSDebug(validReg, p"(${i.U}) entryHitReg:${Hexadecimal(entryHitVecReg.asUInt)} hitVec:${Hexadecimal(hitVec.asUInt)} pfHitVec:${Hexadecimal(pfHitVec.asUInt)} pfArray:${Hexadecimal(pfArray.asUInt)} hit:${hit} miss:${miss} hitppn:${Hexadecimal(hitppn)} hitPerm:${hitPerm}\n")
val multiHit = {
val hitSum = PopCount(hitVec)
......@@ -409,7 +445,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
waiting := false.B
}
// ptw <> DontCare // TODO: need check it
ptw.req.valid := hasMissReq && !sfence.valid && !waiting && !RegNext(refill)
ptw.req.valid := hasMissReq && !waiting && !RegNext(refill)
ptw.resp.ready := waiting
// val ptwReqSeq = Wire(Seq.fill(Width)(new comBundle()))
......@@ -429,7 +465,6 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
// sfence (flush)
when (sfence.valid) {
ptw.req.valid := false.B
when (sfence.bits.rs1) { // virtual address *.rs1 <- (rs1===0.U)
when (sfence.bits.rs2) { // asid, but i do not want to support asid, *.rs2 <- (rs2===0.U)
// all addr and all asid
......
src/main/scala/xiangshan/cache/ptw.scala 已删除 100644 → 0
浏览文件 @ 5a713461
此差异已折叠。
src/main/scala/xiangshan/frontend/IFU.scala
浏览文件 @ ce14a4f1
......@@ -128,7 +128,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
val if2_valid = RegInit(init = false.B)
val if2_allReady = WireInit(if2_ready && icache.io.req.ready)
val if1_fire = (if1_valid && if2_allReady) && (icache.io.tlb.resp.valid || !if2_valid)
val if1_can_go = if1_fire || if3_flush
val if1_can_go = if1_fire
val if1_gh, if2_gh, if3_gh, if4_gh = Wire(new GlobalHistory)
val if2_predicted_gh, if3_predicted_gh, if4_predicted_gh = Wire(new GlobalHistory)
......@@ -151,7 +151,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
val npcGen = new PriorityMuxGenerator[UInt]
npcGen.register(true.B, RegNext(if1_npc), Some("stallPC"))
val if2_bp = bpu.io.out(0)
// if taken, bp_redirect should be true
// when taken on half RVI, we suppress this redirect signal
......@@ -294,7 +294,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
def br_offset(inst: UInt, rvc: Bool): SInt = {
Mux(rvc,
Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)).asSInt,
Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)).asSInt()
Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)).asSInt()
)
}
val if4_instrs = if4_pd.instrs
......@@ -331,7 +331,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
}
prevHalfInstrReq.valid := if4_fire && if4_bp.saveHalfRVI && HasCExtension.B
// // this is result of the last half RVI
prevHalfInstrReq.bits.pc := if4_pd.pc(PredictWidth-1)
prevHalfInstrReq.bits.npc := snpc(if4_pc)
......@@ -406,7 +406,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
io.toFtq.valid := ftqEnqBuf_valid
io.toFtq.bits := ftqEnqBuf
toFtqBuf := DontCare
toFtqBuf.ftqPC := if4_pc
toFtqBuf.lastPacketPC.valid := if4_pendingPrevHalfInstr
......@@ -584,7 +584,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
XSDebug("[IF3][if3_prevHalfInstr] v=%d pc=%x npc=%x instr=%x ipf=%d\n\n",
if3_prevHalfInstr.valid, if3_prevHalfInstr.bits.pc, if3_prevHalfInstr.bits.npc, if3_prevHalfInstr.bits.instr, if3_prevHalfInstr.bits.ipf)
if3_gh.debug("if3")
XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask)
XSDebug("[IF4][snpc]: %x, realMask=%b\n", if4_snpc, if4_mask)
XSDebug("[IF4][bp] taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI)
......@@ -613,7 +613,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
ftqEnqBuf_valid, ftqEnqBuf_ready, b.ftqPC, b.cfiIndex.valid, b.cfiIndex.bits, b.cfiIsCall, b.cfiIsRet, b.cfiIsRVC)
XSDebug("[FtqEnqBuf] valids=%b br_mask=%b rvc_mask=%b hist=%x predHist=%x rasSp=%d rasTopAddr=%x rasTopCtr=%d\n",
b.valids.asUInt, b.br_mask.asUInt, b.rvc_mask.asUInt, b.hist.asUInt, b.predHist.asUInt, b.rasSp, b.rasTop.retAddr, b.rasTop.ctr)
XSDebug("[ToFTQ] v=%d r=%d leftOne=%d ptr=%d\n", io.toFtq.valid, io.toFtq.ready, io.ftqLeftOne, io.ftqEnqPtr.value)
XSDebug("[ToFTQ] v=%d r=%d leftOne=%d ptr=%d\n", io.toFtq.valid, io.toFtq.ready, io.ftqLeftOne, io.ftqEnqPtr.value)
}
}
src/test/csrc/difftest.cpp
浏览文件 @ ce14a4f1
......@@ -194,8 +194,8 @@ int difftest_step(DiffState *s, int coreid) {
if (s->lfu[i] == 0xC || s->lfu[i] == 0xF) { // Load instruction
ref_difftest_getregs(&ref_r, coreid);
if (ref_r[s->wdst[i]] != s->wdata[i] && selectBit(s->wen, i) != 0) {
printf("---[DIFF Core%d] This load instruction gets rectified!\n", coreid);
printf("--- ltype: 0x%x paddr: 0x%lx wen: 0x%x wdst: 0x%x wdata: 0x%lx pc: 0x%lx\n", s->ltype[i], s->lpaddr[i], selectBit(s->wen, i), s->wdst[i], s->wdata[i], s->wpc[i]);
// printf("---[DIFF Core%d] This load instruction gets rectified!\n", coreid);
// printf("--- ltype: 0x%x paddr: 0x%lx wen: 0x%x wdst: 0x%x wdata: 0x%lx pc: 0x%lx\n", s->ltype[i], s->lpaddr[i], selectBit(s->wen, i), s->wdst[i], s->wdata[i], s->wpc[i]);
uint64_t golden;
int len = 0;
if (s->lfu[i] == 0xC) {
......@@ -225,7 +225,7 @@ int difftest_step(DiffState *s, int coreid) {
case 2: golden = (int64_t)(int32_t)golden; break;
}
}
printf("--- golden: 0x%lx original: 0x%lx\n", golden, ref_r[s->wdst[i]]);
// printf("--- golden: 0x%lx original: 0x%lx\n", golden, ref_r[s->wdst[i]]);
if (golden == s->wdata[i]) {
// ref_difftest_memcpy_from_dut(0x80000000, get_img_start(), get_img_size(), i);
ref_difftest_memcpy_from_dut(s->lpaddr[i], &golden, len, coreid);
......@@ -239,9 +239,9 @@ int difftest_step(DiffState *s, int coreid) {
ref_r[s->wdst[i]] = s->wdata[i];
ref_difftest_setregs(ref_r, coreid);
}
printf("--- atomic instr carefully handled\n");
// printf("--- atomic instr carefully handled\n");
} else {
printf("--- goldenmem check failed as well\n");
// printf("--- goldenmem check failed as well\n");
}
}
}
......
src/test/csrc/emu.cpp
浏览文件 @ ce14a4f1
......@@ -501,7 +501,6 @@ uint64_t Emulator::execute(uint64_t max_cycle, uint64_t max_instr) {
uint32_t lasttime_poll = 0;
uint32_t lasttime_snapshot = 0;
uint64_t lastcommit[NumCore];
uint64_t instr_left_last_cycle[NumCore];
const int stuck_limit = 2000;
const int firstCommit_limit = 10000;
uint64_t core_max_instr[NumCore];
......@@ -524,7 +523,6 @@ uint64_t Emulator::execute(uint64_t max_cycle, uint64_t max_instr) {
diff[i].ltype = ltype[i];
diff[i].lfu = lfu[i];
lastcommit[i] = max_cycle;
instr_left_last_cycle[i] = max_cycle;
core_max_instr[i] = max_instr;
}
......@@ -536,9 +534,7 @@ uint64_t Emulator::execute(uint64_t max_cycle, uint64_t max_instr) {
#endif
while (!Verilated::gotFinish() && trapCode == STATE_RUNNING) {
if (!(max_cycle > 0 &&
core_max_instr[0] > 0 &&
instr_left_last_cycle[0] >= core_max_instr[0])) {
if (!(max_cycle > 0 && core_max_instr[0] > 0)) {
trapCode = STATE_LIMIT_EXCEEDED; /* handle overflow */
break;
}
......@@ -557,6 +553,9 @@ uint64_t Emulator::execute(uint64_t max_cycle, uint64_t max_instr) {
max_cycle --;
if (dut_ptr->io_trap_valid) trapCode = dut_ptr->io_trap_code;
#ifdef DUALCORE
if (dut_ptr->io_trap2_valid) trapCode = dut_ptr->io_trap2_code;
#endif
if (trapCode != STATE_RUNNING) break;
for (int i = 0; i < NumCore; i++) {
......@@ -625,21 +624,26 @@ uint64_t Emulator::execute(uint64_t max_cycle, uint64_t max_instr) {
lastcommit[i] = max_cycle;
// update instr_cnt
instr_left_last_cycle[i] = core_max_instr[i];
core_max_instr[i] -= diff[i].commit;
uint64_t commit_count = (core_max_instr[i] >= diff[i].commit) ? diff[i].commit : core_max_instr[i];
core_max_instr[i] -= commit_count;
}
#ifdef DIFFTEST_STORE_COMMIT
for (int core = 0; core < NumCore; core++) {
if (dut_ptr->io_difftest_storeCommit) {
#ifdef DUALCORE
int storeCommit = (core == 0) ? dut_ptr->io_difftest_storeCommit : dut_ptr->io_difftest2_storeCommit;
#else
int storeCommit = dut_ptr->io_difftest_storeCommit;
#endif
if (storeCommit) {
read_store_info(diff[core].store_addr, diff[core].store_data, diff[core].store_mask);
for (int i = 0; i < dut_ptr->io_difftest_storeCommit; i++) {
for (int i = 0; i < storeCommit; i++) {
auto addr = diff[core].store_addr[i];
auto data = diff[core].store_data[i];
auto mask = diff[core].store_mask[i];
if (difftest_store_step(&addr, &data, &mask)) {
difftest_display(dut_ptr->io_difftest_priviledgeMode);
if (difftest_store_step(&addr, &data, &mask, core)) {
difftest_display(dut_ptr->io_difftest_priviledgeMode, core);
printf("Mismatch for store commits: \n");
printf("REF commits addr 0x%lx, data 0x%lx, mask 0x%x\n", addr, data, mask);
printf("DUT commits addr 0x%lx, data 0x%lx, mask 0x%x\n",
......
src/test/csrc/emu.h
浏览文件 @ ce14a4f1
......@@ -7,7 +7,7 @@
#include <verilated_vcd_c.h> // Trace file format header
#define SNAPSHOT_INTERVAL 60 // unit: second
// #define DIFFTEST_STORE_COMMIT
#define DIFFTEST_STORE_COMMIT
// #define DUALCORE
#ifdef DUALCORE
......
src/test/csrc/ram.cpp
浏览文件 @ ce14a4f1
......@@ -157,7 +157,7 @@ void init_ram(const char *img) {
#endif
assert(dram == NULL);
// dram = new ComplexCoDRAMsim3(DRAMSIM3_CONFIG, DRAMSIM3_OUTDIR);
dram = new SimpleCoDRAMsim3(10);
dram = new SimpleCoDRAMsim3(90);
#endif
pthread_mutex_init(&ram_mutex, 0);
......
src/test/csrc/sdcard.cpp
浏览文件 @ ce14a4f1
......@@ -11,18 +11,14 @@ void sd_setaddr(uint32_t addr) {
//assert(0);
}
uint32_t sd_read(int ren) {
if (ren) {
uint32_t data;
fread(&data, 4, 1, fp);
//printf("read data = 0x%08x\n", *data);
return data;
}
return 0xdeadbeaf;
void sd_read(uint32_t *data) {
fread(data, 4, 1, fp);
//printf("read data = 0x%08x\n", *data);
//assert(0);
}
void init_sd(void) {
fp = fopen("/home/xyn/debian/debian.img", "r");
fp = fopen("/home/xyn/workloads/debian/riscv-debian.img", "r");
if(!fp)
{
eprintf(ANSI_COLOR_MAGENTA "[warning] sdcard img not found\n");
......
src/test/scala/cache/ReplaceTest.scala
浏览文件 @ ce14a4f1
......@@ -78,7 +78,7 @@ class ReplaceTest extends AnyFlatSpec
var tag = 0
for(i <- 0 until testnumber){
if(i%5 == 0){ tag = randomGen.nextInt(maxTag + 1) }
if(i%1 == 0){ tag = randomGen.nextInt(maxTag + 1) }
c.io.req.valid.poke(true.B)
c.io.req.bits.tag.poke(tag.U)
if(c.io.resp.bits.hit.peek().litToBoolean){ hitCounter = hitCounter + 1}
......
src/test/scala/top/XSSim.scala
浏览文件 @ ce14a4f1
......@@ -140,9 +140,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
io.uart <> axiMMIO.module.io.uart
val NumCores = top.Parameters.get.socParameters.NumCores
for (i <- 0 until NrExtIntr) {
soc.module.io.extIntrs(i) := false.B
}
soc.module.io.extIntrs := 0.U
val difftest = Seq(WireInit(0.U.asTypeOf(new DiffTestIO)), WireInit(0.U.asTypeOf(new DiffTestIO)))
val trap = Seq(WireInit(0.U.asTypeOf(new TrapIO)), WireInit(0.U.asTypeOf(new TrapIO)))
......@@ -220,7 +218,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
io.trap2 := trap(1)
}
if (env.EnableDebug) {
if (env.EnableDebug || env.EnablePerfDebug) {
val timer = GTimer()
val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
......
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