- 27 7月, 2021 5 次提交
- 26 7月, 2021 16 次提交
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由 Lingrui98 提交于
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由 JinYue 提交于
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由 JinYue 提交于
* pass the range vector into predecode to mask invalid instructions * set the oversize bits when the new ftb entry has an RVI cfi at the end * pass oversize bit to ifu to indicate this block has more than FetchWidth*4 Bytes
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由 zoujr 提交于
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由 zoujr 提交于
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由 JinYue 提交于
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由 zoujr 提交于
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由 zoujr 提交于
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由 zoujr 提交于
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由 JinYue 提交于
* validate instructions only between startAddr and fallThroughAddr. * mask instructions before replayed load. * mask instructions behind jump.
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由 JinYue 提交于
* only instruction that is predicted taken and is a real cfi, will set taken in PreDecode
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 zoujr 提交于
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由 zoujr 提交于
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- 25 7月, 2021 7 次提交
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由 zoujr 提交于
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由 zoujr 提交于
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由 zoujr 提交于
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由 zoujr 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
1. taken mask should consider corresponding valid bit 2. FetchWidth is in 4 bytes
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由 Lingrui98 提交于
1. previously we flush ftq status at stage2Redirect, but use stage3Redirect to flush ifu, when stage3Redirect comes with pdWb, ifuWbPtr would be falsely increased 2. toBpuUpdate.valid should only assign when do_commit
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- 24 7月, 2021 4 次提交
- 23 7月, 2021 2 次提交
- 21 7月, 2021 1 次提交
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由 zoujr 提交于
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- 20 7月, 2021 5 次提交