This commit limits dequeue width of every RS to 2 for better timing.

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
  for dtlb to use plru.

* mmu.tlb: add tlb at new level named btlb

bridge tlb:
one l0-tlb in each mem pipeline
all the l0-tlb connect to bridge tlb
btlb connects to l2tlb, so btlb is also l1-tlb
itlb remains the same

* mmu.tlb: set tlb size: l0-8, l1-64

* mmu.btlb: add sfence logic

* mmu.tlb: fix bug of sfence logic of g bit

* mmu.btlb: add some perf counter

* mmu.btlb: fix bug of random replace

* mmu.filter: add port vector to record which ports the reqs come from

* mmu.btlb: add some perf counter && add refill mask

* mmu.filter: add check for flushed req

* Use difftest version that auto diables jtag rbb server

Use newer difftest version so that jtag remote bitbang server is automatically disabled. Use --enable-jtag to enable.

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue. 

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
  for dtlb to use plru.

* mmu.l2tlb: cut down l2tlb.l2 to 256 and set l3.way to 8

* mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096

* Revert "mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096"

This reverts commit efbb077ef4be1d4e585a49537ba9be3144423b52.

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

* build.sc: add testOne method for unit test

* AdderTest: add testbench for Adder (passed)

* AdderTree: Add testbench for AdderTree (passed)

* ReferenceCounter: implement a 2-bit counter

* Rename: remove redundant code

* Rename: prepared for move elimination [WIP]

* Roq: add eliminated move bit in roq entry;
  label elim move inst as writebacked
AlternativeFreeList: new impl for int free list
Rename: change io of free list
Dispatch1: (todo) not send move to intDq
Bundle: add eliminatedMove bit in roqCommitInfo, uop and debugio
ReferenceCounter: add debug print msg

* Dispatch1: [BUG FIX] not send move inst to IntDq

* DecodeUnit: [BUG FIX] differentiate li from mv

* Bug fix:
  1. Dispatch1: should not label pdest of move as busy in busy table
  2. Rename: use psrc0 to index bit vec isMax
  3. AlternativeFreeList: fix maxVec calculation logic and ref counter
     increment logic
Besides, more debug info and assertions were added.

* AlternativeFreeList Bug Fix:
  1. add redirect input - shouldn't allocate reg when redirect is
     valid
  2. handle duplicate preg in roqCommits in int free list

* AlternativeFreeList: Fix value assignment race condition

* Rename: Fix value assignment race condition too

* RenameTable: refactor spec/arch table write process

* Roq: Fix debug_exuData of move(addi) instruction
  (it was trash data before because move needn't enter exu)

* Rename: change intFreeList's redirect process
  (by setting headPtr back) and flush process

* ME: microbench & coremark & linux-hello passed
  1. DecodeUnit: treat `mv x,x` inst as non-move
  2. AlternativeFreeList: handle duplicate walk req correctly
  3. Roq: fix debug_exuData bug (make sure writeback that updates
debug_exuData happens before ME instruction in program order)

* AlternativeFreeList: License added
build.sc: remove unused config
Others: comments added

* package rename: remove unused modules

* Roq: Replace debug_prf with a cleaner fix method

* Disp1/AltFL/Rename: del unnecessary white spaces

* build.sc: change stack size
AlternativeFreeList: turn off assertions

* build.sc: change stack size for test

Multi-core Linux can boot now, again.

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

* Add bitmanip v1.0 instructions into decede table
* Fix some instructions' name
* Add basic instructions into Alu
* Add clz, ctz, cpop, clmul Instruction into MulDivExeUnit

* Fix allocated flag update logic

Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

mem,sq: don't set commited flag when mmio commits

For simplicity, we increase cmtPtr and set commited flags when
store instructions commit from ROB. However, this causes problems
when there's an MMIO at the head and new instructions enqueue after
the MMIO finishes but before the MMIO commits.

For example, at cycle T0 mmio store instruction with sqPtr p0
finishes and deqPtr is increased. At cycle T1, a new store
instruction enqueues and the p0 is allocated for this new instruction.
At cycle T2, the mmio instruction commits from ROB. With cmtPtr,
p0 is set to commited. However, since p0 is allocated to the new
store instruction, the commited flag should be false.

The example causes at least two issues. (1) when redirect happens, p0
will not be flushed. (2) p0 will be commit to sbuffer before p0
writes back to store queue.

In this commit, we change how commited flag works. We add a
`hasInflightMMIO` flag. When store instructions commit, we only
set commited flag when `hasInflightMMIO` is not set.

Backend --> ExuBlock --> FuBlock --> Exu --> Function Units
        -->          --> Scheduler --> RS

* misc: remove unused files, bump difftest

* misc: update ready-to-run nemu

misc: update MinimalConfig and add it to ci

misc: implement difftest as a submodule

This commit adds support for multiple enqueue for load and store RS.
Also update the parameters in XSCore to avoid explicitly setting wakeup ports.

Compare SqPtr when an instruction with wait bit enqueuing. This should have minor
performance improvements. Also add some performance counters.

XiangShan is jointly released by ICT and PCL.

When --no-diff option is enable, nemuproxy should not be initialized, to avoid the dependence on NEMU.

* CSR: add csr access check for mstatus.tvm

tvm: trap virtual Memory.
when tvm is set, r/w the satp in S-mode will raise illegal-instr

* Fence: add tvm check that may disallow sfence

when tvm is set and at s-mode, sfence.vma will raise illegal-instr

* change the number of function units in MinimalConfig
* remove some hard-wired values

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

This commit adds an non-parameterized scheduler containing all reservation stations.
Now IntegerBlock, FloatBlock, MemBlock contain only function units.
The Schduler connects dispatch with all function units.
Parameterization to be added later.

* PTW: Repeater support multi req by RRArbiter

* ptw: add parameter to choose repeater and filter(default)

simple ci test show that: the filter is critical for perf
like mcf(5m):
  old ptw:2.38
  new ptw with repeater: 2.41
  new ptw with filter: 2.58

* better select policy timing
* unified RS enqueue ports for 4 ALUs
* wrap imm extractor into a module
* backend,rs: wrap dataArray in RawDataModuleTemplate
* should only bypass data between the same addr when allocate.valid

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