* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

* modify the largest history length to be 65 in order to avoid
  2 level xors on speculative update

* update ittage parameters to be an optimized one

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

It will help difftest skip hpm CSR access correctly

* use compressed info to do redirects
* implement folded history class

* tlb: timing optimization, when nWays is 1, divide hit and data(rm hitMux)

* pmp: add param to control leave ParallelMux into next cycle, default n.

The whole pmp match logic seems too long and takes more than
a half cycle.
Add this param and set it default false.

* tlb: timing optimization, when level enable, move ppn gen to first cycle

* tlb: fix bug of saveLevel and add it to TLBParameters

* disable log as default
* code clean up

Update pma default value

* PreDecode: fix beyond fetch bug

* Fallthrough address === startAddress + 34 Bytes and the 17th 2 Bytes is an RVC instruction, which will be missing when sending to ibuffer

* PreDecode: fix target when beyond fetch happen

* SoC: change buffer latency && set L3 size to 8MB

* BinaryArbiter: fix bugs when iknow < 4

This fixes differences between the pingpong bits in ctrlblock and dispatch2.

* IFU: move mmio to f3 and wait commit

* IFU: fix mmio_has_commit condition

* compare FtqPtr to ensure the mmio instruction has been committed

* Uncache fetch : cancel flush when backend redirect

PreDecode: fix cross-line false hit condition

Predecode: Fixed the bug that Predecode did not compare jal offset wh…

* dcache: do not check readline rmask

This should opt bank_conflict check timing

* dcache: block replace if store s1 valid

It takes quite long to generate way_en in mainpipe s1. As a result,
use s1 way_en to judge if replace should be blocked will cause severe
timing problem

Now we simply block replace if mainpipe.s1.valid

Refill timing to be optmized later

* sbuffer: delay sbuffer enqueue for 1 cycle

With store queue growing larger, read data from datamodule nearly
costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle
for better timing.

* dcache: reduce probe queue size

* dcache: replace probe pipe req RRArbiter with Arbiter

* dcache: reduce writeback queue size for timing opt

* dcache: delay wbqueue enqueue req for 1 cycle

Addr enqueue req will compare its addr with addrs in all writeback
entries to check if it should be blocked. Delay enqueue req will
give that process more time.

* dcache: set default replacer to setplru

It does not change current design

* dcache: fix wbqueue req_delayed deadlock

We delayed writeback queue enq for 1 cycle, missQ req does not
depend on wbQ enqueue. As a result, missQ req may be blocked
in req_delayed. When grant comes, that req should also be updated

* dcache: remove outdated require

* dcache: replace missReqArb RRArbiter with Arbiter

* perf: add detailed histogram for low dcache latency

* dcache: fix wbqueue entry alloc logic

* dcache: opt probe req timing

In current design, resv_set is maintained in dcache. All probe req
will be blocked if that addr is in resv_set.

However, checking if that addr is in resv_set costs almost half a cycle,
which causes severe timing problem.

Now when we update update_resv_set, all probe reqs will be blocked
in the next cycle. It should give Probe reservation set addr compare an
independent cycle, which will lead to better timing

* pmp: add sifive license for match and align logick, thanks rocket.

* pmp: change mux chain to ParallelPriorityMux

* Merge icache-bank-interleave branch

* IFU: Hold ICache Read Result

* ICache: fix vIdx width in bank interleaving

* tlb: timing optimization, fault doesn't care hit now

* mem.atomic: 'paddr write to reg' dont care hit

* mem.atomic: regnext exception and check them next cycle

* tlb.hit: dont care set-bits when hit check

* storequeue: divide tlb.miss with paddr write for opt timing

* mem.atomic: fix bug that wrong usage addrAligned

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams to get correct number of cores

* Bump huancun

* Add pll output

* Fix inclusive cache config

* Add one more pll ctrl reg

* Bump huancun

It helps frontend to get hit result at same cycle and keep req when miss.
Then the itlb can set 'samecycle' to false for better timing.
In a word, it helps to better change non-blocked dtlb to a blocked itlb

* bump huancun

* ptw: consider flush in mem_arb's ready

* l2tlb: add repeater/filter's object apply method

* l2tlb: add one more cycle(repeater) between itlb and l2tlb