request.

Try to catch all possible illegal cache reqs.
(s1_kill, mmio, tlb_miss, replay, etc)

array ready.
Or we will make a combinational loop.
I'm still considering about the correctness and forward progress of our
sync scheme.

Now, it can only do normal load.
It will replay req on cache miss.
Enough for dtlb ptw.

Making stu completely nonblocking.

Fixed it.

Also, dump state machine states of FakeLLC and WBU.

when pipeline stage holds no valid req.