Merge branch 'dev-soc' of github.com:RISCVERS/XiangShan into dev-lsu

src/main/scala/xiangshan/mem/LoadUnit.scala

@@ -23,6 +23,10 @@ class LoadUnit extends XSModule {
     val sbuffer = new LoadForwardQueryIO
     val lsroq = new LoadToLsroqIO
   })
+  
+  when(io.ldin.valid){
+    XSDebug("load enpipe %x iw %x fw %x\n", io.ldin.bits.uop.cf.pc, io.ldin.bits.uop.ctrl.rfWen, io.ldin.bits.uop.ctrl.fpWen)
+  }
 
   //-------------------------------------------------------
   // Load Pipeline
@@ -137,18 +141,18 @@ class LoadUnit extends XSModule {
   io.sbuffer.pc := l4_out.bits.uop.cf.pc
   io.sbuffer.valid := l4_out.valid
 
-  val forwardVec = WireInit(io.lsroq.forward.forwardData)
-  val forwardMask = WireInit(io.lsroq.forward.forwardMask)
+  val forwardVec = WireInit(io.sbuffer.forwardData)
+  val forwardMask = WireInit(io.sbuffer.forwardMask)
   // generate XLEN/8 Muxs
   (0 until XLEN/8).map(j => {
-    when(io.sbuffer.forwardMask(j)) {
+    when(io.lsroq.forward.forwardMask(j)) {
       forwardMask(j) := true.B
-      forwardVec(j) := io.sbuffer.forwardData(j)
+      forwardVec(j) := io.lsroq.forward.forwardData(j)
     }
   })
   l4_out.bits.forwardMask := forwardMask
   l4_out.bits.forwardData := forwardVec
-  
+
   PipelineConnect(l4_out, l5_in, io.ldout.fire() || l5_in.bits.miss && l5_in.valid, false.B)
 
   //-------------------------------------------------------
@@ -225,4 +229,8 @@ class LoadUnit extends XSModule {
   io.ldout <> cdbArb.io.out
   hitLoadOut <> cdbArb.io.in(0)
   io.lsroq.ldout <> cdbArb.io.in(1) // missLoadOut
+
+  when(l5_in.valid){
+    XSDebug("load depipe %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen)
+  }
 }

src/main/scala/xiangshan/mem/Lsroq.scala

@@ -258,8 +258,32 @@ class Lsroq extends XSModule {
   loadWbSel(0) := OHToUInt(lselvec0)
   loadWbSel(1) := OHToUInt(lselvec1)
   (0 until StorePipelineWidth).map(i => {
+    // data select
+    val rdata = data(loadWbSel(i)).data
+    val func = uop(loadWbSel(i)).ctrl.fuOpType
+    val raddr = data(loadWbSel(i)).paddr
+    val rdataSel = LookupTree(raddr(2, 0), List(
+      "b000".U -> rdata(63, 0),
+      "b001".U -> rdata(63, 8),
+      "b010".U -> rdata(63, 16),
+      "b011".U -> rdata(63, 24),
+      "b100".U -> rdata(63, 32),
+      "b101".U -> rdata(63, 40),
+      "b110".U -> rdata(63, 48),
+      "b111".U -> rdata(63, 56)
+    ))
+    val rdataPartialLoad = LookupTree(func, List(
+        LSUOpType.lb   -> SignExt(rdataSel(7, 0) , XLEN),
+        LSUOpType.lh   -> SignExt(rdataSel(15, 0), XLEN),
+        LSUOpType.lw   -> SignExt(rdataSel(31, 0), XLEN),
+        LSUOpType.ld   -> SignExt(rdataSel(63, 0), XLEN),
+        LSUOpType.lbu  -> ZeroExt(rdataSel(7, 0) , XLEN),
+        LSUOpType.lhu  -> ZeroExt(rdataSel(15, 0), XLEN),
+        LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN),
+        LSUOpType.ldu  -> ZeroExt(rdataSel(63, 0), XLEN)
+    ))
     io.ldout(i).bits.uop := uop(loadWbSel(i))
-    io.ldout(i).bits.data := data(loadWbSel(i)).data
+    io.ldout(i).bits.data := rdataPartialLoad
     io.ldout(i).bits.redirectValid := false.B
     io.ldout(i).bits.redirect := DontCare
     io.ldout(i).bits.brUpdate := DontCare