Mem: do not write missed load back to CBD immediately

src/main/scala/xiangshan/mem/LoadUnit.scala

@@ -149,7 +149,7 @@ class LoadUnit extends XSModule {
   l4_out.bits.forwardMask := forwardMask
   l4_out.bits.forwardData := forwardVec
   
-  PipelineConnect(l4_out, l5_in, io.ldout.fire(), false.B)
+  PipelineConnect(l4_out, l5_in, io.ldout.fire() || l5_in.bits.miss && l5_in.valid, false.B)
 
   //-------------------------------------------------------
   // LD Pipeline Stage 5
@@ -202,7 +202,7 @@ class LoadUnit extends XSModule {
   hitLoadOut.bits.redirect := DontCare
   hitLoadOut.bits.brUpdate := DontCare
   hitLoadOut.bits.debug.isMMIO := l5_in.bits.mmio
-  hitLoadOut.valid := l5_in.valid && !l5_in.bits.mmio // MMIO will be done in lsroq
+  hitLoadOut.valid := l5_in.valid && !l5_in.bits.mmio && !l5_in.bits.miss // MMIO will be done in lsroq
   XSDebug(hitLoadOut.fire(), "load writeback: pc %x data %x (%x + %x(%b))\n",
     hitLoadOut.bits.uop.cf.pc, rdataPartialLoad, l5_in.bits.data,
     l5_in.bits.forwardData.asUInt, l5_in.bits.forwardMask.asUInt

src/main/scala/xiangshan/mem/Lsroq.scala

@@ -103,7 +103,7 @@ class Lsroq extends XSModule {
   (0 until LoadPipelineWidth).map(i => {
     when(io.loadIn(i).fire()) {
       when(io.loadIn(i).bits.miss) {
-        XSInfo(io.loadIn(i).valid, "load miss write to cbd idx %d pc 0x%x vaddr %x paddr %x data %x mmio %x roll %x\n",
+        XSInfo(io.loadIn(i).valid, "load miss write to lsroq idx %d pc 0x%x vaddr %x paddr %x data %x mmio %x roll %x\n",
           io.loadIn(i).bits.uop.lsroqIdx,
           io.loadIn(i).bits.uop.cf.pc,
           io.loadIn(i).bits.vaddr,
@@ -267,7 +267,13 @@ class Lsroq extends XSModule {
     io.ldout(i).valid := loadWbSelVec(loadWbSel(i))
     when(io.ldout(i).fire()) {
       writebacked(loadWbSel(i)) := true.B
-      // allocated(loadWbSel(i)) := false.B
+      XSInfo(io.loadIn(i).valid, "load miss write to cbd idx %d pc 0x%x paddr %x data %x mmio %x\n",
+        io.ldout(i).bits.uop.lsroqIdx,
+        io.ldout(i).bits.uop.cf.pc,
+        data(loadWbSel(i)).paddr,
+        data(loadWbSel(i)).data,
+        data(loadWbSel(i)).mmio
+      )
     }
   })