- 22 1月, 2021 2 次提交
- 21 1月, 2021 24 次提交
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由 Yinan Xu 提交于
backend,roq: RegNext isEmpty and block commits when exceptions for better timing
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由 Yinan Xu 提交于
excitingutils: warn wires that have multiple sink|source
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由 jinyue110 提交于
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由 Yinan Xu 提交于
Icache uncache
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由 ZhangZifei 提交于
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由 wangkaifan 提交于
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由 Yinan Xu 提交于
csr: support privMode check for perfcnt regs
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由 Yinan Xu 提交于
opt fdiv timing
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由 jinyue110 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
roq: optimize commit timing and block commits when exceptions occur
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由 jinyue110 提交于
For single port SRAM icache, we disable read when write. So we disable if1_cango when flush if2 register
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由 jinyue110 提交于
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由 jinyue110 提交于
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由 ZhangZifei 提交于
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由 LinJiawei 提交于
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
to not pass fu.ready to dispatch through rs
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由 ZhangZifei 提交于
idx -> index red -> redirect fb -> feedback iss -> issue sel -> select bub -> bubble cnt -> count wu -> wakeup bp -> bypass
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由 Yinan Xu 提交于
excitingutils: fix typo and enhance multiple wiring check
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由 ZhangZifei 提交于
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由 Yinan Xu 提交于
L1plusCache: change SRAM spec.
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由 Yinan Xu 提交于
Use DontCare to remove L2 inner A channel's data field.
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由 William Wang 提交于
LoadQueueData: use sync read
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- 20 1月, 2021 14 次提交
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由 William Wang 提交于
StoreQueue: read sbuffer data 1 cycle earlier
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由 wangkaifan 提交于
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由 William Wang 提交于
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由 Allen 提交于
Store whole cache line in one SRAM. Let backend engineers manually split it into smaller banks.
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由 Allen 提交于
This effectly reduces the number of bus data wires from 256 * 3 to 256 * 2. Use DataDontCareNode to add DontCare to the tilelink nodes you are interested in.
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由 jinyue110 提交于
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由 Yinan Xu 提交于
Icache add mmio support for flash instruction fetch
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由 Yinan Xu 提交于
backend: bug fixes for exception-related logic in Roq and CSR
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由 William Wang 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 jinyue110 提交于
icache: add not bus-width aligned MMIO req support IFU: add mmio aligned function
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由 Fa_wang 提交于
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由 jinyue110 提交于
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