Vector load/store queue, exception handling and writeback will be improved later

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Co-authored-by: lulu0521 <majianlu_0521@163.com>

* Memblock: Add load/store 128 bits datapath

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Co-authored-by: lulu0521 <majianlu_0521@163.com>

* Memblock: fix bug of raw addr match

* Memblock, LoadUnit: Fix Vector RAW paddr match

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Co-authored-by: lulu0521 <majianlu_0521@163.com>

* bump coupledL2

* fix hint counter

* hint: make it more accurate

* cache missed load has highest priority in load s0

* add isHWPrefetch condition for l1 prefetch

* fix s2_ld_valid_dup

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Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* fix load exception buffer enqueue condition

* fix load exception buffer enqueue condition

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* snapshot: add rename snapshot switch

* CtrlBlock: add snapshotGen API

* snapshot: optimize timing

* snapshot: put snapshot logic in a module

* add new ldu and stu

* add fast replay kill at s1

* fix pointer chasing cancel

* pick flushpipe_rvc

* merge flushpipe_rvc

* fix s3_cache_rep and s3_feedbacked

* fix fast replay condition

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Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat after commit;

Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

loadpipe & write conflict fine grained with bank mask, and update on master.

Bump difftest

* all miss entries will have chance to wakeup load replay queue

* LoadUnit: fix ldu bankconflict when forward data from bus

Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* Replay cycles increased from 2 to 3 cycles
* Simplified replay selection logic

* dcache: fix the timing coupling of `ecc_resp` and `s1_tag_match`

* dcache: fix bug in cacheOp's ecc

* dcache: fix bug of compilation

* dcache: fix the timing coupling of `ecc_resp` and `s1_tag_match`

* dcache: fix bug in cacheOp's ecc

* dcache: fix bug of compilation

* dcache: split missqueue enq logic

Now, the miss request entering the missqueue is split into two
cycles, the first cycle determines whether it can enq or merge, and the
second cycle does the actual data update.

In order to send  acquire request to L2 as quickly as possible, the
pipeline register also sends acquire when the situation allows. If
it sends successfully, the s_acquire does not need to be updated to false when
updating MSHR

* missqueue: adjust priority

Make acquire from pipereg have highest priority

* dcache: add some pf counter

* missqueue: fix acquire source in pipeline reg

* In latest design, delay release check will not happen.

* CancelCount to EngPtr violates the timing requirement
* Adding one cycle by regnext for better timing.

* Divide dcache sram into N parts above 8 banks in a cache line.
    * N is configurable, and when it is 1, it is the original config.
* Fine-grained read-write bank conflicts base on dcache divide.

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump huancun & utility

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

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Co-authored-by: Ntastynoob <934348725@qq.com>
Co-authored-by: NGuokai Chen <chenguokai17@mails.ucas.ac.cn>
Co-authored-by: Nlixin <1037997956@qq.com>
Co-authored-by: NXiChen <chenxi171@mails.ucas.ac.cn>
Co-authored-by: NZhou Yaoyang <shinezyy@qq.com>
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
Co-authored-by: Nwakafa <wangkaifan@ict.ac.cn>