SoC: remove 4 buffers between L2 and L3 (#2155)

src/main/scala/top/Top.scala

@@ -99,7 +99,7 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
 
   l3cacheOpt match {
     case Some(l3) =>
-      misc.l3_out :*= l3.node :*= TLBuffer.chainNode(2) :*= misc.l3_banked_xbar
+      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
     case None =>
       val dummyMatch = WireDefault(false.B)
       tiles.map(_.HartId).foreach(hartId => ExcitingUtils.addSource(dummyMatch, s"L3MissMatch_${hartId}", ExcitingUtils.Perf, true))

src/main/scala/xiangshan/XSTile.scala

@@ -72,7 +72,7 @@ class XSTileMisc()(implicit p: Parameters) extends LazyModule
 
   l2_binder match {
     case Some(binder) =>
-      memory_port := TLBuffer.chainNode(2) := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* binder
+      memory_port := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* binder
     case None =>
       memory_port := l1_xbar
   }