- 21 10月, 2021 3 次提交
- 07 10月, 2021 1 次提交
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由 happy-lx 提交于
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- 06 10月, 2021 1 次提交
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由 Jiawei Lin 提交于
* Temporarily disable TLMonitor * Bump huancun (L2/L3 MSHR bug fix)
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- 04 10月, 2021 3 次提交
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由 Jiawei Lin 提交于
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由 Lemover 提交于
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由 Yinan Xu 提交于
* bump difftest * alu: fix max and maxu result * alu: fix src1 generated by opcode Co-authored-by: Zhangfw <471348957@qq.com>
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- 01 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit moves load/store reservation stations into the first ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module is also removed from CtrlBlock. Now the module organization becomes: * ExuBlock: Int RS, Load/Store RS, Int RF, Int FUs * ExuBlock_1: Fp RS, Fp RF, Fp FUs * MemBlock: Load/Store FUs Besides, load queue has 80 entries and store queue has 64 entries now.
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- 30 9月, 2021 2 次提交
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由 Jiawei Lin 提交于
* Refactor cache params * L2: support multi-bank * fix l2 size * remove 'IgnoreNode' * bump difftest and huancun
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由 Jiawei Lin 提交于
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- 29 9月, 2021 1 次提交
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由 lixin 提交于
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- 28 9月, 2021 5 次提交
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由 wakafa 提交于
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由 Yinan Xu 提交于
This commit fixes a bug that causes pc to be wrong values when a jump is blocked for issue and a new jump instruction enters reservation station. When the jump for issue is blocked, we should latch its pc value because the entry has been deallocated from rs (and pc no longer exists in the pc mem).
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由 Yinan Xu 提交于
* change ROB to 256 entries * change physical register file to 192 entries * re-organize reservation stations, function units and regfile
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
* rename Roq to Rob * remove trailing whitespaces * remove unused parameters
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- 27 9月, 2021 7 次提交
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由 wakafa 提交于
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由 Li Qianruo 提交于
* scripts,ci: fix broken multi-core build * Fix debugIntNode on multi core
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
This commit adds storage for PC in JUMP reservation station. Jalr needs four operands now, including rs1, pc, jalr_target and imm. Since Jump currently stores two operands and imm, we have to allocate extra space to store the one more extra operand for jalr. It should be optimized later (possibly by reading jalr_target when issuing the instruction). This commit also adds regression check for PC usages. PC should not enter decode stage.
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由 Jiawei Lin 提交于
* L1D: provide independent meta array for load pipe * misc: reorg files in cache dir * chore: reorg l1d related files * bump difftest: use clang to compile verialted files * dcache: add BankedDataArray * dcache: fix data read way_en * dcache: fix banked data wmask * dcache: replay conflict correctly When conflict is detected: * Report replay * Disable fast wakeup * dcache: fix bank addr match logic * dcache: add bank conflict perf counter * dcache: fix miss perf counters * chore: make lsq data print perttier * dcache: enable banked ecc array * dcache: set dcache size to 128KB * dcache: read mainpipe data from banked data array * dcache: add independent mainpipe data read port * dcache: revert size change * Size will be changed after main pipe refactor * Merge remote-tracking branch 'origin/master' into l1-size * dcache: reduce banked data load conflict * MainPipe: ReleaseData for all replacement even if it's clean * dcache: set dcache size to 128KB BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1, and it has to help l1 to avoid addr alias problem * chore: fix merge conflict * Change L2 to non-inclusive / Add alias bits in L1D * debug: hard coded dup data array for debuging * dcache: fix ptag width * dcache: fix amo main pipe req * dcache: when probe, use vaddr for main pipe req * dcache: include vaddr in atomic unit req * dcache: fix get_tag() function * dcache: fix writeback paddr * huancun: bump version * dcache: erase block offset bits in release addr * dcache: do not require probe vaddr != 0 * dcache: opt banked data read timing * bump huancun * dcache: fix atom unit pipe req vaddr * dcache: simplify main pipe writeback_vaddr * bump huancun * dcache: remove debug data array * Turn on all usr bits in L1 * Bump huancun * Bump huancun * enable L2 prefetcher * bump huancun * set non-inclusive L2/L3 + 128KB L1 as default config * Use data in TLBundleB to hint ProbeAck beeds data * mmu.l2tlb: mem_resp now fills multi mq pte buffer mq entries can just deq without accessing l2tlb cache * dcache: handle dirty userbit * bump huancun * chore: l1 cache code clean up * Remove l1plus cache * Remove HasBankedDataArrayParameters * Add bus pmu between L3 and Mem * bump huncun * dcache: fix l1 probe index generate logic * Now right probe index will be used according to the len of alias bits * dcache: clean up amo pipeline * DCacheParameter rowBits will be removed in the future, now we set it to 128 to make dcache work * dcache: fix amo word index * bump huancun Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn> Co-authored-by: NTangDan <tangdan@ict.ac.cn> Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
This commit applys Definition and Instance for some modules. Refer to https://github.com/chipsalliance/chisel3/pull/2045.
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- 26 9月, 2021 4 次提交
- 25 9月, 2021 2 次提交
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由 Yinan Xu 提交于
This commit optimizes ALUOpType to 7 bits. Alu timing will be checked later. We also apply some misc changes including: * Move REVB, PACK, PACKH, PACKW to ALU * Add fused logicZexth, addwZext, addwSexth * Add instruction fusion test cases to CI
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由 zfw 提交于
* Bmu: support zbk* instructions * ci: add zbk* instruction test
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- 24 9月, 2021 2 次提交
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由 Yinan Xu 提交于
This commit explitly imports freechips..rocketchip.util.property.cover for compatibility reasons, since chisel3 now has a cover statement.
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由 Yinan Xu 提交于
This commit changes how compressed move instructions are decoded. From RISC-V spec, mv pesudoinstruction should be addi. However, previously RVC decoder changes compressed mv to add. Move elimination finds move instructions by addi opcode. Compressed move instructions can now be eliminated.
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- 23 9月, 2021 3 次提交
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由 zoujr 提交于
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由 Li Qianruo 提交于
* New SRT4 divider that may improve timing See "Digital reurrence dividers with reduced logical depth" * SRT16 Int Divider that is working properly * Fix bug related to div 1 * Timing improved version of SRT16 int divider * Add copyright and made some minor changes * Fix bugs related to div 0 * Fix another div 0 bug * Fix another special case bug
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由 Yinan Xu 提交于
backend, freelist: optimize critical path & verilog code size in MEFreeList - optimize free/allocate/walk/flush logic in MEFreeList - remove useless assertions - decrease length of generated verilog file
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- 22 9月, 2021 4 次提交
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由 YikeZhou 提交于
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由 YikeZhou 提交于
instead of chisel var in MEFreeList.scala
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由 Yinan Xu 提交于
This commit adds performance counters for function units that have feedback to reservation stations, including FMA, Load and Store. We add performance counters to show how many instructions are issued for multiple times.
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由 Steve Gou 提交于
FTQ: Fix the false hit bug when run mcf
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- 21 9月, 2021 1 次提交
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由 YikeZhou 提交于
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