* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
  in order to remove casting operation in composer

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

* let ubtb store full targets and fall through addresses
* add some fields in BranchPrediction so that ifu requests can be solely derived from it

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMuxGenerator

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

* write ubtb meta and data at the same time
* fix fallThruError method

[WIP] BPU: Modify BPU and Ftq interfaces

fix bug calc backendRedirectCfi.shift

ftq: update interface

[WIP] BPU: Add lastStage function in BranchPredictionResp

[WIP] BPU: Move Tage to s2

[WIP] BPU: Fix some bugs

ftq: add fast enq logic

[WIP] BPU: Move RAS to s2

bpu: s2 and s3 valid should consider corresponding flush signal

[WIP] BPU: When s1_valid and s2_valid all false,

s3 target need compare with s0_pc_reg, s3_predicted_ghit as well

[WIP] BPU: Move resp.s3 assignment from Tage to RAS

[WIP] BPU: Fix bug that Tage send meta in s2

[WIP] BPU: Add brOffset and jmpOffset in ubtb

tage-sc: fix typos

tage: fix phist support