* bump chisel to 3.5

* Remove deprecated 'toBool' && disable tl monitor

* Update RocketChip / Re-enable TLMonitor

* Makefile: remove '--infer-rw'

* mmu: wrap l2tlb's param withL2TLBParameters

* mmu.l2tlb: add param blockBytes: 64, 8 ptes

* mmu.l2tlb: set l2tlb cache size to l2:256, l3:4096

* mmu.l2tlb: add config print

* mmu.l2tlb: fix bug of resp data indices choosen and opt coding style

* rs,bypass: remove optBuf for valid bits

* rs,bypass: add left and right bypass strategy

This commit adds another bypass network implementation to optimize timing of the first stage of function units.

In BypassNetworkLeft, we bypass data at the same cycle that function units write data back. This increases the length of the critical path of the last stage of function units but reduces the length of the critical path of the first stage of function units. Some function units that require a shorter stage zero, like LOAD, may use BypassNetworkLeft.

In this commit, we set all bypass networks to the left style, but we will make it configurable depending on different function units in the future.

This commit changes how io.out is computed for age detector. We use a
register to keep track of the position of the oldest instruction. Since
the updating information has better timing than issue, this could
optimize the timing of issue logic.

* modify UBitPeriod to one-eights of the previous value to adapt
  to nRows enlarged by eight times
* fix a bug assigning sc update mask

bpu: add redirect logic between stages for circumstances where directions differ but targets remain the same

This commit reduces register usage in age detector via using the
upper matrix only. Since the age matrix is symmetric, age(i)(j)
equals !age(j)(i). Besides, age(i)(i) is the same as valid(i).
Thus, we also remove validVec in this commit.

This commit adds a fastUopOut option to function units. This allows the
function units to give valid and uop one cycle before its output data is
ready. FastUopOut lets writeback arbitration happen one cycle before
data is ready and helps optimize the timing.

Since some function units are not ready for this new feature, this
commit adds a fastImplemented option to allow function units to have
fastUopOut but the data is still at the same cycle as uop. This option
will delay the data for one cycle and may cause performance degradation.
FastImplemented should be true after function units support fastUopOut.

* This will be a problem when a RVI jal is the last instrution of a basic
block. The realEndPC will greater than startAddr + 32 bytes.

This commit adds support for directly connecting data from function
units if the function units exclusively own the writeback ports. This
happens for ALU and FMA currently.

* write ubtb meta and data at the same time
* fix fallThruError method

* separate the Alu instructions by 64bit data instructions and w-suffix instructions
* optimize select logic of instructions result

* fix a bug when establishing new ftb entry with a jalr
* use ftb hit signal instead of ubtb to assign entry_hit_status
* move always taken logic to ftb

* use --enable-fork option to open lightSSS when running emu

* EMU_THREADS(>1) and EMU_TRACE should be set before compiling if using
lightSSS

* move lightSSS config to difftest/config/config.h

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters in bus pmu

* Insert BusPMU between L3 and L2

* add some TMA perfcnt
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

This commit changes how to organize reservation stations in the
second ExuBlock. Now the second ExuBlock accepts MUL, MUL, STD, STD.
The int regfile in this ExuBlock becomes 6R8W.

This commit changes how performance data file is named. Previously
we use GITHUB_SHA or pull_request.head.sha. However, we cannot easily
get the sha or they do not work for master branch.

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
  for dtlb to use plru.

* mmu.tlb: raise pf to update a/d

* fp: fix bug of ieee NaN multiple results

* CSR: fix bug of not clearing mprv at mret when mpp is M

* backend, rs: add an age matrix to find the oldest instruction

This commit adds an age matrix to reservation station to find
the oldest instruction. This enables the RS to schedule the oldest
instruction first.

This commit also adda performance counter for oldest inst

* IFU pipeline begin with f0 and end with f3