Opt decode

dispatch2: optimize load/store busyTable read timing and fuType, srcState usages

the cs_src1Type will increase the delay because it need decode info

and change rs data part's listen logic
when enq, if src from rf is not ready, the src will not be writen
  n data module
change enq listen src update logic, remote the highest bit of srcUpdate
which may be done later: enq listen will update srcQueue one cycle
  later

fix pipeline flush bug

dispatch,MemBlock: optimize fuType usages

Trace debug

div: don't accept new request when it's cancelled

SRAMTemplate: fix wmask and update license

LoadQueue: fix lq writeback uop read logic

L2, L3: change SRAM width to 256 bit.

dev-prefetcher: replace stream prefetch with best-offset in L2Prefetcher

Give replay check an extra cycle (store s3)

makefile: generate memory modules and commit id when make verilog