- 12 11月, 2021 5 次提交
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由 zoujr 提交于
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由 zoujr 提交于
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由 Lingrui98 提交于
* modify the largest history length to be 65 in order to avoid 2 level xors on speculative update * update ittage parameters to be an optimized one
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由 Lingrui98 提交于
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由 Lingrui98 提交于
bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top
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- 11 11月, 2021 5 次提交
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由 William Wang 提交于
It will help difftest skip hpm CSR access correctly
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由 Lingrui98 提交于
* use compressed info to do redirects * implement folded history class
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由 Lemover 提交于
* tlb: timing optimization, when nWays is 1, divide hit and data(rm hitMux) * pmp: add param to control leave ParallelMux into next cycle, default n. The whole pmp match logic seems too long and takes more than a half cycle. Add this param and set it default false. * tlb: timing optimization, when level enable, move ppn gen to first cycle * tlb: fix bug of saveLevel and add it to TLBParameters
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由 Yinan Xu 提交于
* disable log as default * code clean up
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由 rvcoresjw 提交于
Update pma default value
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- 10 11月, 2021 2 次提交
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由 wakafa 提交于
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由 Fawang Zhang 提交于
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- 09 11月, 2021 5 次提交
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由 rvcoresjw 提交于
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由 rvcoresjw 提交于
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由 Jay 提交于
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由 Jay 提交于
* PreDecode: fix beyond fetch bug * Fallthrough address === startAddress + 34 Bytes and the 17th 2 Bytes is an RVC instruction, which will be missing when sending to ibuffer * PreDecode: fix target when beyond fetch happen
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由 Jiawei Lin 提交于
* SoC: change buffer latency && set L3 size to 8MB * BinaryArbiter: fix bugs when iknow < 4
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- 07 11月, 2021 1 次提交
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由 Yinan Xu 提交于
This fixes differences between the pingpong bits in ctrlblock and dispatch2.
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- 05 11月, 2021 2 次提交
- 04 11月, 2021 4 次提交
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由 Steve Gou 提交于
PreDecode: fix cross-line false hit condition
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由 Steve Gou 提交于
Predecode: Fixed the bug that Predecode did not compare jal offset wh…
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由 William Wang 提交于
* dcache: do not check readline rmask This should opt bank_conflict check timing * dcache: block replace if store s1 valid It takes quite long to generate way_en in mainpipe s1. As a result, use s1 way_en to judge if replace should be blocked will cause severe timing problem Now we simply block replace if mainpipe.s1.valid Refill timing to be optmized later * sbuffer: delay sbuffer enqueue for 1 cycle With store queue growing larger, read data from datamodule nearly costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle for better timing. * dcache: reduce probe queue size * dcache: replace probe pipe req RRArbiter with Arbiter * dcache: reduce writeback queue size for timing opt * dcache: delay wbqueue enqueue req for 1 cycle Addr enqueue req will compare its addr with addrs in all writeback entries to check if it should be blocked. Delay enqueue req will give that process more time. * dcache: set default replacer to setplru It does not change current design * dcache: fix wbqueue req_delayed deadlock We delayed writeback queue enq for 1 cycle, missQ req does not depend on wbQ enqueue. As a result, missQ req may be blocked in req_delayed. When grant comes, that req should also be updated * dcache: remove outdated require * dcache: replace missReqArb RRArbiter with Arbiter * perf: add detailed histogram for low dcache latency * dcache: fix wbqueue entry alloc logic * dcache: opt probe req timing In current design, resv_set is maintained in dcache. All probe req will be blocked if that addr is in resv_set. However, checking if that addr is in resv_set costs almost half a cycle, which causes severe timing problem. Now when we update update_resv_set, all probe reqs will be blocked in the next cycle. It should give Probe reservation set addr compare an independent cycle, which will lead to better timing
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由 JinYue 提交于
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- 02 11月, 2021 2 次提交
- 01 11月, 2021 3 次提交
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由 zoujr 提交于
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由 Jay 提交于
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由 Lemover 提交于
* tlb: timing optimization, fault doesn't care hit now * mem.atomic: 'paddr write to reg' dont care hit * mem.atomic: regnext exception and check them next cycle * tlb.hit: dont care set-bits when hit check * storequeue: divide tlb.miss with paddr write for opt timing * mem.atomic: fix bug that wrong usage addrAligned
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- 30 10月, 2021 2 次提交
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由 Yinan Xu 提交于
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由 Jiawei Lin 提交于
* Add cache ctrl node * L2/L3: Reduce client dir size * Ctrl: connect soft reset from L3 to core * Add pll * Config: seperate SocParams and CoreParams to get correct number of cores * Bump huancun * Add pll output * Fix inclusive cache config * Add one more pll ctrl reg * Bump huancun
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- 29 10月, 2021 5 次提交
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由 Lemover 提交于
It helps frontend to get hit result at same cycle and keep req when miss. Then the itlb can set 'samecycle' to false for better timing. In a word, it helps to better change non-blocked dtlb to a blocked itlb
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由 William Wang 提交于
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由 William Wang 提交于
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由 Jiawei Lin 提交于
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由 Jay 提交于
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- 28 10月, 2021 1 次提交
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由 wakafa 提交于
* bump huancun * ptw: consider flush in mem_arb's ready
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- 27 10月, 2021 3 次提交
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由 Lemover 提交于
* l2tlb: add repeater/filter's object apply method * l2tlb: add one more cycle(repeater) between itlb and l2tlb
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由 William Wang 提交于
* mem: update lsu op encoding * decode: remove prefetch bits from CtrlSignals * mem: simplify software prefetch logic in loadpipe * mem: fix wrong dcacheShouldResp assertion
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由 Jiawei Lin 提交于
* Bump huancun * Simplify l2 -> l3 cross bar * HuanCun: remove debug print
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