* Untested Trigger Implementation
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>
Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>

BPU: implement PhyPriorityMuxGenerator, distinguish between logical priority and physical priority

* assuming that beyond fetch => oversize

implement folded global histories for tage-sc/ittage

* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

core: add one more cycles between dtlb and ptw

* FDivSqrt: replace hardfloat by fudian

* use pipeline branch for fudian

* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

* difftest: add basic difftest features for releases

This commit adds basic difftest features for every release, no matter
it's for simulation or physical design. The macro SYNTHESIS is used to
skip these logics when synthesizing the design. This commit aims at
allowing designs for physical design to be verified.

* bump ready-to-run

* difftest: add int and fp writeback data

* modify the largest history length to be 65 in order to avoid
  2 level xors on speculative update

* update ittage parameters to be an optimized one

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

It will help difftest skip hpm CSR access correctly

* use compressed info to do redirects
* implement folded history class

* tlb: timing optimization, when nWays is 1, divide hit and data(rm hitMux)

* pmp: add param to control leave ParallelMux into next cycle, default n.

The whole pmp match logic seems too long and takes more than
a half cycle.
Add this param and set it default false.

* tlb: timing optimization, when level enable, move ppn gen to first cycle

* tlb: fix bug of saveLevel and add it to TLBParameters

* disable log as default
* code clean up

Update pma default value

* PreDecode: fix beyond fetch bug

* Fallthrough address === startAddress + 34 Bytes and the 17th 2 Bytes is an RVC instruction, which will be missing when sending to ibuffer

* PreDecode: fix target when beyond fetch happen

* SoC: change buffer latency && set L3 size to 8MB

* BinaryArbiter: fix bugs when iknow < 4

This fixes differences between the pingpong bits in ctrlblock and dispatch2.

* IFU: move mmio to f3 and wait commit

* IFU: fix mmio_has_commit condition

* compare FtqPtr to ensure the mmio instruction has been committed

* Uncache fetch : cancel flush when backend redirect