- 15 2月, 2023 1 次提交
-
-
由 Maxpicca 提交于
Besides adding load/store arch database, this PR also fixed a bug which caused prefetch using l1 info failed to work. Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher failed to receive prefetch train info from L1. This commit should fix that. * ROB: add inst db drop globalID signal output is still duplicated * TLB: TLB will carry mem idx when req and resp * InstDB: update the TLBFirstIssue * InstDB: the first version is complete * InstDB: update decode logic * InstDB: update ctrlBlock writeback * Merge: fix bug * merge: fix compile bug * code rule: rename debug signals and add db's FPGA signal control * code rule: update db's FPGA signal control * ldu: fix isFirstIssue flag for ldflow from rs * ldu: isFirstIssue flag for hw pf is always false --------- Co-authored-by: Ngood-circle <fenghaoyuan19@mails.ucas.ac.cn> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
-
- 14 2月, 2023 1 次提交
-
-
由 bugGenerator 提交于
* test: add example to genenrate verilog for a small module Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop * test: add DecodeUnitTest as an example for xs' chiseltest * ctrlblock: <> usage has changed, unidirection should use := * bump huancun * makefile: mv new makefile cmd into Makefile.test
-
- 13 2月, 2023 1 次提交
-
-
由 bugGenerator 提交于
Here is a bug cause by EnableUncacheWriteOutstanding: The case is extintr in Nexus-AM. Three steps of the test: clear intrGen's intr: Stop pass interrupt. A mmio write. clear plic claim: complete intr. A mmio write. read plic claim to check: claim should be 0. A mmio read. The corner case: intrGen's mmio write is to slow. The instruction after it executes and plic claim's mmio's write & read execute before it. On the side of core with plic, claim is cleared. But on the side of intrGen with plic, the source of interrupt is still enabled and trigger interrupt. So the "read plic claim to check" get a valid claim and failed.
-
- 11 2月, 2023 3 次提交
-
-
由 William Wang 提交于
SimTop: add support for Constantin
-
由 William Wang 提交于
dtlb: set pf-tlb's ready to be True by default
-
由 ZhangZifei 提交于
-
- 10 2月, 2023 2 次提交
-
-
由 William Wang 提交于
-
由 William Wang 提交于
-
- 08 2月, 2023 2 次提交
-
-
由 Guokai Chen 提交于
-
由 William Wang 提交于
sms,ldu,dcache: prefetch to l1 framework & new load flow arb
-
- 06 2月, 2023 3 次提交
-
-
由 wakafa 提交于
-
由 bugGenerator 提交于
-
由 William Wang 提交于
Software prefetch flow (from storeprefetch uop) will not be replayed unless tlb reports a miss. In that case, software prefetch flow behaves like an normal tlb missed load. Hardware prefetch flow will never be replayed.
-
- 05 2月, 2023 5 次提交
-
-
由 William Wang 提交于
This commit refactors ldu load_s0 load flow arbitor logic. Now there are 6 load flow sources, which are (priority high -> low): src0: load replayed by LSQ (io.lsqOut) src1: hardware prefetch from prefetchor (high confidence) (io.prefetch) src2: int read / software prefetch first issue from RS (io.in) src3: vec read first issue from RS (TODO) src4: load try pointchaising when no issued or replayed load (io.fastpath) src5: hardware prefetch from prefetchor (high confidence) (io.prefetch)
-
由 xiwenx 提交于
-
由 czw 提交于
-
由 Haoyuan Feng 提交于
Co-authored-by: NZhangZifei <1773908404@qq.com>
-
由 Haoyuan Feng 提交于
-
- 04 2月, 2023 1 次提交
-
-
由 Steve Gou 提交于
-
- 02 2月, 2023 2 次提交
-
-
由 William Wang 提交于
-
由 William Wang 提交于
-
- 01 2月, 2023 4 次提交
-
-
由 William Wang 提交于
-
由 William Wang 提交于
-
由 William Wang 提交于
-
由 William Wang 提交于
-
- 31 1月, 2023 2 次提交
-
-
由 William Wang 提交于
-
由 William Wang 提交于
-
- 30 1月, 2023 3 次提交
-
-
由 William Wang 提交于
TODO: ldflow from prefetch to be added to ldflow select logic
-
由 William Wang 提交于
-
由 William Wang 提交于
-
- 29 1月, 2023 8 次提交
-
-
由 William Wang 提交于
-
由 William Wang 提交于
Now SMS is the same as f684ed00
-
由 LinJiawei 提交于
-
由 LinJiawei 提交于
-
由 Yinan Xu 提交于
-
由 William Wang 提交于
-
由 William Wang 提交于
-
由 William Wang 提交于
TLB and Huancun conflict fix is not included in this commit
-
- 28 1月, 2023 2 次提交
-
-
由 William Wang 提交于
-
由 LinJiawei 提交于
-