Roq: add a "just enough" roq to backend

Regfile: finish regfile

Brq: finish brq

* Roq size is set to 32 to speedup FIRRTL compile

FreeList: set tailPtr's initial value to '1<<PhyRegIdxWidth'

Finish rename stage

EXU/ALU： add ALU and add ALU/BRU's redirect to Brq

ALU/BRU's outRedirect.bits is passed Brq directly.
Redirect's valid is ALU/BRU's fire()

Rename: send phy-reg status(rdy/busy) to dispatch-2

1. add ALU(almost copy from Noop.ALU)
   remove jal/jalr/ret/call from ALU
   remove predictWrong from ALU(judged by brq now)
   remove bpuUpdateReq from ALU
2. add Redirect to ExuOutput
   it is connected to brq

1. remove ExuInput.redirect to ExuIO.redirect for input redirect
don't need waiting for function unit's in.valid.
2. remove ExuOutput.redirect for redirect is only generate by brq
and roq. ALU/BRU.bj instr only need generate target and send to
brq.

Bundle/ExuIO: add redirect to ExuInput and ExuOutput

  ExuInput is used to flush the function unit itself.
  ExuOutput is used to flush other function units.
  Just ROB, bru(can exec jal/jalr/csr instrs) and alu(can exec
branch instrs) can generate redirect.

Add freelist ptr in MicroOp