Roq: add a "just enough" Roq

src/main/scala/xiangshan/Bundle.scala

@@ -56,7 +56,7 @@ class Redirect extends XSBundle {
   val target = UInt(VAddrBits.W)
   val brTag = UInt(BrTagWidth.W)
   val isException = Bool()
-  val roqIdx = UInt(RoqIdxWidth.W)
+  val roqIdx = UInt(ExtendedRoqIdxWidth.W)
   val freelistAllocPtr = UInt(PhyRegIdxWidth.W)
 }
 

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 
-
+// A "just-enough" Roq
 class Roq extends XSModule with NeedImpl {
   val io = IO(new Bundle() {
     val brqRedirect = Input(Valid(new Redirect))
@@ -17,7 +17,7 @@ class Roq extends XSModule with NeedImpl {
 
   val microOp = Reg(Vec(RoqSize, new MicroOp))
   // val brMask = Reg(Vec(RoqSize, UInt(BrqSize.W)))
-  val valid = RegInit(VecInit(List.fill(RoqSize)false.B))
+  val valid = RegInit(VecInit(List.fill(RoqSize)(false.B)))
   val writebacked = Reg(Vec(RoqSize, Bool()))
   val redirect = Reg(Vec(RoqSize, new Redirect))
   val isMMIO = Reg(Vec(RoqSize, Bool()))//for debug
@@ -25,40 +25,79 @@ class Roq extends XSModule with NeedImpl {
 
   val ringBufferHeadExtended = RegInit(0.U(ExtendedRoqIdxWidth.W))
   val ringBufferTailExtended = RegInit(0.U(ExtendedRoqIdxWidth.W))
-  val ringBufferHead = ringBufferHead(RoqIdxWidth-1,0)
-  val ringBufferTail = ringBufferTail(RoqIdxWidth-1,0)
-  val ringBufferEmpty = ringBufferHead === ringBufferTail && ringBufferHead(RoqIdxWidth)===ringBufferTail(RoqIdxWidth)
-  val ringBufferEmpty = ringBufferHead === ringBufferTail && ringBufferHead(RoqIdxWidth)=/=ringBufferTail(RoqIdxWidth)
+  val ringBufferWalkExtended = Reg(UInt(ExtendedRoqIdxWidth.W))
+  val ringBufferWalkTarget = Reg(UInt(ExtendedRoqIdxWidth.W))
+  val ringBufferHead = ringBufferHeadExtended(RoqIdxWidth-1,0)
+  val ringBufferTail = ringBufferTailExtended(RoqIdxWidth-1,0)
+  val ringBufferWalk = ringBufferWalkExtended(RoqIdxWidth-1,0)
+  val ringBufferEmpty = ringBufferHead === ringBufferTail && ringBufferHeadExtended(RoqIdxWidth)===ringBufferTailExtended(RoqIdxWidth)
+  val ringBufferFull = ringBufferHead === ringBufferTail && ringBufferHeadExtended(RoqIdxWidth)=/=ringBufferTailExtended(RoqIdxWidth)
   val ringBufferAllowin = !ringBufferFull 
 
+  val s_idle :: s_walk :: Nil = Enum(2)
+  val state = RegInit(s_idle)
+
   // Dispatch
   for(i <- 0 until RenameWidth){
-    when(dp1Req(i).fire()){
-      microOp(ringBufferHead+i) := io.dp1Req(i).bits
-      valid(ringBufferHead+i) := true.B
+    when(io.dp1Req(i).fire()){
+      microOp(ringBufferHead+i.U) := io.dp1Req(i).bits
+      valid(ringBufferHead+i.U) := true.B
     }
-    io.dp1Req(i).ready := ringBufferAllowin && !vaild(ringBufferHead+i)
-    io.roqIdxs(i) := ringBufferHeadExtended+i
+    io.dp1Req(i).ready := ringBufferAllowin && !valid(ringBufferHead+i.U) && state === s_idle
+    io.roqIdxs(i) := ringBufferHeadExtended+i.U
+  }
+  val validDispatch = VecInit((0 until CommitWidth).map(i => io.dp1Req(i).fire())).asUInt
+  when(validDispatch.orR){
+    ringBufferHeadExtended := ringBufferHeadExtended + PopCount(validDispatch)
   }
 
   // Writeback
   for(i <- 0 until exuConfig.ExuCnt){
-    when(exeWbResults(i).fire()){
+    when(io.exeWbResults(i).fire()){
       writebacked(io.exeWbResults(i).bits.uop.roqIdx) := true.B
     }
   }
 
-  // Commit
-  // TODO
-  // for(i <- 0 until CommitWidth){
-  //   io.commits.valid := valid(ringBufferTail+i) && writebacked(ringBufferTail+i)
-  //   io.commits.bits.uop := microOp(ringBufferTail+i)
-  //   io.commits.bits.isWalk := DontCare //TODO
-  // }
-  // io.redirect := DontCare //TODO
-  // io.redirect.valid := false.B //TODO
+  // Commit uop to Rename
+  for(i <- 0 until CommitWidth){
+    when(state === s_idle){
+      io.commits(i).valid := valid(ringBufferTail+i.U) && writebacked(ringBufferTail+i.U)
+      io.commits(i).bits.uop := microOp(ringBufferTail+i.U)
+      when(valid(ringBufferTail+i.U)){valid(ringBufferTail+i.U) := false.B}//FIXIT
+    }.otherwise{//state === s_walk
+      io.commits(i).valid := valid(ringBufferWalk+i.U) && writebacked(ringBufferWalk+i.U)
+      io.commits(i).bits.uop := microOp(ringBufferWalk+i.U)
+      valid(ringBufferWalk+i.U) := false.B
+    }
+    io.commits(i).bits.isWalk := state === s_walk
+  }
+
+  val validCommit = VecInit((0 until CommitWidth).map(i => io.commits(i).valid)).asUInt
+  when(state === s_idle){
+    ringBufferTailExtended := ringBufferTailExtended + PopCount(validCommit)
+  }
+
+  val walkFinished = (0 until CommitWidth).map(i => (ringBufferWalk + i.U) === ringBufferWalkTarget).reduce(_||_)
+
+  when(state===s_walk){
+    //exit walk state when all roq entry is commited
+    when(walkFinished){
+      state := s_idle
+    }
+    ringBufferWalkExtended := ringBufferWalkExtended + CommitWidth.U
+    // Debug(){
+      printf("[ROQ] rolling back: head %d tail %d walk %d\n", ringBufferHead, ringBufferTail, ringBufferWalk)
+    // }
+  }
 
-  // Flush
-  // TODO
+  when(io.brqRedirect.valid){
+    state := s_walk
+    ringBufferWalkExtended := io.brqRedirect.bits.roqIdx
+    ringBufferWalkTarget := ringBufferHeadExtended
+    ringBufferHeadExtended := io.brqRedirect.bits.roqIdx
+  }
 
+  // roq redirect only used for exception
+  io.redirect := DontCare //TODO
+  io.redirect.valid := false.B //TODO
 }