- 22 10月, 2021 2 次提交
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由 William Wang 提交于
* mem: support ld-ld violation check * mem: do not fast wakeup if ld vio check failed * mem: disable ld-ld vio check after core reset
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由 Yinan Xu 提交于
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- 21 10月, 2021 1 次提交
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由 happy-lx 提交于
add mmu's asid support. 1. put asid inside sram (if the entry is sram), or it will take too many sources. 2. when sfence, just flush it all, don't care asid. 3. when hit check, check asid. 4. when asid changed, flush all the inflight ptw req for safety 5. simple asid unit test: asid 1 write, asid 2 read and check, asid 2 write, asid 1 read and check. same va, different pa * ASID: make satp's asid bits configurable to RW * use AsidLength to control it * ASID: implement asid refilling and hit checking * TODO: sfence flush with asid * ASID: implement sfence with asid * TODO: extract asid from SRAMTemplate * ASID: extract asid from SRAMTemplate * all is down * TODO: test * fix write to asid * Sfence: support rs2 of sfence and fix Fence Unit * rs2 of Sfence should be Reg and pass it to Fence Unit * judge the value of reg instead of the index in Fence Unit * mmu: re-write asid now, asid is stored inside sram, so sfence just flush it it's a complex job to handle the problem that asid is changed but no sfence.vma is executed. when asid is changed, all the inflight mmu reqs are flushed but entries in storage is not influenced. so the inflight reqs do not need to record asid, just use satp.asid * tlb: fix bug of refill mask * ci: add asid unit test Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 30 9月, 2021 1 次提交
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由 Jiawei Lin 提交于
* Refactor cache params * L2: support multi-bank * fix l2 size * remove 'IgnoreNode' * bump difftest and huancun
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- 28 9月, 2021 1 次提交
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由 Yinan Xu 提交于
* rename Roq to Rob * remove trailing whitespaces * remove unused parameters
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- 19 9月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds load balance strategy in issue selection logic for reservation stations. Previously we have a load balance option in ExuBlock, but it cannot work if the function units have feedbacks to RS. In this commit it is removed. This commit adds a victim index option for oldestFirst. For LOAD, the first issue port has better performance and thus we set the victim index to 0. For other function units, we use the last issue port.
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- 11 9月, 2021 1 次提交
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由 Lemover 提交于
* mmu.l2tlb: add object TimeOutAssert * mmu.l2tlb: add TimeOutAssert to Repeater * mmu.l2tlb: cut down mem req buffer from 8 ptes to 1 pte each * util: move some utils from MMUBundle to utils
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- 05 9月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds assertion in MaskData to check the width of mask and data. When the width of mask is smaller than the width of data, (~mask & data) and (mask & data) will always clear the upper bits of the data. This usually causes unexpected behavior. This commit adds explicit width declarations where MaskData is used.
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- 02 9月, 2021 1 次提交
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由 Lemover 提交于
* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)" This reverts commit b052b972. * fu: remove unused import * mmu.tlb: 2 load/store pipeline has 1 dtlb * mmu: remove btlb, the l1-tlb * mmu: set split-tlb to 32 to check perf effect * mmu: wrap tlb's param with TLBParameters * mmu: add params 'useBTlb' dtlb size is small: normal 8, super 2 * mmu.tlb: add Bundle TlbEntry, simplify tlb hit logic(coding) * mmu.tlb: seperate tlb's storage, relative hit/sfence logic tlb now supports full-associate, set-associate, directive-associate. more: change tlb's parameter usage, change util.Random to support case that mod is 1. * mmu.tlb: support normalAsVictim, super(fa) -> normal(sa/da) be carefull to use tlb's parameter, only a part of param combination is supported * mmu.tlb: fix bug of hit method and victim write * mmu.tlb: add tlb storage's perf counter * mmu.tlb: rewrite replace part, support set or non-set * mmu.tlb: add param outReplace to receive out replace index * mmu.tlb: change param superSize to superNWays add param superNSets, which should always be 1 * mmu.tlb: change some perf counter's name and change some params * mmu.tlb: fix bug of replace io bundle * mmu.tlb: remove unused signal wayIdx in tlbstorageio * mmu.tlb: separate tlb_ld/st into two 'same' tlb * mmu.tlb: when nWays is 1, replace returns 0.U before, replace will return 1.U, no influence for refill but bad for perf counter * mmu.tlb: give tlb_ld and tlb_st a name (in waveform)
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- 30 8月, 2021 1 次提交
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由 Jiawei Lin 提交于
* bump chisel to 3.5 * Remove deprecated 'toBool' && disable tl monitor * Update RocketChip / Re-enable TLMonitor * Makefile: remove '--infer-rw'
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- 16 8月, 2021 2 次提交
- 14 8月, 2021 1 次提交
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由 zoujr 提交于
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- 24 7月, 2021 1 次提交
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由 Yinan Xu 提交于
XiangShan is jointly released by ICT and PCL.
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- 17 7月, 2021 1 次提交
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由 Yinan Xu 提交于
* better select policy timing * unified RS enqueue ports for 4 ALUs * wrap imm extractor into a module * backend,rs: wrap dataArray in RawDataModuleTemplate * should only bypass data between the same addr when allocate.valid
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- 08 7月, 2021 1 次提交
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由 Yinan Xu 提交于
* better select policy timing * unified RS enqueue ports for 4 ALUs * wrap imm extractor into a module * backend,rs: wrap dataArray in RawDataModuleTemplate * should only bypass data between the same addr when allocate.valid
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- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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- 30 4月, 2021 2 次提交
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由 William Wang 提交于
* emu: add --no-perf-counter option Now perf counter result print will no longer be controlled by --log-begin / --log-end * emu: add --force-dump-result option This option will override log_end to -1 when simulation finishs. --no-perf-counter option is removed.
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由 Yinan Xu 提交于
In this commit, we add support for using DPI-C calls to replace DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to be ignored or bypassed. Configurations are controlled by useFakeDCache, useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache. However, some configurations may not work correctly.
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- 21 4月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 19 4月, 2021 1 次提交
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由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 05 4月, 2021 1 次提交
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由 ljw 提交于
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- 01 4月, 2021 1 次提交
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由 Yinan Xu 提交于
* Add ResetRegGen module to generate reset signals for different modules To meet physical design requirements, reset signals for different modules need to be generated respectively. This commit adds a ResetRegGen module to automatically generate reset registers and connects different reset signals to different modules, including l3cache, l2cache, core. L1plusCache, MemBlock, IntegerBlock, FloatBlock, CtrlBlock, Frontend are reset one by one.
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- 30 3月, 2021 2 次提交
- 25 3月, 2021 4 次提交
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由 Allen 提交于
XSPerfAccumulate: sum up performance values. XSPerfHistogram: count the occurrence of performance values, split them into bins, so that we can estimate their distribution. XSPerfMax: get max of performance values.
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由 Allen 提交于
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由 Allen 提交于
Now we can put a performance value into several bins and count them. In this way, we can get a distribution of this performance value.
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers * Ftq: bypass 'commit state' to fix dequeue bug * perf: uptimize perf-cnt in ctrlblock & ftq * perf: fix compilation problem in ftq * perf: remove duplicate perf-cnt * perf: calcu extra walk cycle exceeding frontend flush bubble * Revert "perf: calcu extra walk cycle exceeding frontend flush bubble" This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70. * perf: add perf-cnt for ifu * perf: add perf-cnt for rs * RS: optimize numExist signal * RS: fix some typo * perf: add QueuePerf util to monitor usage info of queues * perf: remove some duprecate perfcnt
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- 13 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 11 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 10 3月, 2021 1 次提交
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由 Steve Gou 提交于
previously the biggest problem was using '+' instead of '+&' to do sums
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- 09 3月, 2021 1 次提交
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由 Jay 提交于
* L1I/L1+: Add performance counters for each way. * Replacement: fix that lfsr always changes in random.
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- 06 3月, 2021 1 次提交
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由 Jay 提交于
* Replacement: fix way method bugs We do state change when calling way method, but in lack of a signal to inform whether it is necessary to do state change, this might cause problem. * ICache: use new replacement method * L1plusCache: change replacement method * L1plusCache: add performance counters. * L1plusCache: fix performance bug. ICache miss penalty increases because that we miss the access method in L1plusCache for replacement :)
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- 04 3月, 2021 1 次提交
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由 Jay 提交于
* Replacement: change state in way method. * State change is also needed when miss occurs, otherwise we will choose a way that has been just refilled into cache as the victim. * Optimize ctrlblock timing (#620) * CtrlBlock: delay exception flush for 1 cycle * CtrlBlock: delay load replay for 1 cycle * roq: delay wb from exu for one clock cycle to meet timing * CtrlBlock: fix pipeline bug between decode and rename Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> * L1plusCache: use plru replacement policy. * ICache: fix mmio bugs 1. MMIO cut helper uses packet align logic 2. still send req to uncache when flush * ICache: change packet from mmio use packet align as the mem * IntrUncache: fix state bug state will change into s_invalid and get stuck * fix Registers that not being initiated
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- 28 2月, 2021 2 次提交
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers
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由 William Wang 提交于
* WaitTable: add waittable framework * WaitTable: get replay info from RedirectGenerator * StoreQueue: maintain issuePtr for load rs * RS: add loadWait to rs (only for load Unit's rs) * WaitTable: fix update logic * StoreQueue: fix issuePtr update logic * chore: set loadWaitBit in ibuffer * StoreQueue: fix issuePtrExt update logic Former logic does not work well with mmio logic We may also make sure that issuePtrExt is not before cmtPtrExt * WaitTable: write with priority * StoreQueue: fix issuePtrExt update logic for mmio * chore: fix typos * CSR: add slvpredctrl * slvpredctrl will control load violation predict micro architecture * WaitTable: use xor folded pc to index waittable Co-authored-by: NZhangZifei <1773908404@qq.com>
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- 25 2月, 2021 1 次提交
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由 wangkaifan 提交于
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- 24 2月, 2021 2 次提交
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由 wangkaifan 提交于
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由 wangkaifan 提交于
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