- 25 7月, 2021 3 次提交
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由 Lingrui98 提交于
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由 Lingrui98 提交于
1. taken mask should consider corresponding valid bit 2. FetchWidth is in 4 bytes
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由 Lingrui98 提交于
1. previously we flush ftq status at stage2Redirect, but use stage3Redirect to flush ifu, when stage3Redirect comes with pdWb, ifuWbPtr would be falsely increased 2. toBpuUpdate.valid should only assign when do_commit
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- 24 7月, 2021 4 次提交
- 23 7月, 2021 2 次提交
- 21 7月, 2021 1 次提交
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由 zoujr 提交于
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- 20 7月, 2021 5 次提交
- 19 7月, 2021 6 次提交
- 18 7月, 2021 5 次提交
- 17 7月, 2021 14 次提交
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由 zoujr 提交于
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由 zoujr 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
* Now can pass compiling. [WIP] comment out-of-date code in frontend [WIP] move NewFtq to xiangshan.frontend and rename class to Ftq Ibuffer: update sigal names for new IFU [WIP] remove redundant NewFrontend [WIP] set entry_fetch_status to f_sent once send req to buf Fix syntax error in IFU Fix syntax error in IFU/ICache/Ibuffer [WIP] indent fix in ftq BPU: Move GlobalHistory define from IFU.scala to BPU.scala [WIP] fix some compilation errors BPU: Remove HasIFUConst and move some bundles from BPU.scala to frontendBundle.scala [WIP] fix some compilation errors [WIP] rename ftq-bpu ios [WIP] recover some const definitions [WIP] fix some compilation errors [WIP]connect some IOs in frontend BPU: fix syntax error [WIP] fix compilation errors in predecode BPU: fix RAS syntax error [WIP] add some simulation perf counters back BPU: Remove numBr redefine in ubtb and bim
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由 Lingrui98 提交于
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由 Lemover 提交于
* CSR: add csr access check for mstatus.tvm tvm: trap virtual Memory. when tvm is set, r/w the satp in S-mode will raise illegal-instr * Fence: add tvm check that may disallow sfence when tvm is set and at s-mode, sfence.vma will raise illegal-instr
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由 Yinan Xu 提交于
* change the number of function units in MinimalConfig * remove some hard-wired values
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由 Yinan Xu 提交于
This commit adds support for a parameterized scheduler. A scheduler can be parameterized via issue and dispatch ports. Note: other parameters have not been tested.
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由 Yinan Xu 提交于
This commit adds an non-parameterized scheduler containing all reservation stations. Now IntegerBlock, FloatBlock, MemBlock contain only function units. The Schduler connects dispatch with all function units. Parameterization to be added later.
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由 Jiawei Lin 提交于
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由 Lemover 提交于
* PTW: Repeater support multi req by RRArbiter * ptw: add parameter to choose repeater and filter(default) simple ci test show that: the filter is critical for perf like mcf(5m): old ptw:2.38 new ptw with repeater: 2.41 new ptw with filter: 2.58
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由 Yinan Xu 提交于
* better select policy timing * unified RS enqueue ports for 4 ALUs * wrap imm extractor into a module * backend,rs: wrap dataArray in RawDataModuleTemplate * should only bypass data between the same addr when allocate.valid
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