Log and waveform are controlled by cpu clock cycles instead of simulated cycles.
When loading from snapshot and assert stops the simulation, we cannot know the accurate cpu cycle.
To determine the actual cpu clock, we print cycleCnt when loading from snapshot.

--threads 1 can delay assert to the end of each cycle and produce the entire log

have not connected the performance counters to CSR

emu: asynchronous reset ram

We need to asynchronous reset the system when reset is true.
In verilator model, it's done by always resetting the external devices when reset is true.
After the reset signal is released, we call init once for external devices to make sure they are correctly reset.

Update chisel to 3.4.0

Revert "mem,lsq: improve tailPtr update logic"

This reverts commit a0ffea30.

MissQueue: for read hit, remember to set new_coh in decide_next_state

L2 support outer probe

optimize dispatch queue: support dequeue when store writes back

Case: vvvdvvvddddd
            ^    ^
If the leftmost instruction is a store and it writebacks, these instructions won't be replayed.
However, we cannot move headPtr to the left hand side of the dispatchPtr since there're still
instructions that have not been dispatched to issue queues.
In this case, we only remove the instructions before dispatchPtr.
Moving headPtr in case of store writeback only affects performance, since instructions leave dispatch queue when they commit.