This commit adds blocking logic for instructions when they enter
dispatch queues. If previous instructions have exceptions, any
following instructions should be enter dispatch queue.

Consider the following case. If uop(0) has an exception and is a load.
If uop(1) does not have an exception and is a load as well. Then the
allocation logic in dispatch queue will allocate an entry for both
uop(0) and uop(1). However, uop(0) will not set enq.valid and leave
the entry in dispatch queue empty. uop(1) will be allocated in dpq.
In dispatch queue, pointers are updated according to the real number
of instruction enqueue, which is one. While the second is actually
allocated. This causes errors.

* bump huancun

* Fix probe BtoB
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send full L1CacheErrorInfo to CSR

* icache: provide cache error info for CSR

* dcache: force resp hit if tag ecc error happens

* mem: reorg l1 cache error report path

Now dcache tag error will force trigger a hit

* dcache: fix readline ecc check error

* dcache: mainpipe will not be influenced by tag error

* dcache: fix data ecc check error

* dcache: if coh state is Nothing, do not raise error
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>

add buffer at tl pma

For 0:x and 1:x, 1:x should be after 0:x.

Valid should be set to true after atomic.exception.valid and cleared
after redirect is valid.

If s2_data_invalid and s2_ldld_violation happens together, enter
s2_ldld_violation workflow.

Note:
ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

Exception address is used serveral cycles after flush. We delay it
by more cycles to ensure its flush safety.

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

* mem: optimize missq reject to lq timing

DCache replay request is quite slow to generate, as it need to compare
load address with address in all valid miss queue entries.

Now we delay the usage of replay request from data cache.
Now replay request will not influence normal execution flow until
load_s3 (1 cycle after load_s2, load result writeback to RS).

Note1: It is worth mentioning that "select refilling inst for load
writeback" will be disabled if dcacheRequireReplay in the
last cycle.

Note2: ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

* dcache: compare probe block addr instead of full addr

* difftest: bump difftest to support --no-diff test

* ci: add cacheoptest test (--no-diff)

* dcache: use sram to build ecc array

* MainPipe: latch s1_encTag to last until s1_fire
Authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>

This commit adds an LsqEnqCtrl module to add one more clock cycle
between dispatch and load/store queue.

LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter.
They are used to determine whether load/store queue can accept new
instructions. After that, instructions are sent to load/store queue.
This module decouples queue allocation and real enqueue.

Besides, uop storage in load/store queue are optimized. In dispatch,
only robIdx is required. Other information is naturally conveyed in
the pipeline and can be stored later in load/store queue if needed.
For example, exception vector, trigger, ftqIdx, pdest, etc are
unnecessary before the instruction leaves the load/store pipeline.

This commit removed PriorityEncoder in sbuffer enq path. It should improve sbuffer enqueue timing.

* pma: allow r/w priv for l3-cache op mmio space

* bump huancun

* bump huancun

* bump huancun

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data stores in L2)

* Ftq: add prefetchPtr and prefetch interface

* Fix IPrefetch PMP Port preempting problem

* Fix merge conflict

Refactor Trigger

* ICache: raise access fault when L2 send corrupt

* ICache: add ECC error connection

* chores: add comments and code clean-up

* ICache: raise AF when Meta/Data Parity wrong

* Update Frontend.scala

* dcache: let ecc error and l2 corrupt raise load af

If CSR.smblockctl.cache_error_enable is disabled, ecc error and l2 corrupt
will not raise any exception.

* mem: enable cache error by default

* mem: support store ecc check, add ecc error csr

Support store / atom ecc check (early version)
Add ecc error csr to distingush ecc error and other access fault

Timing opt and unit tests to be added.

* memblock: regnext ptw's resp

* pmp: timing optimization from tlb.sram.ppn to pmp, add static pmp check

long latency: tlb's sram may be slow to gen ppn, ppn to pmp may be
long latency.
Solution: add static pmp check.

Fatal problem: pmp grain is smalled than TLB pages(4KB, 2MB, 1GB)
Solution: increase pmp'grain to 4K, for 4K entries, pre-check pmp and
store the result into tlb storage. For super pages, still dynamic check
that translation and check.

* pmp: change pmp grain to 4KB, change pma relative init config

* bump ready-to-run, update nemu so for pmp grain

* bump ready-to-run, update nemu so for pmp grain again

  update pmp unit test. The old test assumes that pmp grain is less than 512bit.

* Change L3 to 6MB

* Bump huancun

We have singlestep already so triggers do not need to hit after inst commits

* dcache: fix bug in ecc check

* dcache: remove redundant ecc array

* CacheInstruction: fix typo

* dcache: fix bugs in cache instruction on ecc

* MetaArray: wrap ecc array as a single module

* fix invalidTakenFault use wrong seqTarget

* IFU: fix oversize bug

* ctrl: mark all flushes as level.flush for frontend

This commit changes how flushes behave for frontend.

When ROB commits an instruction with a flush, we notify the frontend
of the flush without the commit.

Flushes to frontend may be delayed by some cycles and commit before
flush causes errors. Thus, we make all flush reasons to behave the
same as exceptions for frontend, that is, RedirectLevel.flush.

* IFU: exclude lastTaken situation when judging beyond fetch
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

* Debug Mode: support basic difftest with spike

* Debug Mode: fix some bugs

Bugs fixed are:
1. All interrupts and exceptions cause debug mode to enter park loop
2. Debug interrupt ignored due to flushPipe

* mmpma: fix read/write io decoupled logic

* pma: fix init pma config