* Update mill and rocket-chip

* [WIP] auto generate dts by diplomacy

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more configurable style.

The new RS has not finished.
- Support only integer instructions
- Feedback from load/store instructions is not supported
- Fast wakeup for multi-cycle instructions is not supported
- Submodules are refined later

* RS: use wakeup signals from arbiter.out

* RS: support feedback and re-schedule when needed

For load and store reservation stations, the instructions that left RS before may be
replayed later.

* test,vcs: check difftest_state and return on nemu trap instructions

* backend,RS: support floating-point operands and delayed regfile read for store RS

This commit adds support for floating-point instructions in reservation stations.
Beside, currently fp data for store operands come a cycle later than int data. This
feature is also supported.

Currently the RS should be ready for any circumstances.

* rs,status: don't trigger assertions when !status.valid

* test,vcs: add +workload option to specify the ram init file

* backend,rs: don't enqueue when redirect.valid or flush.valid

* backend,rs: support wait bit that instruction waits until store issues

This commit adds support for wait bit, which is mainly used in load and
store reservation stations to delay instruction issue until the corresponding
store instruction issued.

* backend,RS: optimize timing

This commit optimizes BypassNetwork and PayloadArray timing.

- duplicate bypass mask to avoid too many FO4
- use one-hot vec to get read data

* PTW: add ptw multi-processing graph

* [WIP] PTW: try to add miss queue, failed for complexity and not very useful

* [WIP] PTW: rewrite ptw for multi req support

* PTW: remove some assert, fix level init bug

* PTW: itlb has highter priority than dtlb

* PTW: fix bug that mix cache's resp logic

* PTW: fix stupid bug that mix .U and .W

* PTW: replay will not be blocked if fsm empty

* PTW: miss queue req may return miss queue

In the before design, only miss queue req can go into
fsm, and would not be blocked.
Now, to simplify design, miss queue req are just the
same with new req, may blocked, going to fsm or miss queue.

* PTW: fix ptw filter iss valid bug

* PTW.fsm: fix bug that should not mem.req when sfenceLatch

* PTW: fix ptw sfenceLatch's bug

* PTW: add some perf counters

* PTW: fix bug in filter enq ptr logic

* PTW: fix bug of sfence in ptw

* test: add current branch to ci-test, tmp

* PTW: fix bug of cache's hit logic and fsm's pf

* PTW: fix bug of filter's enq and block* signal

* PTW: fix bug of filter's pteResp filter

* PTW: add some assert of filter's counter

* PTW: fix bug of filter's enq logic

* PTW: set PTWMSHRSIZE 16

* PTW: fix naive perf counter's bug

* PTW: set PTWMSHRSIZE 8

* PTW: set PTWMSHRSIZE 32

* Revert "PTW: set PTWMSHRSIZE 32"

This reverts commit fd3981ae8bbb015c6cd398c4db60486d39fc92ef.

* Revert "test: add current branch to ci-test, tmp"

This reverts commit 8a7a8a494d5c05789e05a385a9fc7791a8ffef2f.

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to
be ignored or bypassed. Configurations are controlled by useFakeDCache,
useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache.
However, some configurations may not work correctly.

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* Add ResetRegGen module to generate reset signals for different modules

To meet physical design requirements, reset signals for different modules
need to be generated respectively. This commit adds a ResetRegGen module
to automatically generate reset registers and connects different reset
signals to different modules, including l3cache, l2cache, core.
L1plusCache, MemBlock, IntegerBlock, FloatBlock, CtrlBlock, Frontend are
reset one by one.

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware performance counters

* MainPipe/LoadPipe: disable fast wakeup when data sram is to be written

* RS: set EnableLoadFastWakeUp true

* LoadPipe: add perf cnt for disabling ld fast wakeup speculatively

* MainPipe: disable ld fast wakeup when s1 read data in MainPipe
Co-authored-by: Nzhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>

* LoadUnit: generate fastUop in load_s1

* RS/Load: add load to fast wakeup when cache hit, while maintain its slow

* RS: remove legacy assert that doesn't work for load has fast and slow

* LoadUnit: fix bug that fastUops's valid forgets load_s1.io.in.valid

* MemBlock: fix bug of loadUnit's fast and slow connect

IPC of coremark 10 cycles raise from 1.63 to 1.70

* RS: RegNext srcUpdate to use it at next cycle

* RS: add param EnableLoadFastWakeUp and set default to false
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* MySoc: verilog top

* MySoc: connect mmio

* MySoc: fix some bugs

* wip

* TopMain: remove to top

* WIP: add dma port

* Update XSTop for FPGA/ASIC platform

* Top: add rocket-chip source

* Append SRAM to generated verilog
Co-authored-by: NLinJiawei <linjiav@outlook.com>

This reverts commit 1c6ad6d0.

* Replacement: fix way method bugs

We do state change when calling way method, but in lack of a signal to
inform whether it is necessary to do state change, this might cause
problem.

* ICache: use new replacement method

* L1plusCache: change replacement method

* L1plusCache: add performance counters.

* L1plusCache: fix performance bug.

ICache miss penalty increases because that we miss the access method
in L1plusCache for replacement :)

* xscore: remove reg and logic in xscore top module

* XSCore: remove logic in top module

* Fp/Int block: fix write back bug
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

* RS: optimize numExist signal

* RS: fix some typo

* RS: optimize deq logic for block-nonfeedback rs

separate ecc correction from the critical path of dcache resp

* DCache: remove ecc to improve timing.

* MissQueue: refill_arb change RRArbiter to Arbiter to improve timing.

* WaitTable: add waittable framework

* WaitTable: get replay info from RedirectGenerator

* StoreQueue: maintain issuePtr for load rs

* RS: add loadWait to rs (only for load Unit's rs)

* WaitTable: fix update logic

* StoreQueue: fix issuePtr update logic

* chore: set loadWaitBit in ibuffer

* StoreQueue: fix issuePtrExt update logic

Former logic does not work well with mmio logic

We may also make sure that issuePtrExt is not before cmtPtrExt

* WaitTable: write with priority

* StoreQueue: fix issuePtrExt update logic for mmio

* chore: fix typos

* CSR: add slvpredctrl

* slvpredctrl will control load violation predict micro architecture

* WaitTable: use xor folded pc to index waittable
Co-authored-by: NZhangZifei <1773908404@qq.com>

* Backend: fix some bugs related to exu write

* Roq: revert to perv verision

* Fix fp write back bugs