*BPU: move resetVector from IFU to BPU
    *ICache: remove useless `val`s and `def`s in HasICacheParameters
    *IFU: clean up HasIFUConst/Change cut function
    *PreDecode: replace "16"s with "PredictWidth"s

Fix bug that Tage update pc error

and modify some log

br_hit and hist is read at ftq when redirect is sent to bpu

* fix some unconnected wires
* add debug log for ras
* TODO: when predecode detects no-hit returns, we should
  use the result of ras

Fix the bug that Tage use wrong Bim prediction result
Fix the bug that wrong global history was sent to Tage
Fix the bug that sawNTBr and takenOnBr would also be assigned when Ftb not hit
Fix the bug that is_br was not returned in ubtb resp
Remove isMisPred signal in redirect

Fix the bug that the global history was not sended to FTQ
Modifi some logic in TAGE

Add Tage into Composer
Add global history manage logic in BPU
Modify CfiUpdate interface: sawNotTakenBranch -> br_hit

Modify FallThroughAddress to PartialFallThroughAddress in BPU
Fix pftAddr wrong width in TFQ

Fix the bug that pftAddr is not transmitted when ubtb predict not taken
Turn off the random allocation of the allocWay function
Add GTimer in FTBMeta
Add log in Bim.scala

* for packets sent to ifu but not yet written back at replay,
  we still allow them to have predecode mispredict once written
  back from ifu

Fix Bim read idx bug
Remove valids in BranchPredictionResp
Modify out from Decoupled to Output in BasePredictorIO

* jumpOH could have more than one valid

* ifu: f2_redirect should consider successive predecode mispredicts
* ftq: when predicted not taken, cifIndex should be set to PrediectWidth-1