BPU: Add BPU log and fix a ubtb idx bug

src/main/scala/xiangshan/decoupled-frontend/BPU.scala

@@ -259,6 +259,8 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
   val s0_pc = WireInit(resetVector.U)
   val s0_pc_reg = RegInit(resetVector.U)
   val s1_pc = RegEnable(s0_pc, s0_fire)
+  val s2_pc = RegEnable(s1_pc, s1_fire)
+  val s3_pc = RegEnable(s2_pc, s2_fire)
 
   // val s3_gh = predictors.io.out.bits.resp.s3.ghist
   // val final_gh = RegInit(0.U.asTypeOf(new GlobalHistory))
@@ -356,7 +358,7 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
 
   // io.bpu_to_ftq.resp.bits.hit   := predictors.io.out.bits.resp.s3.hit
   // io.bpu_to_ftq.resp.bits.preds := predictors.io.out.bits.resp.s3.preds
-  io.bpu_to_ftq.resp.valid := s3_fire && !io.ftq_to_bpu.redirect.valid
+  io.bpu_to_ftq.resp.valid := s3_valid && !io.ftq_to_bpu.redirect.valid
   io.bpu_to_ftq.resp.bits  := predictors.io.out.resp.s3
   io.bpu_to_ftq.resp.bits.meta  := predictors.io.out.s3_meta
 
@@ -389,6 +391,26 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
   }
 
   if(debug) {
+    XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n")
+    XSDebug(io.ftq_to_bpu.update.valid, p"Update from ftq\n")
+    XSDebug(io.ftq_to_bpu.redirect.valid, p"Redirect from ftq\n")
+
+    XSDebug("[BP0]                 fire=%d                      pc=%x\n", s0_fire, s0_pc)
+    XSDebug("[BP1] v=%d r=%d sr=%d fire=%d             flush=%d pc=%x\n",
+      s1_valid, s1_ready, s1_components_ready, s1_fire, s1_flush, s1_pc)
+    XSDebug("[BP2] v=%d r=%d sr=%d fire=%d redirect=%d flush=%d pc=%x\n",
+    s2_valid, s2_ready, s2_components_ready, s2_fire, s2_redirect, s2_flush, s2_pc)
+    XSDebug("[BP3] v=%d r=%d sr=%d fire=%d redirect=%d flush=%d pc=%x\n",
+    s3_valid, s3_ready, s3_components_ready, s3_fire, s3_redirect, s3_flush, s3_pc)
+    XSDebug("[FTQ] ready=%d\n", io.bpu_to_ftq.resp.ready)
+    XSDebug("resp.s1.preds.target=%x\n", resp.s1.preds.target)
+    XSDebug("resp.s2.preds.target=%x\n", resp.s2.preds.target)
+
+
+    XSDebug(io.ftq_to_bpu.update.valid, io.ftq_to_bpu.update.bits.toPrintable)
+    XSDebug(io.ftq_to_bpu.redirect.valid, io.ftq_to_bpu.redirect.bits.toPrintable)
+
+
     XSPerfAccumulate("s2_redirect", s2_redirect)
   }
 }

src/main/scala/xiangshan/decoupled-frontend/FTB.scala

@@ -59,6 +59,17 @@ class FTBEntry (implicit p: Parameters) extends XSBundle with FTBParams {
 
   def getOffsetVec = VecInit(brOffset :+ jmpOffset)
   def isJal = !isJalr
+
+  override def toPrintable: Printable = {
+    p"-----------FTBEntry----------- " +
+      p"[valid] $valid  " +
+      p"[tag] ${Hexadecimal(tag)} " +
+      (0 until numBr).map( i => p"[br$i]: v=${brValids(i)}, offset=${brOffset(i)}, target=${Hexadecimal(brTargets(i))} ").reduce(_+_) +
+      p"[jmp]: v=${jmpValid}, offset=${jmpOffset}, target=${Hexadecimal(jmpTarget)} " +
+      p"[pgfAddr] ${Hexadecimal(pftAddr)} " +
+      p"isCall=$isCall, isRet=$isRet, isJalr=$isJalr " +
+      p"carry=$carry, oversize=$oversize, last_is_rvc=$last_is_rvc "
+  }
 }
 
 class FTBMeta(implicit p: Parameters) extends XSBundle with FTBParams {
@@ -103,8 +114,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
 
     io.read_pc.ready := ftb.io.r.req.ready
 
-    val read_tag = Reg(UInt(tagSize.W))
-    read_tag := ftbAddr.getTag(io.read_pc.bits)(tagSize-1, 0)
+    val read_tag = RegEnable(ftbAddr.getTag(io.read_pc.bits)(tagSize-1, 0), io.read_pc.valid)
 
     val read_datas = ftb.io.r.resp.data
 
@@ -203,10 +213,10 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
 
   io.out.resp.s3 := RegEnable(io.out.resp.s2, io.s2_fire)
 
-  when(!s2_hit) {
-    io.out.resp.s2.ftb_entry.pftAddr := RegEnable(s1_pc + (FetchWidth*4).U, io.s1_fire)
-  }.otherwise {
+  when(s2_hit) {
     io.out.resp.s2.ftb_entry.pftAddr := RegEnable(ftb_entry.pftAddr, io.s1_fire)
+  }.otherwise {
+    io.out.resp.s2.ftb_entry.pftAddr := RegEnable(s1_pc + (FetchWidth*4).U, io.s1_fire)
   }
 
   // Update logic
@@ -241,15 +251,33 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
     has_update_ptr := has_update_ptr + !u_updated
   }
 
-  XSPerfAccumulate("ftb_first_miss", u_valid && !u_updated && !update.hit)
-  XSPerfAccumulate("ftb_updated_miss", u_valid && u_updated && !update.hit)
+  if (debug) {
+    XSDebug("req_v=%b, req_pc=%x, ready=%b (resp at next cycle)\n", io.s0_fire, s0_pc, ftbBank.io.read_pc.ready)
+    XSDebug("s1_hit=%b, hit_way=%b\n", s1_hit, writeWay.asUInt)
+    XSDebug("taken_mask=%b\n", s1_latch_taken_mask.asUInt)
+    XSDebug("target=%x\n", s1_latch_target)
+
+    XSDebug(ftb_entry.toPrintable)
+    XSDebug("\n")
 
-  XSPerfAccumulate("ftb_read_first_miss", RegNext(io.s0_fire) && !s1_hit && !r_updated)
-  XSPerfAccumulate("ftb_read_updated_miss", RegNext(io.s0_fire) && !s1_hit && r_updated)
+    XSDebug(u_valid, "Update from ftq\n")
+    XSDebug(u_valid, "update_pc=%x, tag=%x, update_write_way=%b\n",
+      update.pc, ftbAddr.getTag(update.pc), u_way_mask)
 
-  XSPerfAccumulate("ftb_read_hits", RegNext(io.s0_fire) && s1_hit)
-  XSPerfAccumulate("ftb_read_misses", RegNext(io.s0_fire) && !s1_hit)
 
-  XSPerfAccumulate("ftb_commit_hits", u_valid && update.hit)
-  XSPerfAccumulate("ftb_commit_misses", u_valid && !update.hit)
+
+
+
+    XSPerfAccumulate("ftb_first_miss", u_valid && !u_updated && !update.hit)
+    XSPerfAccumulate("ftb_updated_miss", u_valid && u_updated && !update.hit)
+
+    XSPerfAccumulate("ftb_read_first_miss", RegNext(io.s0_fire) && !s1_hit && !r_updated)
+    XSPerfAccumulate("ftb_read_updated_miss", RegNext(io.s0_fire) && !s1_hit && r_updated)
+
+    XSPerfAccumulate("ftb_read_hits", RegNext(io.s0_fire) && s1_hit)
+    XSPerfAccumulate("ftb_read_misses", RegNext(io.s0_fire) && !s1_hit)
+
+    XSPerfAccumulate("ftb_commit_hits", u_valid && update.hit)
+    XSPerfAccumulate("ftb_commit_misses", u_valid && !update.hit)
+  }
 }

src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala

@@ -17,8 +17,8 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle {
 
   override def toPrintable: Printable = {
     p"[start] ${Hexadecimal(startAddr)} [pft] ${Hexadecimal(fallThruAddr)}" +
-    p"[tgt] ${Hexadecimal(target)} [ftqIdx] $ftqIdx [jmp] v:${ftqOffset.valid}" +
-    p" offset: ${ftqOffset.bits}\n"
+      p"[tgt] ${Hexadecimal(target)} [ftqIdx] $ftqIdx [jmp] v:${ftqOffset.valid}" +
+      p" offset: ${ftqOffset.bits}\n"
   }
 }
 
@@ -98,10 +98,11 @@ class BranchPrediction(implicit p: Parameters) extends XSBundle with HasBPUConst
   def taken = taken_mask.reduce(_||_) // || (is_jal || is_jalr)
 
   override def toPrintable: Printable = {
-    p"[taken_mask] ${Binary(taken_mask.asUInt)}\n" +
-      p"[is_br] ${Binary(is_br.asUInt)}, [is_jal] ${Binary(is_jal.asUInt)}\n" +
-      p"[is_jalr] ${Binary(is_jalr.asUInt)}, [is_call] ${Binary(is_call.asUInt)}, [is_ret] ${Binary(is_ret.asUInt)}\n" +
-      p"[target] ${Hexadecimal(target)}}, [hit] $hit\n"
+    p"-----------BranchPrediction----------- " +
+      p"[taken_mask] ${Binary(taken_mask.asUInt)} " +
+      p"[is_br] ${Binary(is_br.asUInt)}, [is_jal] ${Binary(is_jal.asUInt)} " +
+      p"[is_jalr] ${Binary(is_jalr.asUInt)}, [is_call] ${Binary(is_call.asUInt)}, [is_ret] ${Binary(is_ret.asUInt)} " +
+      p"[target] ${Hexadecimal(target)}}, [hit] $hit "
   }
 }
 
@@ -119,8 +120,11 @@ class BranchPredictionBundle(implicit p: Parameters) extends XSBundle with HasBP
   val ftb_entry = new FTBEntry() // TODO: Send this entry to ftq
 
   override def toPrintable: Printable = {
-    p"[pc] ${Hexadecimal(pc)} [pft] ${Hexadecimal(ftb_entry.pftAddr)}" +
-    p"[tgt] ${Hexadecimal(preds.target)} [hit] $hit\n"
+    p"-----------BranchPredictionBundle----------- " +
+      p"[pc] ${Hexadecimal(pc)} [hit] $hit " +
+      p"[ghist] ${Binary(ghist.predHist)}  " +
+      preds.toPrintable +
+      ftb_entry.toPrintable
   }
 }
 
@@ -136,6 +140,32 @@ class BranchPredictionUpdate(implicit p: Parameters) extends BranchPredictionBun
   val false_hit = Bool()
   val new_br_insert_pos = Vec(numBr, Bool())
   // val ghist = new GlobalHistory() This in spec_meta
+
+  override def toPrintable: Printable = {
+    p"-----------BranchPredictionUpdate----------- " +
+      p"[mispred_mask] ${Binary(mispred_mask.asUInt)} [false_hit] ${Binary(false_hit)}" +
+      p"[new_br_insert_pos] ${Binary(new_br_insert_pos.asUInt)} " +
+      super.toPrintable +
+      p"\n"
+  }
+
 }
 
-class BranchPredictionRedirect(implicit p: Parameters) extends Redirect with HasBPUConst {}
+class BranchPredictionRedirect(implicit p: Parameters) extends Redirect with HasBPUConst {
+  override def toPrintable: Printable = {
+    p"-----------BranchPredictionRedirect----------- " +
+      p"-----------cfiUpdate----------- " +
+      p"[pc] ${Hexadecimal(cfiUpdate.pc)} " +
+      p"[predTaken] ${cfiUpdate.predTaken}, [taken] ${cfiUpdate.taken}, [isMisPred] ${cfiUpdate.isMisPred} " +
+      p"[target] ${cfiUpdate.target} " +
+      p"------------------------------- " +
+      p"[roqPtr] f=${roqIdx.flag} v=${roqIdx.value} " +
+      p"[ftqPtr] f=${ftqIdx.flag} v=${ftqIdx.value} " +
+      p"[ftqOffset] ${ftqOffset} " +
+      p"[level] ${level}, [interrupt] ${interrupt} " +
+      p"[stFtqIdx] f=${stFtqIdx.flag} v=${stFtqIdx.value} " +
+      p"[stFtqOffset] ${stFtqOffset} " +
+      p"\n"
+
+  }
+}

src/main/scala/xiangshan/decoupled-frontend/uBTB.scala

@@ -28,7 +28,7 @@ trait MicroBTBParams extends HasXSParameter {
   val numWays = 16
   val tagSize = 20
   val lowerBitSize = 20
-  val untaggedBits = log2Up(PredictWidth) + instOffsetBits
+  val untaggedBits = instOffsetBits
 }
 
 @chiselName
@@ -282,6 +282,18 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
   banks.update_write_data.bits := update_write_datas
   banks.update_taken_mask := u_taken_mask
 
-  XSPerfAccumulate("ubtb_read_hits", RegNext(io.s1_fire) && banks.read_hit)
-  XSPerfAccumulate("ubtb_read_misses", RegNext(io.s1_fire) && !banks.read_hit)
+  if (debug) {
+    XSDebug("req_v=%b, req_pc=%x, hit=%b\n", io.s1_fire, s1_pc, banks.read_hit)
+    XSDebug("target=%x, taken_mask=%b\n", io.out.resp.s1.preds.target, read_resps.taken_mask.asUInt)
+
+    XSDebug(u_valid, "Update from ftq\n")
+    XSDebug(u_valid, "update_pc=%x, tag=%x\n", u_pc, getTag(u_pc))
+    XSDebug(u_valid, "taken_mask=%b, brValids=%b, jmpValid=%b\n",
+      u_taken_mask.asUInt, update.preds.is_br.asUInt, update.preds.is_jal || update.preds.is_jalr)
+
+    XSPerfAccumulate("ubtb_read_hits", RegNext(io.s1_fire) && banks.read_hit)
+    XSPerfAccumulate("ubtb_read_misses", RegNext(io.s1_fire) && !banks.read_hit)
+  }
+
+
 }