* should be compatible with single core difftest framework

This effectly reduces the number of bus data wires from 256 * 3 to 256 * 2.

Use DataDontCareNode to add DontCare to the tilelink nodes you are
interested in.

1. duplicated connection to cache node enables banking
2. properly place filter node in manager side
 (then InclusiveCahce can fix the banked address)
3. use out-of-box bankbinder utility

* urge tests for external interrupt

Now, they are still 64bit(negotiated by diplomacy), since AXI4RAM is 64bit wide.
Considering changing AXI4RAM to 64bit.

The goal of this commit is to remove 'implict val p: XSConfig' in our code becasue it's inconvenient

Use fake Icache to fetch 8 instructions per cycle.