- 01 3月, 2021 2 次提交
- 28 2月, 2021 16 次提交
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由 Lemover 提交于
* TLB: add more tlb and ptw's perf counter * TLB: change perf count signal name(rm module name)
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由 Yinan Xu 提交于
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由 zoujr 提交于
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由 ljw 提交于
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由 Yinan Xu 提交于
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由 ljw 提交于
* Ftq: use reg instead 4r_sram * Ftq: use delayed value form exu output
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由 zoujr 提交于
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由 zoujr 提交于
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers
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由 ljw 提交于
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由 zoujr 提交于
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由 zoujr 提交于
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由 William Wang 提交于
* WaitTable: add waittable framework * WaitTable: get replay info from RedirectGenerator * StoreQueue: maintain issuePtr for load rs * RS: add loadWait to rs (only for load Unit's rs) * WaitTable: fix update logic * StoreQueue: fix issuePtr update logic * chore: set loadWaitBit in ibuffer * StoreQueue: fix issuePtrExt update logic Former logic does not work well with mmio logic We may also make sure that issuePtrExt is not before cmtPtrExt * WaitTable: write with priority * StoreQueue: fix issuePtrExt update logic for mmio * chore: fix typos * CSR: add slvpredctrl * slvpredctrl will control load violation predict micro architecture * WaitTable: use xor folded pc to index waittable Co-authored-by: NZhangZifei <1773908404@qq.com>
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由 Steve Gou 提交于
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由 Yinan Xu 提交于
* intWb: set wb.valid when !fpwen to allow writeback if !fpwen and !rfwen * RS: pass ExuConfigs instead of wake-up port number to rs * ci: add mcf, xalancbmk, gcc and namd to CI for performance test * ram: change default dram model to DRAMsim3 model * RS: store's rs's base-src dont care fp wake-up * update default configurations * rs: fix replay delay to avoid deadlock * load: fix tlb feedback * update default configurations
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由 zoujr 提交于
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- 27 2月, 2021 9 次提交
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由 Yinan Xu 提交于
* intWb: set wb.valid when !fpwen to allow writeback if !fpwen and !rfwen * rs: fix replay delay to avoid deadlock * load: fix tlb feedback
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由 zoujr 提交于
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由 Lemover 提交于
* RS: pass ExuConfigs instead of wake-up port number to rs * RS: store's rs's base-src dont care fp wake-up
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Lemover 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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- 26 2月, 2021 4 次提交
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由 ljw 提交于
* Backend: fix some bugs related to exu write * Roq: revert to perv verision * Fix fp write back bugs
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由 William Wang 提交于
* LSQ: use async vaddrModule * StoreQueue: opt mmio writeback valid timing * LSQ: opt vaddr read ptr gen timing * chore: remove unnecessary script
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由 Steve Gou 提交于
* csr: add sbpctrl to control branch predictors * bpu: add dynamic switch to each predictor * csr: change spfctl and sbpctl address * bpu: fix s3 connections Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
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由 zoujr 提交于
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
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- 25 2月, 2021 9 次提交
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由 Steve Gou 提交于
perf: Add perf counters for bpu
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由 zoujr 提交于
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由 zoujr 提交于
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由 Yinan Xu 提交于
Optimize l1plus Cache and L1plus prefetcher timing.
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由 jinyue110 提交于
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由 zoujr 提交于
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由 Yinan Xu 提交于
perf: support pf-cnt dump & clean
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由 jinyue110 提交于
First latch and then decode for timing consideration.
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由 jinyue110 提交于
fix conflict for l1plusprefetcher
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