This reverts commit e100a73b.

* Vaddr gen will be done in L0
* Paddr match & state check will be done in L1
* Data select will be done in L2

* Data select is 1 cycle after SQ writeback, it will not cause any problem
as in that cycle we can still read old value in SQ.
(Though SQ entry may be written in that cycle)

* Now we use parallel op to build store data forward logic
* Further timing opt tbd

This reverts commit f5c6b070.