roq,commits: update commit io

src/main/scala/xiangshan/Bundle.scala

@@ -286,9 +286,13 @@ class CSRSpecialIO extends XSBundle {
 //  val mcommit = Input(UInt(3.W))
 //}
 
-class RoqCommit extends XSBundle {
-  val uop = new MicroOp
-  val isWalk = Bool()
+class RoqCommitIO extends XSBundle {
+  val isWalk = Output(Bool())
+  val valid = Vec(CommitWidth, Output(Bool()))
+  val uop = Vec(CommitWidth, Output(new MicroOp))
+
+  def hasWalkInstr = isWalk && valid.asUInt.orR
+  def hasCommitInstr = !isWalk && valid.asUInt.orR
 }
 
 class TlbFeedback extends XSBundle {

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -53,7 +53,7 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
       val exception = ValidIO(new MicroOp)
       val isInterrupt = Output(Bool())
       // to mem block
-      val commits = Vec(CommitWidth, ValidIO(new RoqCommit))
+      val commits = new RoqCommitIO
       val roqDeqPtr = Output(new RoqPtr)
     }
   })
@@ -96,7 +96,7 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
   brq.io.enqReqs <> decode.io.toBrq
   brq.io.exuRedirect <> io.fromIntBlock.exuRedirect
 
-  decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk
+  decBuf.io.isWalking := roq.io.commits.hasWalkInstr
   decBuf.io.redirect.valid <> redirectValid
   decBuf.io.redirect.bits <> redirect
   decBuf.io.out <> rename.io.in

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -53,7 +53,7 @@ class MemBlock
 
     val lsqio = new Bundle {
       val exceptionAddr = new ExceptionAddrIO // to csr
-      val commits = Flipped(Vec(CommitWidth, Valid(new RoqCommit))) // to lsq
+      val commits = Flipped(new RoqCommitIO) // to lsq
       val roqDeqPtr = Input(new RoqPtr) // to lsq
     }
   })

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -15,7 +15,7 @@ class RenameBypassInfo extends XSBundle {
 class Rename extends XSModule {
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
-    val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit)))
+    val roqCommits = Flipped(new RoqCommitIO)
     // from decode buffer
     val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl)))
     // to dispatch1
@@ -54,11 +54,11 @@ class Rename extends XSModule {
   def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = {
     {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)}
   }
-  val walkValid = Cat(io.roqCommits.map(_.valid)).orR && io.roqCommits(0).bits.isWalk
+  val walkValid = io.roqCommits.hasWalkInstr
   fpFreeList.walk.valid := walkValid
   intFreeList.walk.valid := walkValid
-  fpFreeList.walk.bits := PopCount(io.roqCommits.map(c => c.valid && needDestReg(true, c.bits.uop)))
-  intFreeList.walk.bits := PopCount(io.roqCommits.map(c => c.valid && needDestReg(false, c.bits.uop)))
+  fpFreeList.walk.bits := PopCount((0 until CommitWidth).map(i => io.roqCommits.valid(i) && needDestReg(true, io.roqCommits.uop(i))))
+  intFreeList.walk.bits := PopCount((0 until CommitWidth).map(i => io.roqCommits.valid(i) && needDestReg(false, io.roqCommits.uop(i))))
   fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready
   intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready
 
@@ -117,21 +117,21 @@ class Rename extends XSModule {
       // speculative inst write
       val specWen = freeList.req.allocReqs(i) && freeList.req.canAlloc && freeList.req.doAlloc
       // walk back write
-      val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop)
-      val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk
+      val commitDestValid = io.roqCommits.valid(i) && needDestReg(fp, io.roqCommits.uop(i))
+      val walkWen = commitDestValid && io.roqCommits.isWalk
 
       rat.specWritePorts(i).wen := specWen || walkWen
-      rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest)
-      rat.specWritePorts(i).wdata := Mux(specWen, freeList.req.pdests(i), io.roqCommits(i).bits.uop.old_pdest)
+      rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits.uop(i).ctrl.ldest)
+      rat.specWritePorts(i).wdata := Mux(specWen, freeList.req.pdests(i), io.roqCommits.uop(i).old_pdest)
 
       XSInfo(walkWen,
-        {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" +
+        {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits.uop(i).cf.pc)}" +
           p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
       )
 
-      rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk
-      rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest
-      rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest
+      rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk
+      rat.archWritePorts(i).addr := io.roqCommits.uop(i).ctrl.ldest
+      rat.archWritePorts(i).wdata := io.roqCommits.uop(i).pdest
 
       XSInfo(rat.archWritePorts(i).wen,
         {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" +
@@ -139,7 +139,7 @@ class Rename extends XSModule {
       )
 
       freeList.deallocReqs(i) := rat.archWritePorts(i).wen
-      freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest
+      freeList.deallocPregs(i) := io.roqCommits.uop(i).old_pdest
 
     }
 

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -53,7 +53,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     val exception = Output(new MicroOp)
     // exu + brq
     val exeWbResults = Vec(numWbPorts, Flipped(ValidIO(new ExuOutput)))
-    val commits = Vec(CommitWidth, Valid(new RoqCommit))
+    val commits = new RoqCommitIO
     val bcommit = Output(UInt(BrTagWidth.W))
     val roqDeqPtr = Output(new RoqPtr)
     val csr = new RoqCSRIO
@@ -127,15 +127,15 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   val hasBlockBackward = RegInit(false.B)
   val hasNoSpecExec = RegInit(false.B)
   // When blockBackward instruction leaves Roq (commit or walk), hasBlockBackward should be set to false.B
-  val blockBackwardLeave = Cat(io.commits.map(c => c.valid && c.bits.uop.ctrl.blockBackward)).orR || io.redirect.valid
-  when(blockBackwardLeave){ hasBlockBackward:= false.B }
+  val blockBackwardLeave = Cat((0 until CommitWidth).map(i => io.commits.valid(i) && io.commits.uop(i).ctrl.blockBackward)).orR
+  when(blockBackwardLeave || io.redirect.valid) { hasBlockBackward:= false.B }
   // When noSpecExec instruction commits (it should not be walked except when it has not entered Roq),
   // hasNoSpecExec should be set to false.B
-  val noSpecExecCommit = Cat(io.commits.map(c => c.valid && !c.bits.isWalk && c.bits.uop.ctrl.noSpecExec)).orR || io.redirect.valid
-  when(noSpecExecCommit){ hasNoSpecExec:= false.B }
+  val noSpecExecCommit = !io.commits.isWalk && Cat((0 until CommitWidth).map(i => io.commits.valid(i) && io.commits.uop(i).ctrl.noSpecExec)).orR
+  when(noSpecExecCommit || io.redirect.valid) { hasNoSpecExec:= false.B }
   // Assertion on that noSpecExec should never be walked since it's the only instruction in Roq.
   // Extra walk should be ok since noSpecExec has not enter Roq.
-  val walkNoSpecExec = Cat(io.commits.map(c => c.valid && c.bits.isWalk && c.bits.uop.ctrl.noSpecExec)).orR
+  val walkNoSpecExec = io.commits.isWalk && Cat((0 until CommitWidth).map(i => io.commits.valid(i) && io.commits.uop(i).ctrl.noSpecExec)).orR
   XSError(state =/= s_extrawalk && walkNoSpecExec, "noSpecExec should not walk\n")
 
   val validDispatch = io.enq.req.map(_.valid)
@@ -171,7 +171,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   // Writeback
   val firedWriteback = io.exeWbResults.map(_.fire())
   XSInfo(PopCount(firedWriteback) > 0.U, "writebacked %d insts\n", PopCount(firedWriteback))
-  for(i <- 0 until numWbPorts){
+  for(i <- 0 until numWbPorts) {
     when(io.exeWbResults(i).fire()){
       val wbIdxExt = io.exeWbResults(i).bits.uop.roqIdx
       val wbIdx = wbIdxExt.value
@@ -234,27 +234,31 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   // wiring to csr
   val fflags = WireInit(0.U.asTypeOf(new Fflags))
   val dirty_fs = WireInit(false.B)
-  for(i <- 0 until CommitWidth){
-    io.commits(i) := DontCare
+
+  io.commits.isWalk := state =/= s_idle
+  for (i <- 0 until CommitWidth) {
+    io.commits.valid(i) := false.B
+    io.commits.uop(i)   := DontCare
+
     switch(state){
       is(s_idle){
         val commitIdx = deqPtr + i.U
         val commitUop = microOp(commitIdx)
         val hasException = Cat(commitUop.cf.exceptionVec).orR() || intrEnable
-        val canCommit = if(i!=0) (io.commits(i-1).valid && !io.commits(i-1).bits.uop.ctrl.flushPipe) else true.B
+        val canCommit = if(i!=0) (io.commits.valid(i-1) && !io.commits.uop(i-1).ctrl.flushPipe) else true.B
         val v = valid(commitIdx)
         val w = writebacked(commitIdx)
-        io.commits(i).valid := v && w && canCommit && !hasException
-        io.commits(i).bits.uop := commitUop
+        io.commits.valid(i) := v && w && canCommit && !hasException
+        io.commits.uop(i) := commitUop
 
-        storeCommitVec(i) := io.commits(i).valid &&
+        storeCommitVec(i) := io.commits.valid(i) &&
           commitUop.ctrl.commitType === CommitType.STORE
 
-        cfiCommitVec(i) := io.commits(i).valid &&
+        cfiCommitVec(i) := io.commits.valid(i) &&
           !commitUop.cf.brUpdate.pd.notCFI
 
         val commitFflags = exuFflags(commitIdx)
-        when(io.commits(i).valid){
+        when(io.commits.valid(i)){
           when(commitFflags.asUInt.orR()){
             // update fflags
             fflags := exuFflags(commitIdx)
@@ -265,7 +269,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
           }
         }
 
-        XSInfo(io.commits(i).valid,
+        XSInfo(io.commits.valid(i),
           "retired pc %x wen %d ldest %d pdest %x old_pdest %x data %x fflags: %b\n",
           commitUop.cf.pc,
           commitUop.ctrl.rfWen,
@@ -275,7 +279,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
           debug_exuData(commitIdx),
           exuFflags(commitIdx).asUInt
         )
-        XSInfo(io.commits(i).valid && debug_exuDebug(commitIdx).isMMIO,
+        XSInfo(io.commits.valid(i) && debug_exuDebug(commitIdx).isMMIO,
           "difftest skiped pc0x%x\n",
           commitUop.cf.pc
         )
@@ -285,12 +289,12 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
         val idx = walkPtrVec(i).value
         val v = valid(idx)
         val walkUop = microOp(idx)
-        io.commits(i).valid := v && shouldWalkVec(i)
-        io.commits(i).bits.uop := walkUop
+        io.commits.valid(i) := v && shouldWalkVec(i)
+        io.commits.uop(i) := walkUop
         when(shouldWalkVec(i)){
           v := false.B
         }
-        XSInfo(io.commits(i).valid && shouldWalkVec(i), "walked pc %x wen %d ldst %d data %x\n",
+        XSInfo(io.commits.valid(i) && shouldWalkVec(i), "walked pc %x wen %d ldst %d data %x\n",
           walkUop.cf.pc,
           walkUop.ctrl.rfWen,
           walkUop.ctrl.ldest,
@@ -301,23 +305,22 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
       is(s_extrawalk){
         val idx = RenameWidth-i-1
         val walkUop = extraSpaceForMPR(idx)
-        io.commits(i).valid := usedSpaceForMPR(idx)
-        io.commits(i).bits.uop := walkUop
+        io.commits.valid(i) := usedSpaceForMPR(idx)
+        io.commits.uop(i) := walkUop
         state := s_walk
-        XSInfo(io.commits(i).valid, "use extra space walked pc %x wen %d ldst %d\n",
+        XSInfo(io.commits.valid(i), "use extra space walked pc %x wen %d ldst %d\n",
           walkUop.cf.pc,
           walkUop.ctrl.rfWen,
           walkUop.ctrl.ldest
         )
       }
     }
-    io.commits(i).bits.isWalk := state =/= s_idle
   }
 
   io.csr.fflags := fflags
   io.csr.dirty_fs := dirty_fs
 
-  val validCommit = io.commits.map(_.valid)
+  val validCommit = io.commits.valid
   val commitCnt = PopCount(validCommit)
   when(state===s_walk) {
     //exit walk state when all roq entry is commited
@@ -367,7 +370,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   }
 
   // instvalid field
-  
+
   // write
   // enqueue logic writes 6 valid
   for (i <- 0 until RenameWidth) {
@@ -379,7 +382,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   for(i <- 0 until CommitWidth){
     switch(state){
       is(s_idle){
-        when(io.commits(i).valid){valid(deqPtrExtPlus(i)) := false.B}
+        when(io.commits.valid(i)){valid(deqPtrExtPlus(i)) := false.B}
       }
       is(s_walk){
         val idx = walkPtrVec(i).value
@@ -390,7 +393,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     }
   }
 
-  // read 
+  // read
   // enqueue logic reads 6 valid
   // dequeue/walk logic reads 6 valid, dequeue and walk will not happen at the same time
   // rollback reads all valid? is it necessary?
@@ -412,15 +415,15 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
       writebacked(enqPtrValPlus(i)) := false.B
     }
   }
-  // writeback logic set numWbPorts writebacked to true 
-  for(i <- 0 until numWbPorts){
+  // writeback logic set numWbPorts writebacked to true
+  for(i <- 0 until numWbPorts) {
     when(io.exeWbResults(i).fire()){
       val wbIdxExt = io.exeWbResults(i).bits.uop.roqIdx
       val wbIdx = wbIdxExt.value
       writebacked(wbIdx) := true.B
     }
   }
-  // rollback: write all 
+  // rollback: write all
   // when rollback, reset writebacked entry to valid
   // when(io.memRedirect.valid) { // TODO: opt timing
   //   for (i <- 0 until RoqSize) {
@@ -447,8 +450,8 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   // all flagBkup will be used
 
   // exuFflags
-  // write: writeback logic set numWbPorts exuFflags 
-  for(i <- 0 until numWbPorts){
+  // write: writeback logic set numWbPorts exuFflags
+  for(i <- 0 until numWbPorts) {
     when(io.exeWbResults(i).fire()){
       val wbIdxExt = io.exeWbResults(i).bits.uop.roqIdx
       val wbIdx = wbIdxExt.value
@@ -468,7 +471,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   }
   XSDebug(false, true.B, "\n")
 
-  for(i <- 0 until RoqSize){
+  for(i <- 0 until RoqSize) {
     if(i % 4 == 0) XSDebug("")
     XSDebug(false, true.B, "%x ", microOp(i).cf.pc)
     XSDebug(false, !valid(i), "- ")
@@ -476,14 +479,14 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     XSDebug(false, valid(i) && !writebacked(i), "v ")
     if(i % 4 == 3) XSDebug(false, true.B, "\n")
   }
-  
+
   val id = roqDebugId()
   val difftestIntrNO = WireInit(0.U(XLEN.W))
   val difftestCause = WireInit(0.U(XLEN.W))
   ExcitingUtils.addSink(difftestIntrNO, s"difftestIntrNOfromCSR$id")
   ExcitingUtils.addSink(difftestCause, s"difftestCausefromCSR$id")
-  
-  if(!env.FPGAPlatform){ 
+
+  if(!env.FPGAPlatform) {
 
     //difftest signals
     val firstValidCommit = deqPtr + PriorityMux(validCommit, VecInit(List.tabulate(CommitWidth)(_.U)))
@@ -499,29 +502,29 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     for(i <- 0 until CommitWidth){
       // io.commits(i).valid
       val idx = deqPtr+i.U
-      val uop = io.commits(i).bits.uop
+      val uop = io.commits.uop(i)
       val DifftestSkipSC = false
       if(!DifftestSkipSC){
-        skip(i) := debug_exuDebug(idx).isMMIO && io.commits(i).valid
+        skip(i) := debug_exuDebug(idx).isMMIO && io.commits.valid(i)
       }else{
         skip(i) := (
-            debug_exuDebug(idx).isMMIO || 
+            debug_exuDebug(idx).isMMIO ||
             uop.ctrl.fuType === FuType.mou && uop.ctrl.fuOpType === LSUOpType.sc_d ||
             uop.ctrl.fuType === FuType.mou && uop.ctrl.fuOpType === LSUOpType.sc_w
-          ) && io.commits(i).valid
+          ) && io.commits.valid(i)
       }
-      wen(i) := io.commits(i).valid && uop.ctrl.rfWen && uop.ctrl.ldest =/= 0.U
+      wen(i) := io.commits.valid(i) && uop.ctrl.rfWen && uop.ctrl.ldest =/= 0.U
       wdata(i) := debug_exuData(idx)
       wdst(i) := uop.ctrl.ldest
       diffTestDebugLrScValid(i) := uop.diffTestDebugLrScValid
       wpc(i) := SignExt(uop.cf.pc, XLEN)
-      trapVec(i) := io.commits(i).valid && (state===s_idle) && uop.ctrl.isXSTrap
+      trapVec(i) := io.commits.valid(i) && (state===s_idle) && uop.ctrl.isXSTrap
       isRVC(i) := uop.cf.brUpdate.pd.isRVC
     }
 
-    val scFailed = !diffTestDebugLrScValid(0) && 
-      io.commits(0).bits.uop.ctrl.fuType === FuType.mou &&
-      (io.commits(0).bits.uop.ctrl.fuOpType === LSUOpType.sc_d || io.commits(0).bits.uop.ctrl.fuOpType === LSUOpType.sc_w)
+    val scFailed = !diffTestDebugLrScValid(0) &&
+      io.commits.uop(0).ctrl.fuType === FuType.mou &&
+      (io.commits.uop(0).ctrl.fuOpType === LSUOpType.sc_d || io.commits.uop(0).ctrl.fuOpType === LSUOpType.sc_w)
 
     val instrCnt = RegInit(0.U(64.W))
     instrCnt := instrCnt + retireCounter

src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala

@@ -244,7 +244,7 @@ class LsqWrappper extends XSModule with HasDCacheParameters {
     val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback store
     val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store
     val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
-    val commits = Flipped(Vec(CommitWidth, Valid(new RoqCommit)))
+    val commits = Flipped(new RoqCommitIO)
     val rollback = Output(Valid(new Redirect))
     val dcache = new DCacheLineIO
     val uncache = new DCacheWordIO

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -37,7 +37,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
     val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // FIXME: Valid() only
     val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback load
     val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
-    val commits = Flipped(Vec(CommitWidth, Valid(new RoqCommit)))
+    val commits = Flipped(new RoqCommitIO)
     val rollback = Output(Valid(new Redirect)) // replay now starts from load instead of store
     val dcache = new DCacheLineIO
     val uncache = new DCacheWordIO
@@ -67,8 +67,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
   val isFull = enqPtr === deqPtr && !sameFlag
   val allowIn = !isFull
 
-  val loadCommit = (0 until CommitWidth).map(i => io.commits(i).valid && !io.commits(i).bits.isWalk && io.commits(i).bits.uop.ctrl.commitType === CommitType.LOAD)
-  val mcommitIdx = (0 until CommitWidth).map(i => io.commits(i).bits.uop.lqIdx.value)
+  val loadCommit = (0 until CommitWidth).map(i => io.commits.valid(i) && !io.commits.isWalk && io.commits.uop(i).ctrl.commitType === CommitType.LOAD)
+  val mcommitIdx = (0 until CommitWidth).map(i => io.commits.uop(i).lqIdx.value)
 
   val tailMask = (((1.U((LoadQueueSize + 1).W)) << deqPtr).asUInt - 1.U)(LoadQueueSize - 1, 0)
   val headMask = (((1.U((LoadQueueSize + 1).W)) << enqPtr).asUInt - 1.U)(LoadQueueSize - 1, 0)
@@ -474,11 +474,11 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
 
   // setup misc mem access req
   // mask / paddr / data can be get from lq.data
-  val commitType = io.commits(0).bits.uop.ctrl.commitType
+  val commitType = io.commits.uop(0).ctrl.commitType
   io.uncache.req.valid := pending(deqPtr) && allocated(deqPtr) &&
     commitType === CommitType.LOAD &&
     io.roqDeqPtr === uop(deqPtr).roqIdx &&
-    !io.commits(0).bits.isWalk
+    !io.commits.isWalk
 
   io.uncache.req.bits.cmd  := MemoryOpConstants.M_XRD
   io.uncache.req.bits.addr := dataModule.io.rdata(deqPtr).paddr

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -34,23 +34,23 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReq))
     val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store
     val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
-    val commits = Flipped(Vec(CommitWidth, Valid(new RoqCommit)))
+    val commits = Flipped(new RoqCommitIO)
     val uncache = new DCacheWordIO
     val roqDeqPtr = Input(new RoqPtr)
     // val refill = Flipped(Valid(new DCacheLineReq ))
     val exceptionAddr = new ExceptionAddrIO
   })
-  
+
   val uop = Reg(Vec(StoreQueueSize, new MicroOp))
   // val data = Reg(Vec(StoreQueueSize, new LsqEntry))
   val dataModule = Module(new LSQueueData(StoreQueueSize, StorePipelineWidth))
-  dataModule.io := DontCare 
+  dataModule.io := DontCare
   val allocated = RegInit(VecInit(List.fill(StoreQueueSize)(false.B))) // sq entry has been allocated
   val datavalid = RegInit(VecInit(List.fill(StoreQueueSize)(false.B))) // non-mmio data is valid
   val writebacked = RegInit(VecInit(List.fill(StoreQueueSize)(false.B))) // inst has been writebacked to CDB
   val commited = Reg(Vec(StoreQueueSize, Bool())) // inst has been commited by roq
   val pending = Reg(Vec(StoreQueueSize, Bool())) // mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of roq
-  
+
   val enqPtrExt = RegInit(0.U.asTypeOf(new SqPtr))
   val deqPtrExt = RegInit(0.U.asTypeOf(new SqPtr))
   val enqPtr = enqPtrExt.value
@@ -59,9 +59,9 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
   val isEmpty = enqPtr === deqPtr && sameFlag
   val isFull = enqPtr === deqPtr && !sameFlag
   val allowIn = !isFull
-  
-  val storeCommit = (0 until CommitWidth).map(i => io.commits(i).valid && !io.commits(i).bits.isWalk && io.commits(i).bits.uop.ctrl.commitType === CommitType.STORE)
-  val mcommitIdx = (0 until CommitWidth).map(i => io.commits(i).bits.uop.sqIdx.value)
+
+  val storeCommit = (0 until CommitWidth).map(i => io.commits.valid(i) && !io.commits.isWalk && io.commits.uop(i).ctrl.commitType === CommitType.STORE)
+  val mcommitIdx = (0 until CommitWidth).map(i => io.commits.uop(i).sqIdx.value)
 
   val tailMask = (((1.U((StoreQueueSize + 1).W)) << deqPtr).asUInt - 1.U)(StoreQueueSize - 1, 0)
   val headMask = (((1.U((StoreQueueSize + 1).W)) << enqPtr).asUInt - 1.U)(StoreQueueSize - 1, 0)
@@ -94,7 +94,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     enqPtrExt := enqPtrExt + PopCount(firedDispatch)
     XSInfo("dispatched %d insts to sq\n", PopCount(firedDispatch))
   }
-    
+
   // writeback store
   (0 until StorePipelineWidth).map(i => {
     dataModule.io.wb(i).wen := false.B
@@ -163,7 +163,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     // TODO: do not select according to seq, just select 2 valid bit randomly
     val firstSelVec = valid
     val notFirstVec = Wire(Vec(valid.length, Bool()))
-    (0 until valid.length).map(i => 
+    (0 until valid.length).map(i =>
       notFirstVec(i) := (if(i != 0) { valid(i) || !notFirstVec(i) } else { false.B })
     )
     val secondSelVec = VecInit((0 until valid.length).map(i => valid(i) && !notFirstVec(i)))
@@ -229,7 +229,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
 
     val differentFlag = deqPtrExt.flag =/= io.forward(i).sqIdx.flag
     val forwardMask = ((1.U((StoreQueueSize + 1).W)) << io.forward(i).sqIdx.value).asUInt - 1.U
-    val storeWritebackedVec = WireInit(VecInit(Seq.fill(StoreQueueSize)(false.B))) 
+    val storeWritebackedVec = WireInit(VecInit(Seq.fill(StoreQueueSize)(false.B)))
     for (j <- 0 until StoreQueueSize) {
       storeWritebackedVec(j) := datavalid(j) && allocated(j) // all datavalid terms need to be checked
     }
@@ -241,7 +241,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     // do real fwd query
     dataModule.io.forwardQuery(
       channel = i,
-      paddr = io.forward(i).paddr, 
+      paddr = io.forward(i).paddr,
       needForward1 = needForward1,
       needForward2 = needForward2
     )
@@ -279,20 +279,20 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
   })
 
   // Memory mapped IO / other uncached operations
-  
+
   // setup misc mem access req
   // mask / paddr / data can be get from sq.data
-  val commitType = io.commits(0).bits.uop.ctrl.commitType 
+  val commitType = io.commits.uop(0).ctrl.commitType
   io.uncache.req.valid := pending(deqPtr) && allocated(deqPtr) &&
     commitType === CommitType.STORE &&
     io.roqDeqPtr === uop(deqPtr).roqIdx &&
-    !io.commits(0).bits.isWalk
+    !io.commits.isWalk
 
   io.uncache.req.bits.cmd  := MemoryOpConstants.M_XWR
-  io.uncache.req.bits.addr := dataModule.io.rdata(deqPtr).paddr 
+  io.uncache.req.bits.addr := dataModule.io.rdata(deqPtr).paddr
   io.uncache.req.bits.data := dataModule.io.rdata(deqPtr).data
   io.uncache.req.bits.mask := dataModule.io.rdata(deqPtr).mask
-  
+
   io.uncache.req.bits.meta.id       := DontCare // TODO: // FIXME
   io.uncache.req.bits.meta.vaddr    := DontCare
   io.uncache.req.bits.meta.paddr    := dataModule.io.rdata(deqPtr).paddr
@@ -301,18 +301,18 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
   io.uncache.req.bits.meta.tlb_miss := false.B
   io.uncache.req.bits.meta.mask     := dataModule.io.rdata(deqPtr).mask
   io.uncache.req.bits.meta.replay   := false.B
-  
+
   io.uncache.resp.ready := true.B
-  
+
   when(io.uncache.req.fire()){
     pending(deqPtr) := false.B
   }
-  
+
   when(io.uncache.resp.fire()){
     datavalid(deqPtr) := true.B // will be writeback to CDB in the next cycle
     // TODO: write back exception info
   }
-  
+
   when(io.uncache.req.fire()){
     XSDebug("uncache req: pc %x addr %x data %x op %x mask %x\n",
       uop(deqPtr).cf.pc,